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21. 发明专利

JP2011222566A Electronic component and manufacturing method of the same 有权
标题翻译：电子元件及其制造方法
公开(公告)号：JP2011222566A
公开(公告)日：2011-11-04
申请号：JP2010086484
申请日：2010-04-02
申请人： Fujitsu Ltd , 富士通株式会社
发明人： ABE TOMOYUKI , MIZUKOSHI MASATAKA
IPC分类号： H01L23/12 , H05K3/20 , H05K3/46
CPC分类号： H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2924/15311 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To form a conductor pattern finer than a conventional one in an electronic component and a manufacturing method of the electronic component.SOLUTION: The manufacturing method of the electronic component includes a process for forming a resin layer 6 on a conductor foil 4, a process for pressing a conductor plate 2 where a projected pattern 2w is formed on one main face 2x on the resin layer 6 and embedding the projected pattern 2w in the resin layer 6, a process for forming through holes 6a in the conductor plate 2, the resin layer 6 and the conductor foil 4 respectively, a process for embedding a conductor 11 in the through hole 6a, a process for forming a first conductor pattern 4x which is electrically connected to the conductor 11 by patterning the conductor foil 4 and a process for forming a second conductor pattern 2z which is electrically connected to the first conductor pattern 4x via the conductor 11 in the resin layer 6 by polishing, CMP or grinding the other main face 2y of the conductor plate 2 until the resin layer 6 appears.
摘要翻译：要解决的问题：在电子部件中形成比以往更细的导体图案和电子部件的制造方法。解决方案：电子部件的制造方法包括在导体箔4上形成树脂层6的工序，在树脂的一个主面2上形成突出图案2w的导体板2的按压方法层6并将投射图案2w嵌入树脂层6中，分别在导体板2，树脂层6和导体箔4中形成通孔6a的工艺，将导体11嵌入通孔6a中的工艺形成通过图案化导体箔4而电连接到导体11的第一导体图案4x的处理和用于形成第二导体图案2z的工艺，该第二导体图案2z通过导体11电连接到第一导体图案4x 树脂层6通过抛光，CMP或研磨导体板2的另一个主面2y直到树脂层6出现。版权所有（C）2012，JPO＆INPIT

22. 发明专利

JP2011210913A Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2011210913A
公开(公告)日：2011-10-20
申请号：JP2010076592
申请日：2010-03-30
申请人： Fujitsu Ltd , 富士通株式会社
发明人： IMAIZUMI NOBUHIRO , AKAMATSU TOSHIYA , MIZUKOSHI MASATAKA
IPC分类号： H01L25/065 , H01L21/3205 , H01L21/60 , H01L23/52 , H01L25/07 , H01L25/18
CPC分类号： H01L24/05 , H01L2224/04042 , H01L2224/48463 , H01L2224/48465 , H01L2224/49175 , H01L2224/73203 , H01L2224/73207 , H01L2924/00014 , H01L2924/01004 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01067 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/00 , H01L2224/05556
摘要： PROBLEM TO BE SOLVED: To provide a means for manufacturing a semiconductor device at low cost, the semiconductor device that is formed by laminating two or more semiconductor elements.SOLUTION: The semiconductor device 31 has a first semiconductor element 10 mounted on a circuit board 1 and a connection terminal 26 of a second semiconductor element 20 joined to a solder bump 17 on a first electrode pad 14 of the first semiconductor element 10. Second and third electrode pads 15 and 16 of the first semiconductor element 10 are electrically connected to the circuit board 1 through a wire 18. The distance H0 between the first and second semiconductor elements 10 and 20 is so set as being ≥the height H1 of the wire 18 loop by the tall connection terminal 26.
摘要翻译：要解决的问题：为了提供一种以低成本制造半导体器件的方法，通过层叠两个或更多个半导体元件形成的半导体器件。解决方案：半导体器件31具有安装在电路板1上的第一半导体元件10 以及连接到第一半导体元件10的第一电极焊盘14上的焊料凸块17的第二半导体元件20的连接端子26.第一半导体元件10的第二和第三电极焊盘15和16电连接到电路第一半导体元件10和第二半导体元件20之间的距离H0被高连接端子26设定为线18的高度H1。

23. 发明专利

JP2008238388A Machining device and manufacturing method 有权
标题翻译：加工设备和制造方法
公开(公告)号：JP2008238388A
公开(公告)日：2008-10-09
申请号：JP2007086824
申请日：2007-03-29
申请人： Fujitsu Ltd , 富士通株式会社
发明人： AWANO YUJI , MIZUKOSHI MASATAKA , IWAI DAISUKE , MATSUSHITA NAOHISA , NISHIYAMA SHUSAKU
IPC分类号： B23B27/14 , B23B51/00 , B23C5/16
摘要： PROBLEM TO BE SOLVED: To provide a machining part having high wear resistance and machining accuracy below a submicron level.
SOLUTION: A carbon nanotube 14 is formed from a catalytic metal layer 13 formed in contact with a core part 12 along a side portion of the core part 12 and the carbon nanotube 14 is formed with a fixation layer 15. A machining device 10 having high wear resistance and capable of performing accurate machining of a nanometer order is provided by using the side portion of the nanotube 14 as the machining part 11.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供具有低于亚微米级的高耐磨性和加工精度的加工部件。解决方案：碳纳米管14由沿着核心部分12的侧部与核心部分12接触形成的催化金属层13形成，并且碳纳米管14形成有固定层15.加工装置通过使用纳米管14的侧部作为加工部11，提供具有高耐磨性并能够进行纳米级精确加工的10。版权所有（C）2009，JPO＆INPIT

24. 发明专利

JP2008211241A Method for processing base 有权
标题翻译：加工基地方法
公开(公告)号：JP2008211241A
公开(公告)日：2008-09-11
申请号：JP2008112130
申请日：2008-04-23
申请人： Fujitsu Ltd , 富士通株式会社
发明人： MIZUKOSHI MASATAKA , IMAIZUMI NOBUHIRO , ISHIZUKI YOSHIKATSU
IPC分类号： H01L21/60 , H01L25/065 , H01L25/07 , H01L25/18
CPC分类号： H01L21/563 , H01L23/3114 , H01L24/11 , H01L24/12 , H01L24/16 , H01L24/17 , H01L24/29 , H01L24/81 , H01L24/83 , H01L2224/05001 , H01L2224/05022 , H01L2224/05124 , H01L2224/05139 , H01L2224/05144 , H01L2224/05147 , H01L2224/05155 , H01L2224/05184 , H01L2224/05572 , H01L2224/05611 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/05684 , H01L2224/1147 , H01L2224/13099 , H01L2224/16225 , H01L2224/29111 , H01L2224/2919 , H01L2224/32225 , H01L2224/45139 , H01L2224/45144 , H01L2224/73104 , H01L2224/73203 , H01L2224/73204 , H01L2224/81801 , H01L2224/83191 , H01L2224/83194 , H01L2224/838 , H01L2924/00011 , H01L2924/00013 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01022 , H01L2924/01024 , H01L2924/01027 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01043 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01056 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/0132 , H01L2924/014 , H01L2924/0665 , H01L2924/07802 , H01L2924/0781 , H01L2924/13091 , H01L2924/1579 , H01L2924/19041 , H01L2924/00 , H01L2924/00015 , H01L2224/29099 , H01L2224/48 , H01L2924/013 , H01L2924/01049
摘要： PROBLEM TO BE SOLVED: To achieve a semiconductor device having high reliability, which can form metal terminals at low cost and which can be mounted at low damage, the metal terminals having uniform height and smoothness and allowing connection under low load. SOLUTION: Electrodes 5 and an insulating film 6 are both formed of materials having such a property that: they are solid and do not exhibit the adhesiveness at room temperature; they exhibit the adhesiveness at least at a first temperature higher than the room temperature; and they cure at least at a second temperature higher than the first temperature. Cutting work is performed by using a hard bite composed of diamond or the like so that the surfaces of the electrodes 5 and the insulating film 6 of a semiconductor chip 1a may become flat continuously and then planarization is performed. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：解决的问题为了实现具有高可靠性的半导体器件，其可以以低成本形成金属端子并且可以以低损伤安装，金属端子具有均匀的高度和平滑度并且允许在低负载下连接。电极5和绝缘膜6均由具有以下特性的材料形成：它们是固体并且在室温下不表现出粘合性; 它们至少在高于室温的第一温度下表现出粘合性; 并且它们至少在高于第一温度的第二温度下固化。通过使用由金刚石等构成的硬质咬合来进行切削加工，使得半导体芯片1a的电极5和绝缘膜6的表面可以连续变平，然后进行平坦化。版权所有（C）2008，JPO＆INPIT

25. 发明专利

JP2008084951A Manufacturing method of semiconductor device 有权
标题翻译：半导体器件的制造方法
公开(公告)号：JP2008084951A
公开(公告)日：2008-04-10
申请号：JP2006260852
申请日：2006-09-26
申请人： Fujitsu Ltd , 富士通株式会社
发明人： SAKAI TAIJI , MIZUKOSHI MASATAKA , HAYASAKA NOBORU , TESHIROGI KAZUO
IPC分类号： H01L21/60
CPC分类号： H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2224/81907 , H01L2224/83907 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To surely achieve bonding between a semiconductor substrate and a circuit substrate. SOLUTION: An insulating material is buried between electrodes respectively formed at each front surface of the semiconductor substrate and the circuit substrate forming a pair of substrates. The semiconductor substrate is inclined for the circuit substrate and is temporarily fixed thereto under a first temperature for an insulating material to show its bonding property. A plurality of substrates forming a pair thereof fixed temporarily are evacuated to a vacuum state. A pair of substrates are bonded to maintain the pressure by uniformly applying the pressure to the front surface of a plurality of substrates forming a pair fixed temporarily. Moreover, the bonded insulating materials are hardened under a second temperature for hardening the insulating material and metal bonding occurs between the bonded electrodes under a third temperature wherein the electrodes cause solid-state diffusion with each other or the electrodes are fused with each other. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：确实实现半导体基板和电路基板之间的接合。解决方案：绝缘材料被埋在分别形成在半导体衬底的每个前表面的电极和形成一对衬底的电路衬底之间。半导体基板对于电路基板倾斜，并且在绝缘材料的第一温度下暂时固定到其上以显示其接合特性。临时形成一对的多个基板被抽真空至真空状态。通过对形成暂时固定的一对的多个基板的前表面均匀地施加压力，结合一对基板来保持压力。此外，接合绝缘材料在用于硬化绝缘材料的第二温度下硬化，并且在第三温度下发生在接合电极之间的金属接合，其中电极彼此引起固态扩散或电极彼此熔合。版权所有（C）2008，JPO＆INPIT

26. 发明专利

JP2007311700A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2007311700A
公开(公告)日：2007-11-29
申请号：JP2006141504
申请日：2006-05-22
申请人： Fujitsu Ltd , 富士通株式会社
发明人： AWANO YUJI , MIZUKOSHI MASATAKA , IWAI DAISUKE , NAKAMURA TOMOJI
IPC分类号： H01L21/60
CPC分类号： H01L23/49811 , H01L21/6835 , H01L23/49877 , H01L24/03 , H01L24/11 , H01L24/12 , H01L24/16 , H01L24/72 , H01L24/73 , H01L24/90 , H01L24/91 , H01L2224/03505 , H01L2224/0401 , H01L2224/11003 , H01L2224/13078 , H01L2224/13099 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2224/81901 , H01L2224/81904 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01022 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01079 , H01L2924/014 , Y10S977/72 , Y10S977/721 , Y10S977/722 , Y10S977/762 , Y10S977/763 , Y10S977/766 , Y10S977/784 , Y10S977/932 , Y10S977/936 , Y10S977/937 , Y10S977/938 , Y10S977/963 , H01L2924/00 , H01L2224/72
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device in which a semiconductor chip can be mounted to a mounting substrate and easily detached.
SOLUTION: A plurality of conductive pads (2) are formed on the mounting surface of the mounting substrate (1). When the main surface of the semiconductor chip (10), conductive pads (11) are formed on positions of the main surface corresponding to the mounting substrate. A plurality of conductive nano-tubes (12) extend from one of the conductive pad of the mounting substrate and the conductive pad of the semiconductor chip. In a state that the tip of each of the conductive nano-tubes contacts with the corresponding conductive pad having no conductive tube, a pressing mechanism (3) presses the conductive chip to the mounting substrate, and restrains the position of the semiconductor chip in the mounting surface. In this way, the semiconductor chips can be mounted to the semiconductor substrate.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供一种其中可以将半导体芯片安装到安装基板并容易分离的半导体器件。解决方案：在安装基板（1）的安装表面上形成多个导电焊盘（2）。当半导体芯片（10）的主表面形成在与安装基板对应的主表面的位置时，导电焊盘（11）。多个导电纳米管（12）从安装基板的导电焊盘和半导体芯片的导电焊盘之一延伸。在每个导电纳米管的尖端与不具有导电管的相应导电焊盘接触的状态下，按压机构（3）将导电芯片按压到安装基板，并且将半导体芯片的位置限制在安装面。以这种方式，可以将半导体芯片安装到半导体衬底。版权所有（C）2008，JPO＆INPIT

27. 发明专利

JP2006344671A MULTILAYER CIRCUIT BOARD AND ITS MANUFACTURING METHOD 审中-公开
公开(公告)号：JP2006344671A
公开(公告)日：2006-12-21
申请号：JP2005167160
申请日：2005-06-07
申请人： FUJITSU LTD
发明人： KURASHINA MAMORU , MIZUKOSHI MASATAKA , ABE TOMOYUKI
IPC分类号： H05K3/46
摘要： PROBLEM TO BE SOLVED: To produce a multilayer wiring circuit board with highly reliable stack vias in a landless way with narrow pitch, while the connecting surface of the vias and the bonded surface of an insulating layer are arranged on the different planes. SOLUTION: The stack vias has such a structure that electric conductors are interconnected up and down in the shape of a cone pillar making a convex trapezoid downward in a multilayer insulating layer. The multilayer circuit board is constituted such that the connecting surface of the vias and the bonded surface of an insulating layer are arranged on the different planes. A film which has a photoresist layer on the upper layer and an insulating resin layer on the lower layer is stuck to the substrate. Both the layers are opened in block by the laser method for providing an opening in the shape of a cone pillar making a convex trapezoid so that a metal electric conductor may be embedded there by plating. Thus, the vias are formed by removing the photoresist layer. The manufacturing method for forming the stack vias is applied by repeating this process. COPYRIGHT: (C)2007,JPO&INPIT

28. 发明专利

JP2006261510A Electronic device and its manufacturing method 有权
标题翻译：电子设备及其制造方法
公开(公告)号：JP2006261510A
公开(公告)日：2006-09-28
申请号：JP2005079048
申请日：2005-03-18
申请人： Fujitsu Ltd , 富士通株式会社
发明人： NAKAGAWA KANAE , MIZUKOSHI MASATAKA
IPC分类号： H01L23/12
CPC分类号： H01L21/4853 , H01L21/4846 , H01L21/563 , H01L23/49811 , H01L23/49827 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/81 , H01L24/83 , H01L24/90 , H01L2224/05001 , H01L2224/05022 , H01L2224/05147 , H01L2224/05572 , H01L2224/05647 , H01L2224/05666 , H01L2224/1147 , H01L2224/1184 , H01L2224/13099 , H01L2224/13147 , H01L2224/16225 , H01L2224/16235 , H01L2224/2784 , H01L2224/2919 , H01L2224/32225 , H01L2224/73104 , H01L2224/73203 , H01L2224/73204 , H01L2224/81894 , H01L2224/83192 , H01L2224/83194 , H01L2224/83855 , H01L2224/83856 , H01L2224/9202 , H01L2924/01005 , H01L2924/01006 , H01L2924/01015 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/0665 , H01L2924/14 , H01L2924/15174 , H01L2924/15311 , H01L2924/19041 , H01L2924/00 , H01L2924/00014
摘要： PROBLEM TO BE SOLVED: To provide an electronic device and its manufacturing method, wherein electrodes can certainly be joined to each other without deteriorating a reliability. SOLUTION: This electronic device has a first substrate 10; a first electrode 22 formed on one primary face of the first substrate 10; a first resin layer 32 which is formed so that the first electrode 22 is embedded on the one primary face of the first substrate 10 and is made of a thermosetting resin; a second substrate 12 arranged opposite to the one primary face of the first substrate 10; a second electrode 24 which is formed on one primary face of a second substrate 12 opposite to the first substrate 10 corresponding to the first electrode 22, and is joined to the first electrode 22; and a thermosetting second resin layer 42 which is formed so that the second electrode 24 is embedded on the one primary face of the second substrate 12, is made of a thermosetting resin, and is adhered to the first resin layer 32. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：为了提供电子装置及其制造方法，其中电极可以肯定地彼此接合而不劣化可靠性。解决方案：该电子设备具有第一基板10; 形成在第一基板10的一个主面上的第一电极22; 第一树脂层32，其形成为使得第一电极22嵌入在第一基板10的一个主面上并由热固性树脂制成; 与第一基板10的一个主面相对布置的第二基板12; 第二电极24，形成在与第一电极22对应的与第一基板10相对的第二基板12的一个主面上，并与第一电极22接合; 以及形成为使第二电极24嵌入第二基板12的一个主面上的热固性第二树脂层42由热固性树脂制成，并且粘附到第一树脂层32上。（C）2006，JPO＆NCIPI

29. 发明专利

JP2002141367A METHOD FOR FORMING BUMP, ELECTRONIC COMPONENT AND SOLDER PASTE 失效
公开(公告)号：JP2002141367A
公开(公告)日：2002-05-17
申请号：JP2000363235
申请日：2000-11-29
申请人： FUJITSU LTD
发明人： SAKUYAMA SEIKI , YAMAGISHI YASUO , MIZUKOSHI MASATAKA
IPC分类号： H01L25/18 , B23K35/24 , B23K35/363 , H01L21/48 , H01L21/60 , H01L21/68 , H01L23/498 , H01L25/065 , H01L25/07 , H05K3/34
摘要： PROBLEM TO BE SOLVED: To form bumps having small height unevenness at a low cost for a plurality of electrode pads provided on a base plate. SOLUTION: A method for forming the bumps comprises a step of providing masks having a plurality of openings corresponding to the plurality of electrode pads on the base plate having the plurality of electrode pads to a state in which the pads are exposed, a step of filling a solder paste in the openings, and a step of heat treating the paste. In this method, as a solder powder of the solder paste, a solder powder containing powder particles of a ratio of a particle size larger than a thickness of the mask to 1.5 times as large as the thickness of the mask of 10 wt.% or less is used. It is further preferred that as the solder powder, the powder containing particles of a ratio of a particle size of 40% or more of an opening size of the opening of 10 wt.% or less is used and the powder containing particles of a ratio of a particle size of 40 to 100% of the thickness of the mask of 30 wt.% or more is used.

30. 发明专利

JPH10261677A TEST METHOD FOR SEMICONDUCTOR WAFER 失效
公开(公告)号：JPH10261677A
公开(公告)日：1998-09-29
申请号：JP6511797
申请日：1997-03-18
申请人： FUJITSU LTD
发明人： MIZUKOSHI MASATAKA , AKASAKI HIDEHIKO
IPC分类号： H01L21/66 , H01L21/822 , H01L27/04
摘要： PROBLEM TO BE SOLVED: To perform full specification test and burn-in with good reliability collectively for a plurality of semiconductor chips at the stage of a semiconductor wafer, in a test method for a semiconductor wafer. SOLUTION: This method has a process 10 for forming a temporary auxiliary film 30 for a test which is performed prior to test, a test process 11 which is performed, with a probe 41 applied to the temporary auxiliary film 30 for the test, and a process 13 of temporarily peeling off the auxiliary film for test which is performed to peel off the temporary auxiliary film 30 for the test after test. The temporary auxiliary film 30 for test has a group of electrodes for test, where a plurality of electrodes 32 for test are drawn up regularly, at the surface, and has a wiring pattern 35 for electrically connecting each electrode 32 for test of the group 31 of electrodes 31 for test with the separate element electrodes of the above plurality of semiconductor elements 21. The probe pins 42 of a probe 41 are in a row, corresponding to each electrode 32 for test of the group 31 of the electrodes for test.

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