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21. 发明授权

US07342789B2 Method and apparatus for cooling an equipment enclosure through closed-loop, liquid-assisted air cooling in combination with direct liquid cooling 有权
标题翻译：通过闭环，液体辅助空气冷却与直接液体冷却结合来冷却设备外壳的方法和设备
公开(公告)号：US07342789B2
公开(公告)日：2008-03-11
申请号：US11427384
申请日：2006-06-29
申请人： Shawn A. Hall , Shurong Tian , Paul W. Coteus , John P. Karidis , Evan G. Colgan , Robert W. Guernsey, Jr.
发明人： Shawn A. Hall , Shurong Tian , Paul W. Coteus , John P. Karidis , Evan G. Colgan , Robert W. Guernsey, Jr.
IPC分类号： H05K7/20 , F28D15/00 , F28F7/00
CPC分类号： H05K7/20754 , G06F1/20 , G06F2200/201
摘要： A method and an apparatus for cooling, preferably within an enclosure, a diversity of heat-generating components, with at least some of the components having high-power densities and others having low-power densities. Heat generated by the essentially relatively few high-power-density components, such as microprocessor chips for example, is removed by direct liquid cooling, whereas heat generated by the more numerous low-power or low-watt-density components, such as memory chips for example, is removed by liquid-assisted air cooling in the form of a closed loop comprising a plurality of heating and cooling zones that alternate along the air path.
摘要翻译：优选地在外壳内冷却发热部件的多样性的方法和装置，其中至少一些部件具有高功率密度，而其它部件具有低功率密度。由基本相对较少的高功率密度组件（例如微处理器芯片）产生的热量通过直接液体冷却而被去除，而由更多的低功率或低功率密度组件产生的热量，例如存储芯片例如，通过液体辅助空气冷却以封闭回路的形式除去，包括沿着空气路径交替的多个加热和冷却区域。

22. 发明授权

US07180179B2 Thermal interposer for thermal management of semiconductor devices 失效
标题翻译：用于半导体器件热管理的热插入器
公开(公告)号：US07180179B2
公开(公告)日：2007-02-20
申请号：US10872575
申请日：2004-06-18
申请人： Lawrence S. Mok , Evan G. Colgan , Minhua Lu , Da-Yuan Shih
发明人： Lawrence S. Mok , Evan G. Colgan , Minhua Lu , Da-Yuan Shih
IPC分类号： H01L23/34 , H01L23/495
CPC分类号： H01L23/427 , H01L2224/16 , H01L2224/16225 , H01L2224/73253 , H01L2924/01019 , H01L2924/01078 , H01L2924/01322 , H01L2924/09701 , H01L2924/10158 , H01L2924/15311
摘要： A thermal interposer is provided for attachment to a surface of a semiconductor device. In one embodiment, the thermal interposer includes an upper plate having a bottom surface with a plurality of grooves and made of a material having high thermal conductivity, and a lower plate having a top surface with a plurality of grooves and made of a material having a coefficient of thermal expansion that is substantially the same as the coefficient of thermal expansion of the material of a semiconductor device that is bonded to the bottom surface of the lower plate. The bottom surface of the upper plate is hermetically bonded to the top surface of the lower plate so that a vapor chamber is formed by the upper and lower plates, and walls of the grooves on the top surface of the lower plate extend to within less than 250 microns from walls of the grooves on the bottom surface of the upper plate comprise a plurality of second walls the first walls.
摘要翻译：提供了用于附接到半导体器件的表面的热插入件。在一个实施例中，热插入件包括具有多个凹槽并由具有高导热性的材料制成的底表面的上板，以及具有多个凹槽的顶表面的下板，并由具有热膨胀系数与结合到下板的底面的半导体器件的材料的热膨胀系数基本相同。上板的底面与下板的顶面密封，从而通过上板和下板形成蒸气室，下板顶表面上的槽的壁延伸到小于在上板的底表面上的槽的壁250微米包括多个第二壁和第一壁。

23. 发明授权

US07128472B2 Method and apparatus for providing optoelectronic communication with an electronic device 有权
标题翻译：用于与电子设备进行光电通信的方法和设备
公开(公告)号：US07128472B2
公开(公告)日：2006-10-31
申请号：US10631933
申请日：2003-07-31
申请人： Alan F. Benner , Evan G. Colgan , How Tzu Lin , John H. Magerlein , Frank L. Pompeo , Subhash L. Shinde , Daniel J. Stigliani, Jr.
发明人： Alan F. Benner , Evan G. Colgan , How Tzu Lin , John H. Magerlein , Frank L. Pompeo , Subhash L. Shinde , Daniel J. Stigliani, Jr.
IPC分类号： G02B6/42 , G02B6/36 , G02B6/43
CPC分类号： G02B6/4201 , G02B6/4246 , G02B6/4249 , G02B6/4268 , G02B6/4281 , G02B6/4283 , G02B6/4292
摘要： An optoelectronic assembly for a computer system includes an electronic chip(s), a substrate, an electrical signaling medium, an optoelectronic transducer, and an optical coupling guide. The electronic chip(s) is in communication with the substrate, which is in communication with a first end of the electrical signaling medium. A second end of the electrical signaling medium is in communication with the optoelectronic transducer, and includes the optical coupling guide for aligning an optical signaling medium with the optoelectronic transducer. An electrical signal from the electronic chip is communicated to the optoelectronic transducer via the substrate and the electrical signaling medium. The optical transducer and electronic chip(s) share a common heat spreader, and communication to other groups of electronic chip(s) is done without the need for communication via a second level electrical package.
摘要翻译：用于计算机系统的光电组件包括电子芯片，基板，电信号介质，光电转换器和光耦合引导件。电子芯片与基板通信，该基板与电信号介质的第一端连通。电信令介质的第二端与光电换能器通信，并且包括用于使光信号介质与光电换能器对准的光耦合引导件。来自电子芯片的电信号通过衬底和电信令介质传送到光电换能器。光学传感器和电子芯片共享共同的散热器，并且完成与其他电子芯片组的通信，而不需要通过第二级电气封装进行通信。

24. 发明授权

US06815270B2 Thin film transistor formed by an etching process with high anisotropy 有权
标题翻译：通过具有高各向异性的蚀刻工艺形成的薄膜晶体管
公开(公告)号：US06815270B2
公开(公告)日：2004-11-09
申请号：US10438725
申请日：2003-05-15
申请人： Takatoshi Tsujimura , Masatomo Takeichi , Kai R. Schleupen , Evan G. Colgan
发明人： Takatoshi Tsujimura , Masatomo Takeichi , Kai R. Schleupen , Evan G. Colgan
IPC分类号： H01L2100
CPC分类号： H01L27/12 , H01L27/124 , H01L27/1248 , H01L29/66765 , Y10S438/90
摘要： The present invention discloses a thin film transistor and a process for forming thereof by a high anisotropy etching process. A thin film transistor according to the present invention comprises a transistor element including a gate electrode, a gate insulating layer, a semiconductor layer, and source and drain electrodes; a passivation layer being deposited on the layers and having first openings for contact holes; and an interlayer insulator extending along with the passivation layer and having second openings for the contact holes, the first openings and the second openings being aligned each other over the substrate, wherein an electrical conductive layer is deposited on an inner wall of the contact hole and the inner wall is formed by the first and second openings tapered smoothly and continuously through an anisotropic etching process.
摘要翻译：本发明公开了一种薄膜晶体管及其通过高各向异性蚀刻工艺形成的方法。根据本发明的薄膜晶体管包括晶体管元件，其包括栅极电极，栅极绝缘层，半导体层以及源极和漏极电极; 钝化层沉积在层上并具有用于接触孔的第一开口; 以及与所述钝化层一起延伸并具有用于所述接触孔的第二开口的层间绝缘体，所述第一开口和所述第二开口在所述衬底上彼此对准，其中导电层沉积在所述接触孔的内壁上，并且内壁由第一和第二开口形成，其平滑且连续地通过各向异性蚀刻工艺而逐渐变细。

25. 发明授权

US06713786B2 Thin film transistors with self-aligned transparent pixel electrode 有权
标题翻译：具有自对准透明像素电极的薄膜晶体管
公开(公告)号：US06713786B2
公开(公告)日：2004-03-30
申请号：US10348288
申请日：2003-01-21
申请人： Evan G. Colgan , Kai R. Schleupen , Takatoshi Tsujimura
发明人： Evan G. Colgan , Kai R. Schleupen , Takatoshi Tsujimura
IPC分类号： H01L2904
CPC分类号： G02F1/136227 , G02F1/1368
摘要： A pixel cell has a thin film transistor structure formed on a substrate. A signal conductor is patterned on the thin film transistor structure, and a first patterned layer of a transparent conductive material covers the signal conductor. The first patterned layer provides a pattern employed in etching a channel region of the thin film transistor structure. A dielectric layer is formed over the pixel cell and includes a via hole down to the first patterned layer of the transparent conductive material. A second layer of transparent conductive material extends through the via hole to contact the first patterned layer wherein the second layer is self-aligned to the transistor structure.
摘要翻译：像素单元具有形成在基板上的薄膜晶体管结构。在薄膜晶体管结构上图形化信号导体，并且透明导电材料的第一图案化层覆盖信号导体。第一图案化层提供了在蚀刻薄膜晶体管结构的沟道区域中使用的图案。介电层形成在像素单元的上方，并且包括通向透明导电材料的第一图案化层的通孔。第二层透明导电材料延伸穿过通孔以接触第一图案化层，其中第二层与晶体管结构自对准。

26. 发明授权

US5281485A Structure and method of making Alpha-Ta in thin films 失效
标题翻译：制造薄膜中的α-Ta的结构和方法
公开(公告)号：US5281485A
公开(公告)日：1994-01-25
申请号：US3959
申请日：1993-01-15
申请人： Evan G. Colgan , Peter M. Fryer
发明人： Evan G. Colgan , Peter M. Fryer
IPC分类号： C23C14/06 , C23C14/14 , H01L21/28 , H01L21/285 , H01L21/768 , B32B15/04
CPC分类号： H01L21/76876 , C23C14/14 , H01L21/28079 , H01L21/28568 , H01L21/76841 , Y10S428/938 , Y10T428/31678
摘要： The present invention relates generally to a structure and a method of making Alpha-Ta films, and more particularly, to a structure and a method of making Alpha-Ta in thin films. A seed layer of Ta reactively sputtered in a nitrogen containing environment is grown on the substrate, and using this seed layer of Ta(N) layers of Alpha-Ta are then formed.
摘要翻译：本发明一般涉及制造α-Ta膜的结构和方法，更具体地说，涉及在薄膜中制造α-Ta的结构和方法。在含氮环境中反应溅射的Ta的籽晶层在衬底上生长，然后形成Ta（N）层的Al-Ta的种子层。

27. 发明授权

US08937810B2 Electronic assembly with detachable coolant manifold and coolant-cooled electronic module 有权
标题翻译：具有可拆卸冷却液歧管和冷却剂冷却电子模块的电子组件
公开(公告)号：US08937810B2
公开(公告)日：2015-01-20
申请号：US13616337
申请日：2012-09-14
申请人： Thomas J. Brunschwiler , Evan G. Colgan , Michael J. Ellsworth, Jr. , Werner Escher , Ingmar G. Meijer , Stephan Paredes , Gerd Schlottig , Martin Witzig , Jeffrey A. Zitz
发明人： Thomas J. Brunschwiler , Evan G. Colgan , Michael J. Ellsworth, Jr. , Werner Escher , Ingmar G. Meijer , Stephan Paredes , Gerd Schlottig , Martin Witzig , Jeffrey A. Zitz
IPC分类号： H05K7/20 , H01L23/46
CPC分类号： H05K7/20772 , Y10T29/49002
摘要： Cooled electronic assemblies, and a method of decoupling a cooled electronic assembly, are provided. In one embodiment, the assembly includes a coolant-cooled electronic module with one or more electronic components and one or more coolant-carrying channels integrated within the module and configured to facilitate flow of coolant through the module for cooling the electronic component(s). In addition, the assembly includes a coolant manifold structure detachably coupled to the electronic module. The manifold structure, which includes a coolant inlet and outlet in fluid communication with the coolant-carrying channel(s) of the electronic module, facilitates flow of coolant through the coolant-carrying channel, and thus cooling of the electronic component(s). Coolant-absorbent material is positioned at the interface between the electronic module and the manifold structure to facilitate absorbing any excess coolant during a stepwise detaching of the manifold structure from the electronic module.
摘要翻译：提供了冷却的电子组件，以及一种解耦冷却的电子组件的方法。在一个实施例中，组件包括冷却剂冷却的电子模块，其具有一个或多个电子部件和一个或多个集成在模块内的冷却剂传送通道并且被配置为便于冷却剂流过模块以冷却电子部件。此外，组件包括可拆卸地联接到电子模块的冷却剂歧管结构。歧管结构包括与电子模块的冷却剂输送通道流体连通的冷却剂入口和出口，有利于冷却剂流过冷却剂输送通道，从而冷却电子部件。冷却剂吸收材料位于电子模块和歧管结构之间的界面处，以便于在将歧管结构从电子模块逐步拆卸时吸收任何多余的冷却剂。

28. 发明申请

US20140024146A1 SEMICONDUCTOR STRUCTURE 审中-公开
公开(公告)号：US20140024146A1
公开(公告)日：2014-01-23
申请号：US13565848
申请日：2012-08-03
申请人： Diego Anzola , Evan G. Colgan , Kevin K. Dezfulian , Daniel C. Edelstein , Mark C. H. Lamorey , Sampath Purushothaman , Thomas M. Shaw , Roy R. Yu
发明人： Diego Anzola , Evan G. Colgan , Kevin K. Dezfulian , Daniel C. Edelstein , Mark C. H. Lamorey , Sampath Purushothaman , Thomas M. Shaw , Roy R. Yu
IPC分类号： H01L21/768 , H01L21/50 , H01L21/66
CPC分类号： H01L23/585 , H01L23/562 , H01L25/0657 , H01L2224/04042 , H01L2224/05624 , H01L2225/06551 , H01L2225/06565
摘要： A semiconductor structure is provided and includes a substrate having an edge surface and a device surface with a central area, a crack stop structure disposed on the device surface and a circuit structure including components disposed on the device surface in the central area and interconnects electrically coupled to the components. The interconnects are configured to extend from the central area to the edge surface while bridging over the crack stop structure.

29. 发明授权

US08479388B2 Method of producing a land grid array interposer 有权
标题翻译：地面栅格阵列插入器的制作方法
公开(公告)号：US08479388B2
公开(公告)日：2013-07-09
申请号：US12207713
申请日：2008-09-10
申请人： Gareth G. Hougham , Brian S. Beaman , Evan G. Colgan , Paul W. Coteus , Stefano S. Oggioni , Enrique Vargas
发明人： Gareth G. Hougham , Brian S. Beaman , Evan G. Colgan , Paul W. Coteus , Stefano S. Oggioni , Enrique Vargas
IPC分类号： H01K3/10
CPC分类号： H01R12/714 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01R12/52 , H05K3/326 , H05K3/4007 , H05K7/1061 , H05K2201/0133 , H05K2201/0367 , H05K2201/09481 , H05K2201/09745 , H05K2201/10378 , H05K2201/10734 , Y10T29/49002 , Y10T29/49121 , Y10T29/49124 , Y10T29/49126 , Y10T29/49128 , Y10T29/4913 , Y10T29/49147 , Y10T29/49149 , Y10T29/49151 , Y10T29/49155 , Y10T29/49158 , Y10T29/49165 , Y10T29/49204 , Y10T29/49208 , Y10T29/49213 , Y10T29/49218 , Y10T29/49222 , H01L2924/00
摘要： A method of producing a land grid array (LGA) interposer structure, including an electrically insulating carrier plane, and at least one interposer mounted on a first surface of said carrier plane. The interposer possesses a hemi-toroidal configuration in transverse cross-section and is constituted of a dielectric elastomeric material. A plurality of electrically-conductive elements are arranged about the surface of the at least one hemi-toroidal interposer and extend radically inwardly and downwardly from an uppermost end thereof into electrical contact with at least one component located on an opposite side of the electrically insulating carrier plane.
摘要翻译：一种制造包括电绝缘载体平面的平面栅格阵列（LGA）插入器结构以及安装在所述载体平面的第一表面上的至少一个插入件的方法。插入件在横截面中具有半环形结构，并由介电弹性体材料构成。多个导电元件围绕至少一个半环形插入器的表面布置并且从其最上端向内和向下自由地延伸至与位于电绝缘载体的相对侧上的至少一个部件的电接触飞机

30. 发明申请

US20130105994A1 HEATSINK ATTACHMENT MODULE 有权
标题翻译： HEATSINK附件模块
公开(公告)号：US20130105994A1
公开(公告)日：2013-05-02
申请号：US13284522
申请日：2011-10-28
申请人： Evan G. Colgan , Michael A. Gaynes , Jeffrey A. Zitz
发明人： Evan G. Colgan , Michael A. Gaynes , Jeffrey A. Zitz
IPC分类号： H01L23/48 , H01L21/56
CPC分类号： H01L21/50 , H01L23/3128 , H01L23/433 , H01L24/16 , H01L24/32 , H01L24/72 , H01L24/73 , H01L24/90 , H01L24/92 , H01L2224/131 , H01L2224/16225 , H01L2224/32225 , H01L2224/73253 , H01L2224/81815 , H01L2224/83104 , H01L2224/83901 , H01L2224/921 , H01L2924/10253 , H01L2924/15787 , H01L2924/00 , H01L2924/00014 , H01L2924/00012 , H01L2224/83 , H01L2224/90 , H01L2924/014
摘要： A chip packaging apparatus includes a substrate, a load frame attached to the substrate by an adhesive material, the load frame being formed to define an aperture and a semiconductor chip mounted on the substrate within the aperture. A thickness of the adhesive material between the load frame and the substrate is varied and adjusted such that a surface of the load frame opposite the substrate is disposed substantially in parallel to a surface of the chip opposite the substrate.
摘要翻译：芯片封装设备包括基板，通过粘合剂材料附接到基板的负载框架，所述负载框架形成为限定孔和安装在孔内的基板上的半导体芯片。负载框架和基板之间的粘合材料的厚度被改变和调节，使得与基板相对的负载框架的表面基本上平行于与基板相对的芯片的表面平行。

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