会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 24. 发明授权
    • Reduced computation system for wavelet transforms
    • 减少小波变换计算系统
    • US06466957B1
    • 2002-10-15
    • US09388754
    • 1999-09-02
    • Shayne MesserlyTodor Cooklev
    • Shayne MesserlyTodor Cooklev
    • G06F1710
    • G06F17/148
    • An improved architecture for efficiently calculating a discrete wavelet transform is presented. The present system appreciates the associated redundancies of calculations and proposes a topology for eliminating such redundant calculations through the use of storing and making such previously calculated coefficients available in successive wavelet coefficient calculations. The present system while recognizing redundant calculations and performing storage operations, also provides a pipelined architecture whereby the wavelet coefficients are calculated and combined for use in a wavelet packet tree architecture.
    • 提出了一种用于有效计算离散小波变换的改进架构。 本系统欣赏相关的计算冗余,并提出了一种用于通过使用存储并使得先前计算的系数在连续小波系数计算中可用的消除这种冗余计算的拓扑。 本系统同时识别冗余计算和执行存储操作,还提供流水线架构,由此小波系数被计算和组合以用于小波包树结构。
    • 25. 发明授权
    • High throughput UART to DSP interface having Dual transmit and receive FIFO buffers to support data transfer between a host computer and an attached modem
    • 高吞吐量UART至DSP接口,具有双发送和接收FIFO缓冲器,可支持主机和附加调制解调器之间的数据传输
    • US06381661B1
    • 2002-04-30
    • US09321905
    • 1999-05-28
    • Shayne MesserlyHarrison KillianDavid Arnesen
    • Shayne MesserlyHarrison KillianDavid Arnesen
    • G06F1312
    • G06F13/24G06F13/385
    • The high throughput UART to DSP interface (UDIF) maintains UART functionality while integrating dual Transmit (Tx) and Receive (Rx) FIFO buffers that are optimized for more efficient interaction with their respective I/O processors. The portion of the interface design interacting with the DSP, the UDIF, provides several unique Status, Informational, and Control registers that lower the DSP overhead required for many of the basic modem functions. The UDIF design also performs parity add, parity strip, and character echo functions, traditionally performed at a high overhead cost by the DSP. These functions are more efficiently preformed by hardware implementations than by the software routines executed by the DSP. More burdensome command functions like escape, AT, and flow control commands can also be implemented through hardware implementations to reduce processor overhead.
    • 高吞吐量UART到DSP接口(UDIF)在集成双发送(Tx)和接收(Rx))FIFO缓冲器时保持UART功能,该缓冲器经过优化,可与各自的I / O处理器进行更有效的交互。 接口设计与DSP(UDIF)交互的部分提供了几种独特的状态,信息和控制寄存器,可以降低许多基本调制解调器功能所需的DSP开销。 UDIF设计还执行奇偶校验位,奇偶校验位和字符回波功能,传统上由DSP以高额外的成本执行。 这些功能通过硬件实现更有效地执行,而不是由DSP执行的软件程序执行。 还可以通过硬件实现来实现更加繁重的命令功能,如转义,AT和流控制命令,以减少处理器开销。
    • 26. 发明授权
    • Low power ultrasound system
    • 低功率超声系统
    • US08500645B2
    • 2013-08-06
    • US12100983
    • 2008-04-10
    • Benjamin A. CohenDylan K. RoblesShayne Messerly
    • Benjamin A. CohenDylan K. RoblesShayne Messerly
    • A61B8/00A61B8/14
    • A61B8/145A61B8/4472A61B8/4483A61B8/461A61B8/5207A61B8/56G01S7/003G01S7/52017G01S7/5208G01S7/52082G01S7/52085G01S7/52096G01S15/8909
    • A low power ultrasound system for use in sonography applications, including vascular imaging, is disclosed. In one embodiment, the low power ultrasound system comprises a base unit that includes an image processor and a display. An ultrasound probe is operably connected to the base unit. The probe includes a head portion including an array of crystal transducers. A plurality of pulser/receiver modules that cause the transducers to emit ultrasonic transmit pulses are also included in the probe. The pulser/receiver modules are further configured to receive analog signals relating to ultrasonic echo receive pulses detected by the transducers. The probe includes a singular low noise amplifier that amplifies the analog signals, and an analog-to-digital converter that converts the analog signals to a digital signal. A wireless interface is included for enabling the digital signal to be wirelessly transmitted from the probe to the image processor of the base unit.
    • 公开了一种用于超声波应用的低功率超声系统,包括血管成像。 在一个实施例中,低功率超声系统包括包括图像处理器和显示器的基本单元。 超声探头可操作地连接到基座单元。 探头包括包括晶体换能器阵列的头部。 导致换能器发射超声波发射脉冲的多个脉冲发生器/接收器模块也包括在探头中。 脉冲发生器/接收器模块还被配置为接收与由换能器检测到的超声回波接收脉冲有关的模拟信号。 该探头包括放大模拟信号的单个低噪声放大器,以及将模拟信号转换为数字信号的模数转换器。 包括无线接口,用于使数字信号从探头无线传输到基本单元的图像处理器。
    • 30. 发明授权
    • Data signal attenuator and systems and methods for using same
    • 数据信号衰减器及其使用方法
    • US06697485B1
    • 2004-02-24
    • US09189964
    • 1998-11-10
    • Spiro PoulisJohn EvansShayne Messerly
    • Spiro PoulisJohn EvansShayne Messerly
    • H04M100
    • H04M1/76
    • The present invention provides apparatus and methods for attenuating signals received from a source over a data transmission line, having an unknown resistance, to achieve optimized signals in various data terminal and data communications equipment. In a preferred embodiment, a resistor network is operably coupled between the transmission line and a means for processing the signal, such as a digital processor, an ADC and a DAC. The resistor network comprises a termination resistor that is associated with a termination voltage, a variable resistor and another resistor. During use, a switch is operably positioned between a plurality of switch positions so that two voltage measurements will lead to the determination of the voltage of the source and the termination voltage within the resistor network. Once these voltages are known, the unknown resistance can be estimated. Thereafter, the length of the transmission line may be determined because of known resistance-per-unit-distance characteristics of the transmission line. In response to knowing this length, the digital processor selects a desired resistance value for the variable resistor so that, upon adjustment of the variable resistor by the DAC, the signal becomes a largest-possible input at the ADC.
    • 本发明提供用于衰减在数据传输线上从源接收的具有未知电阻的信号的装置和方法,以在各种数据终端和数据通信设备中实现优化的信号。 在优选实施例中,电阻网络可操作地耦合在传输线和用于处理信号的装置之间,诸如数字处理器,ADC和DAC。 电阻网络包括与终端电压相关联的终端电阻器,可变电阻器和另一个电阻器。 在使用期间,开关可操作地定位在多个开关位置之间,使得两个电压测量将导致确定电阻器网络内的电源电压和终止电压。 一旦这些电压已知,可以估计未知电阻。 此后,由于传输线的已知电阻 - 单位 - 距离特性,可以确定传输线的长度。 响应于知道该长度,数字处理器为可变电阻器选择期望的电阻值,使得在通过DAC调节可变电阻器时,该信号在ADC处变为最大可能的输入。