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21. 发明授权

US07683428B2 Vertical Fin-FET MOS devices 有权
标题翻译：垂直Fin-FET MOS器件
公开(公告)号：US07683428B2
公开(公告)日：2010-03-23
申请号：US10597288
申请日：2004-01-22
申请人： Dureseti Chidambarrao , Jochen Beintner , Ramachandra Divakaruni
发明人： Dureseti Chidambarrao , Jochen Beintner , Ramachandra Divakaruni
IPC分类号： H01L27/108
CPC分类号： H01L29/78642 , H01L21/2257 , H01L29/66787
摘要： A new class of high-density, vertical Fin-FET devices that exhibit low contact resistance is described. These vertical Fin-FET devices have vertical silicon “fins” (12A) that act as the transistor body. Doped source and drain regions (26A, 28A) are formed at the bottoms and tops, respectively, of the fins (12A). Gates (24A, 24B) are formed along sidewalls of the fins. Current flows vertically through the fins (12A) between the source and drain regions (26A, 28A) when an appropriate bias is applied to the gates (24A, 24B). An integrated process for forming pFET, nFET, multi-fin, single-fin, multi-gate and double-gate vertical Fin-FETs simultaneously is described.
摘要翻译：描述了一种新型的具有低接触电阻的高密度垂直Fin-FET器件。这些垂直Fin-FET器件具有用作晶体管体的垂直硅“鳍”（12A）。掺杂的源极和漏极区域（26A，28A）分别形成在鳍片（12A）的底部和顶部。盖板（24A，24B）沿翅片的侧壁形成。当适当的偏压被施加到栅极（24A，24B）时，电流垂直地流过源极和漏极区域（26A，28A）之间的鳍片（12A）。描述了同时形成pFET，nFET，多鳍，单鳍，多栅极和双栅极垂直鳍FET的集成工艺。

22. 发明授权

US06724031B1 Method for preventing strap-to-strap punch through in vertical DRAMs 有权
标题翻译：用于防止在垂直DRAM中穿带穿过的方法
公开(公告)号：US06724031B1
公开(公告)日：2004-04-20
申请号：US10340999
申请日：2003-01-13
申请人： Hiroyuki Akatsu , Dureseti Chidambarrao , Ramachandra Divakaruni , Jack Mandelman , Carl J. Radens
发明人： Hiroyuki Akatsu , Dureseti Chidambarrao , Ramachandra Divakaruni , Jack Mandelman , Carl J. Radens
IPC分类号： H01L27108
CPC分类号： H01L27/10864 , H01L27/10841 , H01L27/10867 , H01L29/945
摘要： A dynamic random access memory cell comprising: a trench capacitor formed in a silicon substrate; a vertical MOSFET formed in a silicon substrate above the trench capacitor, the vertical MOSFET having a gate electrode, a first source/drain region extending from a surface of the silicon substrate into the silicon substrate, a buried second source/drain region electrically contacting the trench capacitor, a channel region formed in the silicon substrate between the first source/drain region and the buried second source/drain region and a gate oxide layer disposed between the gate electrode and the channel region; the first source/drain region also belonging to an adjacent vertical MOSFET, the adjacent vertical MOSFET having a buried third source/drain region electrically connected to an adjacent trench capacitor, the buried second and third source/drain regions extending toward one another; and a punch through prevention region disposed between the buried second and third source/drain regions.
摘要翻译：一种动态随机存取存储单元，包括：形成在硅衬底中的沟槽电容器; 在所述沟槽电容器上方的硅衬底中形成的垂直MOSFET，所述垂直MOSFET具有栅极电极，从所述硅衬底的表面延伸到所述硅衬底的第一源极/漏极区域，与所述第二源极/漏极区域电接触的第二源极/ 沟槽电容器，形成在第一源极/漏极区域和埋入的第二源极/漏极区域之间的硅衬底中的沟道区域和设置在栅极电极和沟道区域之间的栅极氧化物层; 第一源极/漏极区域也属于相邻的垂直MOSFET，相邻的垂直MOSFET具有电连接到相邻沟槽电容器的掩埋的第三源极/漏极区域，所述埋入的第二和第三源极/漏极区域彼此延伸; 以及设置在埋入的第二和第三源极/漏极区之间的穿通防止区域。

23. 发明授权

US06703274B1 Buried strap with limited outdiffusion and vertical transistor DRAM 有权
标题翻译：带有限制扩散和垂直晶体管DRAM的埋地带
公开(公告)号：US06703274B1
公开(公告)日：2004-03-09
申请号：US10336988
申请日：2003-01-03
申请人： Dureseti Chidambarrao , Ramachandra Divakaruni , Jack A. Mandelman , Raymond Van Roijen
发明人： Dureseti Chidambarrao , Ramachandra Divakaruni , Jack A. Mandelman , Raymond Van Roijen
IPC分类号： H02L218242
CPC分类号： H01L27/10867 , H01L27/10864 , H01L27/10876
摘要： A DRAM cell with a vertical transistor forms a buried strap outdiffusion with reduced lateral extent by shifting high temperature steps that affect the thermal budget before the initial buried strap diffusion. The gate conductor is formed in two steps, with poly sidewalls being put down above a sacrificial Trench top oxide to form a self-aligned poly-gate insulator structure before the formation of the LDD extension.
摘要翻译：具有垂直晶体管的DRAM单元通过在初始掩埋带扩散之前移动影响热预算的高温步骤而形成具有减小的横向扩展的埋地带外扩散。栅极导体形成为两个阶段，其中多个侧壁被放置在牺牲沟槽顶部氧化物之上，以在形成LDD延伸之前形成自对准多晶硅绝缘体结构。

24. 发明申请

US20090200604A1 VERTICAL FIN-FET MOS DEVICES 有权
标题翻译：垂直熔池MOS器件
公开(公告)号：US20090200604A1
公开(公告)日：2009-08-13
申请号：US10597288
申请日：2004-01-22
申请人： Dureseti Chidambarrao , Jochen Beintner , Ramachandra Divakaruni
发明人： Dureseti Chidambarrao , Jochen Beintner , Ramachandra Divakaruni
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/78642 , H01L21/2257 , H01L29/66787
摘要： A new class of high-density, vertical Fin-FET devices that exhibit low contact resistance is described. These vertical Fin-FET devices have vertical silicon “fins” (12A) that act as the transistor body. Doped source and drain regions (26A, 28A) are formed at the bottoms and tops, respectively, of the fins (12A). Gates (24A, 24B) are formed along sidewalls of the fins. Current flows vertically through the fins (12A) between the source and drain regions (26A, 28A) when an appropriate bias is applied to the gates (24A, 24B). An integrated process for forming pFET, nFET, multi-fin, single-fin, multi-gate and double-gate vertical Fin-FETs simultaneously is described.
摘要翻译：描述了一种新型的具有低接触电阻的高密度垂直Fin-FET器件。这些垂直Fin-FET器件具有用作晶体管体的垂直硅“鳍”（12A）。掺杂的源极和漏极区域（26A，28A）分别形成在鳍片（12A）的底部和顶部。盖板（24A，24B）沿翅片的侧壁形成。当适当的偏压被施加到栅极（24A，24B）时，电流垂直地流过源极和漏极区域（26A，28A）之间的鳍片（12A）。描述了同时形成pFET，nFET，多鳍，单鳍，多栅极和双栅极垂直鳍FET的集成工艺。

25. 发明授权

US07009237B2 Out of the box vertical transistor for eDRAM on SOI 有权
标题翻译：在SOI上用于eDRAM的开箱式垂直晶体管
公开(公告)号：US07009237B2
公开(公告)日：2006-03-07
申请号：US10709450
申请日：2004-05-06
申请人： James W. Adkisson , Gary B. Bronner , Dureseti Chidambarrao , Ramachandra Divakaruni , Carl J. Radens
发明人： James W. Adkisson , Gary B. Bronner , Dureseti Chidambarrao , Ramachandra Divakaruni , Carl J. Radens
IPC分类号： H01L27/108
CPC分类号： H01L27/10841 , H01L27/10864 , H01L27/10867
摘要： The present invention provides a vertical memory device formed in a silicon-on-insulator substrate, where a bitline contacting the upper surface of the silicon-on-insulator substrate is electrically connected to the vertical memory device through an upper strap diffusion region formed through a buried oxide layer. The upper strap diffusion region is formed by laterally etching a portion of the buried oxide region to produce a divot, in which doped polysilicon is deposited. The upper strap region diffusion region also provides the source for the vertical transistor of the vertical memory device. The vertical memory device may also be integrated with a support region having logic devices formed atop the silicon-on-insulator substrate.
摘要翻译：本发明提供了一种形成在绝缘体上硅衬底上的垂直存储器件，其中接触绝缘体上硅衬底的上表面的位线通过上带扩散区域电连接到垂直存储器件掩埋氧化层。上带扩散区域通过横向蚀刻掩埋氧化物区域的一部分而形成，其中沉积掺杂多晶硅。上带区域扩散区域还为垂直存储器件的垂直晶体管提供源极。垂直存储器件还可以与具有形成在绝缘体上硅衬底上的逻辑器件的支撑区域集成。

26. 发明授权

US07129130B2 Out of the box vertical transistor for eDRAM on SOI 失效
公开(公告)号：US07129130B2
公开(公告)日：2006-10-31
申请号：US11298800
申请日：2005-12-09
申请人： James W. Adkisson , Gary B. Bronner , Dureseti Chidambarrao , Ramachandra Divakaruni , Carl J. Radens
发明人： James W. Adkisson , Gary B. Bronner , Dureseti Chidambarrao , Ramachandra Divakaruni , Carl J. Radens
IPC分类号： H01L21/8242 , H01L2/20
CPC分类号： H01L27/10841 , H01L27/10864 , H01L27/10867
摘要： The present invention provides a vertical memory device formed in a silicon-on-insulator substrate, where a bitline contacting the upper surface of the silicon-on-insulator substrate is electrically connected to the vertical memory device through an upper strap diffusion region formed through a buried oxide layer. The upper strap diffusion region is formed by laterally etching a portion of the buried oxide region to produce a divot, in which doped polysilicon is deposited. The upper strap region diffusion region also provides the source for the vertical transistor of the vertical memory device. The vertical memory device may also be integrated with a support region having logic devices formed atop the silicon-on-insulator substrate.

27. 发明授权

US06573561B1 Vertical MOSFET with asymmetrically graded channel doping 失效
标题翻译：具有不对称梯度通道掺杂的垂直MOSFET
公开(公告)号：US06573561B1
公开(公告)日：2003-06-03
申请号：US10096192
申请日：2002-03-11
申请人： Dureseti Chidambarrao , Ramachandra Divakaruni , Jack A. Mandelman , Kevin McStay
发明人： Dureseti Chidambarrao , Ramachandra Divakaruni , Jack A. Mandelman , Kevin McStay
IPC分类号： H01L2976
CPC分类号： H01L27/10864 , H01L27/10876 , H01L29/1041 , H01L29/7827
摘要： Short channel effects in vertical MOSFET transistors are considerably reduced, junction leakage in DRAM cells is reduced and other device parameters are unaffected in a transistor having a vertically asymmetric threshold implant. A preferred embodiment has the peak of the threshold implant moved from the conventional location of midway between source and drain to a point no more than one third of the channel length below the bottom of the source.
摘要翻译：垂直MOSFET晶体管中的短沟道效应显着降低，在具有垂直非对称阈值注入的晶体管中，DRAM单元中的结漏电减少，其它器件参数不受影响。优选实施例具有将阈值注入的峰值从源极和漏极之间的中途的常规位置移动到不超过源极底部的沟道长度的三分之一的点。

28. 发明授权

US09059316B2 Structure and method for mobility enhanced MOSFETs with unalloyed silicide 有权
标题翻译：具有非合金化硅化物的迁移率增强型MOSFET的结构和方法
公开(公告)号：US09059316B2
公开(公告)日：2015-06-16
申请号：US13397860
申请日：2012-02-16
申请人： Yaocheng Liu , Dureseti Chidambarrao , Oleg Gluschenkov , Judson R. Holt , Renee T. Mo , Kern Rim
发明人： Yaocheng Liu , Dureseti Chidambarrao , Oleg Gluschenkov , Judson R. Holt , Renee T. Mo , Kern Rim
IPC分类号： H01L21/8238 , H01L21/768 , H01L21/84 , H01L27/12 , H01L29/66 , H01L29/78 , H01L27/32 , H01L29/165
CPC分类号： H01L21/823864 , H01L21/76886 , H01L21/823807 , H01L21/823814 , H01L21/84 , H01L27/1203 , H01L27/3279 , H01L29/165 , H01L29/665 , H01L29/6656 , H01L29/66628 , H01L29/66636 , H01L29/7848
摘要： While embedded silicon germanium alloy and silicon carbon alloy provide many useful applications, especially for enhancing the mobility of MOSFETs through stress engineering, formation of alloyed silicide on these surfaces degrades device performance. The present invention provides structures and methods for providing unalloyed silicide on such silicon alloy surfaces placed on semiconductor substrates. This enables the formation of low resistance contacts for both mobility enhanced PFETs with embedded SiGe and mobility enhanced NFETs with embedded Si:C on the same semiconductor substrate. Furthermore, this invention provides methods for thick epitaxial silicon alloy, especially thick epitaxial Si:C alloy, above the level of the gate dielectric to increase the stress on the channel on the transistor devices.
摘要翻译：虽然嵌入式硅锗合金和硅碳合金提供了许多有用的应用，特别是为了通过应力工程增强MOSFET的迁移率，在这些表面上形成合金化硅化物降低了器件性能。本发明提供了在放置在半导体衬底上的这种硅合金表面上提供非合金硅化物的结构和方法。这使得能够在具有嵌入式SiGe的迁移率增强的PFET和在同一半导体衬底上具有嵌入的Si：C的迁移率增强的NFET形成低电阻触点。此外，本发明提供了在栅极电介质的电平之上的厚外延硅合金，特别是厚的外延Si：C合金的方法，以增加晶体管器件上的沟道上的应力。

29. 发明授权

US08871576B2 Silicon nanotube MOSFET 有权
标题翻译：硅纳米管MOSFET
公开(公告)号：US08871576B2
公开(公告)日：2014-10-28
申请号：US13036292
申请日：2011-02-28
申请人： Daniel Tekleab , Hung H. Tran , Jeffrey W. Sleight , Dureseti Chidambarrao
发明人： Daniel Tekleab , Hung H. Tran , Jeffrey W. Sleight , Dureseti Chidambarrao
IPC分类号： H01L29/49 , H01L29/06 , B82Y10/00 , H01L29/775 , H01L29/66 , H01L29/78
CPC分类号： H01L29/78 , B82Y10/00 , H01L29/0676 , H01L29/66439 , H01L29/66666 , H01L29/775 , H01L29/7827
摘要： A nanotubular MOSFET device and a method of fabricating the same are used to extend device scaling roadmap while maintaining good short channel effects and providing competitive drive current. The nanotubular MOSFET device includes a concentric tubular inner and outer gate separated from each other by a tubular shaped epitaxially grown silicon layer, and a source and drain respectively separated by spacers surrounding the tubular inner and outer gates. The method of forming the nanotubular MOSFET device includes: forming on a substrate a cylindrical shaped Si layer; forming an outer gate surrounding the cylindrical Si layer and positioned between a bottom spacer and a top spacer; growing a silicon epitaxial layer on the top spacer adjacent to a portion of the cylindrical shaped Si layer; etching an inner portion of the cylindrical shaped Si forming a hollow cylinder; forming an inner spacer at the bottom of the inner cylinder; forming an inner gate by filling a portion of the hollow cylinder; forming a sidewall spacer adjacent to the inner gate; and etching a deep trench for accessing and contacting the outer gate and drain.
摘要翻译：纳米管MOSFET器件及其制造方法用于扩展器件缩放路线图，同时保持良好的短沟道效应并提供有竞争力的驱动电流。纳米管MOSFET器件包括通过管状外延生长硅层彼此分离的同心管状内部和外部栅极，以及分别由围绕管状内部和外部门的间隔开的源极和漏极。形成纳米管MOSFET器件的方法包括：在衬底上形成圆柱形的Si层; 形成围绕圆柱形Si层并位于底部间隔件和顶部间隔件之间的外部门; 在与圆柱形Si层的一部分相邻的顶部间隔上生长硅外延层; 蚀刻形成中空圆筒的圆柱形Si的内部; 在内筒的底部形成内隔板; 通过填充中空圆筒的一部分形成内门; 形成邻近所述内门的侧壁间隔物; 并蚀刻用于访问和接触外部栅极和漏极的深沟槽。

30. 发明授权

US08803243B2 Complementary metal oxide semiconductor (CMOS) device having gate structures connected by a metal gate conductor 有权
标题翻译：具有通过金属栅极导体连接的栅极结构的互补金属氧化物半导体（CMOS）器件
公开(公告)号：US08803243B2
公开(公告)日：2014-08-12
申请号：US13342435
申请日：2012-01-03
申请人： Yue Liang , Dureseti Chidambarrao , Brian J. Greene , William K. Henson , Unoh Kwon , Shreesh Narasimha , Xiaojun Yu
发明人： Yue Liang , Dureseti Chidambarrao , Brian J. Greene , William K. Henson , Unoh Kwon , Shreesh Narasimha , Xiaojun Yu
IPC分类号： H01L21/70
CPC分类号： H01L21/823871 , H01L21/28079 , H01L21/30604 , H01L21/76224 , H01L21/823878 , H01L29/4958
摘要： A complementary metal oxide semiconductor (CMOS) device including a substrate including a first active region and a second active region, wherein each of the first active region and second active region of the substrate are separated by from one another by an isolation region. A n-type semiconductor device is present on the first active region of the substrate, in which the n-type semiconductor device includes a first portion of a gate structure. A p-type semiconductor device is present on the second active region of the substrate, in which the p-type semiconductor device includes a second portion of the gate structure. A connecting gate portion provides electrical connectivity between the first portion of the gate structure and the second portion of the gate structure. Electrical contact to the connecting gate portion is over the isolation region, and is not over the first active region and/or the second active region.
摘要翻译：一种互补金属氧化物半导体（CMOS）器件，包括包括第一有源区和第二有源区的衬底，其中衬底的第一有源区和第二有源区中的每一个被隔离区彼此分开。 n型半导体器件存在于衬底的第一有源区上，其中n型半导体器件包括栅极结构的第一部分。 p型半导体器件存在于衬底的第二有源区上，其中p型半导体器件包括栅极结构的第二部分。连接栅极部分提供栅极结构的第一部分和栅极结构的第二部分之间的电连接。与连接栅极部分的电接触超过隔离区域，并且不在第一有源区域和/或第二有源区域之上。

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