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21. 发明授权

US06816397B1 Bi-directional read write data structure and method for memory 有权
标题翻译：双向读写数据结构和存储方法
公开(公告)号：US06816397B1
公开(公告)日：2004-11-09
申请号：US10448776
申请日：2003-05-29
申请人： John W. Golz , David R. Hanson , Hoki Kim
发明人： John W. Golz , David R. Hanson , Hoki Kim
IPC分类号： G11C502
CPC分类号： G11C7/1057 , G11C7/1051 , G11C7/1078 , G11C7/1084 , G11C11/4093
摘要： As disclosed herein, an integrated circuit memory is provided which includes primary sense amplifiers coupled for access to a multiplicity of storage cells, second sense amplifiers, and pairs of input/output data lines (IODLs), each IODL pair being coupled to a primary sense amplifier, and each IODL pair carrying complementary signals representing a storage bit. The memory further includes pairs of bi-directional primary data lines (BPDLs), each BPDL pair being coupled to a second sense amplifier and each BPDL pair being adapted to carry other complementary signals representing a storage bit. Local buffers are adapted to transfer, in accordance with control input, the complementary signals carried by the IODLs to the BPDLs, and vice versa.
摘要翻译：如本文所公开的，提供集成电路存储器，其包括被耦合用于访问多个存储单元，第二读出放大器和输入/输出数据线对（IODL）的初级读出放大器，每个IODL对被耦合到主感测放大器和每个IODL对承载表示存储位的互补信号。存储器还包括成对的双向主数据线（BPDL），每个BPDL对被耦合到第二读出放大器，并且每个BPDL对适于承载表示存储位的其他互补信号。本地缓冲器适于根据控制输入将IODL携带的互补信号传送到BPDL，反之亦然。

22. 发明授权

US06574127B2 System and method for reducing noise of congested datalines in an eDRAM 有权
标题翻译：减少eDRAM中拥塞数据库噪声的系统和方法
公开(公告)号：US06574127B2
公开(公告)日：2003-06-03
申请号：US09820592
申请日：2001-03-29
申请人： Louis L. Hsu , Rajiv V. Joshi , David R. Hanson
发明人： Louis L. Hsu , Rajiv V. Joshi , David R. Hanson
IPC分类号： G11C506
CPC分类号： G11C5/063
摘要： A dataline wiring structural system is provided for an eDRAM which suppresses coupling and switching noise associated with datalines by providing a plurality of metal levels upon which the datalines are positioned. Each of the datalines carrying a differential signal includes at least one vertical twist in which the true and complementary signal components of the differential signal change position from the one metal level of the plurality of metal levels to another level.
摘要翻译：为eDRAM提供数据线接线结构系统，其通过提供数据线定位在其上的多个金属电平来抑制与数据线相关联的耦合和开关噪声。携带差分信号的每个数据线包括至少一个垂直扭转，其中差分信号的真实和互补信号分量从多个金属电平的一个金属电平改变到另一个电平。

23. 发明授权

US06522171B2 Method of reducing sub-threshold leakage in circuits during standby mode 有权
公开(公告)号：US06522171B2
公开(公告)日：2003-02-18
申请号：US09759011
申请日：2001-01-11
申请人： David R. Hanson , Toshiaki Kirihata , Gerhard Mueller
发明人： David R. Hanson , Toshiaki Kirihata , Gerhard Mueller
IPC分类号： H03K19096
CPC分类号： H03K19/0016 , H03K19/0963
摘要： A dynamic logic circuit having reduced sub-threshold leakage current during standby mode comprises a connection to at least one upper power rail, a connection to a lower power rail, a precharge node, and an output node adapted to be charged to the potential of the upper power rail after a precharge signal is received at the precharge node. A latch on the output node is provided to maintain the potential at the output node, along with at least one input node for receiving at least one evaluation signal to maintain the potential at the output node to the voltage of the upper power rail or reduce the potential at the output node to the potential of the lower power rail. A device is coupled to the output node to set the output node to a potential which minimizes the sub-threshold leakage upon receipt of a standby signal to maintain the potential at the output node at the potential of the upper power rail or at the potential of the lower power rail.

24. 发明授权

US06313663B1 Full swing voltage input/full swing output bi-directional repeaters for high resistance or high capacitance bi-directional signal lines and methods therefor 有权
标题翻译：全摆幅电压输入/全摆幅输出双向中继器，用于高电阻或高电容双向信号线及其方法
公开(公告)号：US06313663B1
公开(公告)日：2001-11-06
申请号：US09491635
申请日：2000-01-27
申请人： Gerhard Mueller , David R. Hanson
发明人： Gerhard Mueller , David R. Hanson
IPC分类号： H03K190185
CPC分类号： B24B9/065 , B24B37/04 , G11C5/063 , H03K19/0013 , H03K19/018592 , H03K19/09429
摘要： A bidirectional full swing voltage repeater implemented on a signal line of an integrated circuit, which includes a first enable node for providing a first enable signal and a second enable node for providing a second enable signal. There is included a first full-swing unidirectional repeater circuit coupled between a first portion of the signal line and a second portion of the signal line. The first full-swing unidirectional repeater is configured to pass a first full swing signal from the first portion of the signal line to the second portion of the signal line when the first enable signal is enabled. The second full-swing unidirectional repeater circuit is coupled between the first portion of the signal line and the second portion of the signal line. The second full-swing unidirectional repeater circuit is configured to pass a second full swing signal from the second portion of the signal line to the first portion of the signal line when the second enable signal is enabled, wherein the first full-swing unidirectional repeater circuit and the second full-swing unidirectional repeater circuit are tri-stated when both the first enable signal and the second enable signal are disabled.
摘要翻译：在集成电路的信号线上实现的双向全摆幅电压中继器，其包括用于提供第一使能信号的第一使能节点和用于提供第二使能信号的第二使能节点。包括耦合在信号线的第一部分和信号线的第二部分之间的第一全方位单向中继器电路。第一全方位单向中继器被配置为当第一使能信号被使能时，将第一全摆幅信号从信号线的第一部分传递到信号线的第二部分。第二全方位单向中继器电路耦合在信号线的第一部分和信号线的第二部分之间。第二全方位单向中继器电路被配置为当第二使能信号被使能时，将第二全摆幅信号从信号线的第二部分传递到信号线的第一部分，其中第一全方位单向中继器电路而当第一使能信号和第二使能信号都被禁止时，第二全方位单向中继器电路是三态的。

25. 发明授权

US06307397B1 Reduced voltage input/reduced voltage output repeaters for high capacitance signal lines and methods therefor 失效
标题翻译：降低电压输入/降低电压输出中继器用于高电容信号线及其方法
公开(公告)号：US06307397B1
公开(公告)日：2001-10-23
申请号：US09491646
申请日：2000-01-27
申请人： Gerhard Mueller , David R. Hanson
发明人： Gerhard Mueller , David R. Hanson
IPC分类号： H03K1902
CPC分类号： B24B9/065 , B24B37/04 , G11C5/063 , H03K19/0013 , H03K19/018592 , H03K19/09429
摘要： A method in an integrated circuit for implementing a reduced voltage repeater circuit on a signal line having thereon reduced voltage signals. The reduced voltage signals has a voltage level that is below VDD. The reduced voltage repeater circuit is configured to be coupled to the signal line and having an input node coupled to a first portion of the signal line for receiving a first reduced voltage signal and an output node coupled to a second portion of the signal line for outputting a second reduced voltage signal. The method includes coupling the input node to the first portion of the signal line. The input node is coupled to an input stage of the reduced voltage repeater circuit. The input stage is configured to receive the first reduced voltage signal on the signal line. The input stage is also coupled to a level shifter stage that is arranged to output a set of level shifter stage control signals responsive to the first reduced voltage signal. A voltage range of the set of level shifter stage control signals is higher than a voltage range associated with the first reduced voltage signal. There is further included coupling the output node to the second portion of the signal line. The output node also is coupled to an output stage of the reduced voltage repeater circuit. The output stage is configured to output the second reduced voltage signal on the output node responsive to the set of level shifter stage control signals. A voltage range of the second reduced voltage signal is lower than the voltage range of the set of level shifter stage control signals.
摘要翻译：一种用于在其上具有减小的电压信号的信号线上实现减小电压中继器电路的集成电路中的方法。降低的电压信号的电压电平低于VDD。减小电压中继器电路被配置为耦合到信号线并且具有耦合到信号线的第一部分的输入节点，用于接收第一降低电压信号和耦合到信号线的第二部分的输出节点，用于输出第二降压信号。该方法包括将输入节点耦合到信号线的第一部分。输入节点耦合到减电压中继器电路的输入级。输入级被配置为在信号线上接收第一降低电压信号。输入级还耦合到电平移位器级，电平移位器级被布置成响应于第一降低电压信号输出一组电平移位器级控制信号。电平移位器级控制信号的电压范围高于与第一降压信号相关联的电压范围。还包括将输出节点耦合到信号线的第二部分。输出节点也耦合到减电压中继器电路的输出级。输出级被配置为响应于电平移位器级控制信号的集合而在输出节点上输出第二降压信号。第二降压信号的电压范围低于电平移位器级控制信号的电压范围。

26. 发明授权

US07106096B2 Circuit and method of controlling integrated circuit power consumption using phase change switches 有权
标题翻译：使用相变开关控制集成电路功耗的电路和方法
公开(公告)号：US07106096B2
公开(公告)日：2006-09-12
申请号：US10904460
申请日：2004-11-11
申请人： Huilong Zhu , Hon-Sum Philip Wong , Xinlin Wang , David R. Hanson
发明人： Huilong Zhu , Hon-Sum Philip Wong , Xinlin Wang , David R. Hanson
IPC分类号： G06F7/38 , H03K19/173 , H03K19/096 , G05F1/10 , G05F3/02
CPC分类号： H03K19/1778 , H01L45/06 , H01L45/1206 , H01L45/1286 , H01L45/144 , H03K19/0008 , H03K19/17784
摘要： A circuit and method of controlling integrated circuit power consumption using phase change switches where the phase change switches switchably couple and decouple power sources to logic blocks in response to a programming voltage.
摘要翻译：使用相变开关来控制集成电路功耗的电路和方法，其中相变开关响应于编程电压而切换地将电源耦合和解耦到逻辑块。

27. 发明授权

US07084449B2 Microelectronic element having trench capacitors with different capacitance values 失效
标题翻译：具有不同电容值的沟槽电容器的微电子元件
公开(公告)号：US07084449B2
公开(公告)日：2006-08-01
申请号：US10710146
申请日：2004-06-22
申请人： Kangguo Cheng , Johnathan E. Faltermeier , David R. Hanson , Carl J. Radens
发明人： Kangguo Cheng , Johnathan E. Faltermeier , David R. Hanson , Carl J. Radens
IPC分类号： H01L27/108 , H01L29/00
CPC分类号： H01L29/66181 , H01L27/1087 , H01L27/10894 , H01L29/945
摘要： A microelectronic element is provided having a major surface, the microelectronic element including a first capacitor formed on a sidewall of a first trench, the first trench being elongated in a downwardly extending direction from the major surface. The microelectronic element further includes a second capacitor formed on a sidewall of a second trench, the second trench being elongated in a downwardly extending direction from the major surface, wherein a top of the first capacitor is disposed at a first depth from the major surface, and a top of the second capacitor is disposed at a second depth from the major surface.
摘要翻译：提供具有主表面的微电子元件，微电子元件包括形成在第一沟槽的侧壁上的第一电容器，第一沟槽从主表面沿向下延伸的方向伸长。微电子元件还包括形成在第二沟槽的侧壁上的第二电容器，第二沟槽从主表面沿向下延伸的方向伸长，其中第一电容器的顶部设置在距离主表面的第一深度处，并且第二电容器的顶部设置在距离主表面的第二深度处。

28. 发明授权

US07013991B2 Obstacle detection system for underground operations 有权
标题翻译：地下作业障碍物检测系统
公开(公告)号：US07013991B2
公开(公告)日：2006-03-21
申请号：US10919748
申请日：2004-08-17
申请人： Alan Wilson-Langman , Michael R. Inggs , Leendert Johannes du Toit , Kirankumar M. Kothari , David R. Hanson
发明人： Alan Wilson-Langman , Michael R. Inggs , Leendert Johannes du Toit , Kirankumar M. Kothari , David R. Hanson
IPC分类号： E21B44/06
CPC分类号： E21B47/00 , E21B7/04
摘要： An obstacle avoidance system for obstacle detection in an opaque material. The system includes at least one electromagnetic signal source adapted to produce an electromagnetic source signal suitable for transmission through the opaque material, at least one electromagnetic signal detector adapted to receive reflected electromagnetic energy signals from discontinuities in the opaque material encountered by the electromagnetic source signal, and a reflected electromagnetic energy signal processor suitable for determining a presence of obstructions and/or strata variations within the opaque material. The system is preferably integral with a head element suitable for traversing the opaque material, for example a subterranean drill bit.
摘要翻译：在不透明材料中进行障碍物检测的障碍物回避系统。该系统包括适于产生适于通过不透明材料传输的电磁源信号的至少一个电磁信号源，至少一个电磁信号检测器，适于从电磁源信号遇到的不透明材料的不连续部分接收反射的电磁能信号，以及适用于确定不透明材料内的障碍物和/或层状变化的存在的反射电磁能量信号处理器。该系统优选地与适于横穿不透明材料（例如地下钻头）的头部元件成一体。

29. 发明授权

US06768143B1 Structure and method of making three finger folded field effect transistors having shared junctions 失效
标题翻译：制造具有共同连接点的三指折叠场效应晶体管的结构和方法
公开(公告)号：US06768143B1
公开(公告)日：2004-07-27
申请号：US10604913
申请日：2003-08-26
申请人： Gregory J. Fredeman , John W. Golz , David R. Hanson , Hoki Kim
发明人： Gregory J. Fredeman , John W. Golz , David R. Hanson , Hoki Kim
IPC分类号： H01L2710
CPC分类号： H01L27/10897 , G11C11/4085
摘要： An integrated circuit including a field effect transistor (FET) is provided in which the gate conducter has an even number of fingers disposed between alternating source and drain regions of a substrate. The fingers are disposed in a pattern over an area of the substrate having a length in a horizontal direction, the area equaling the length multiplied by a width in a vertical direction that is occupied by an odd number of the fingers.
摘要翻译：提供了包括场效应晶体管（FET）的集成电路，其中栅极导通器具有设置在衬底的交替的源极和漏极区域之间的偶数个指状物。手指在图案上设置有在水平方向上具有长度的区域的区域，该区域等于长度乘以由奇数手指占据的垂直方向上的宽度。

30. 发明授权

US06570794B1 Twisted bit-line compensation for DRAM having redundancy 有权
标题翻译：具有冗余的DRAM的双向位线补偿
公开(公告)号：US06570794B1
公开(公告)日：2003-05-27
申请号：US10034626
申请日：2001-12-27
申请人： Wolfgang Hokenmaier , Gunther Lehmann , Gerd Frankowsky , David R. Hanson
发明人： Wolfgang Hokenmaier , Gunther Lehmann , Gerd Frankowsky , David R. Hanson
IPC分类号： G11C700
CPC分类号： G11C7/18 , G11C11/4097 , G11C29/70
摘要： A memory is provided having an array of rows and columns of memory cells. The memory includes plurality of sense amplifiers, each one having a true terminal and a compliment terminal. The memory also includes a plurality of pairs of twisted bit lines, each one of the pairs of lines being coupled to true and compliment terminals of a corresponding one of the plurality of sense amplifiers. A plurality of word lines is provided, each one being connected to a corresponding one of the rows of memory cells. An address logic section is fed by column address signals, fed to the bit lines, and row address signals, fed to the word lines, for producing invert/non-invert signals in accordance with the fed row and column address signals. The memory includes a plurality of inverters each one being coupled to a corresponding one of the sense amplifiers for inverting data fed to or read from the sense amplifier selectively in accordance with the invert/non-invert signals produced by the address logic.
摘要翻译：提供具有存储器单元的行和列阵列的存储器。存储器包括多个读出放大器，每个读出放大器具有真正的终端和补码终端。存储器还包括多对扭绞位线，每对线对中的每一对被耦合到多个读出放大器中对应的一个读出放大器的真实和补充端子。提供多个字线，每个字线连接到存储器单元的行中相应的一行。地址逻辑部分由馈送到位线的列地址信号和馈送到字线的行地址信号馈送，用于根据馈送的行和列地址信号产生反相/非反相信号。存储器包括多个反相器，每个反相器被耦合到读出放大器中的对应的一个，用于根据由地址逻辑产生的反相/非反相信号选择性地反转馈送到读出放大器或从读出放大器读取的数据。

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