专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

21. 发明授权

US5707889A Process for forming field isolation 失效
标题翻译：用于形成场隔离的方法
公开(公告)号：US5707889A
公开(公告)日：1998-01-13
申请号：US645362
申请日：1996-05-13
申请人： Ting Chen Hsu , Laureen H. Parker , David G. Kolar , Philip J. Tobin , Hsing-Huang Tseng , Lisa K. Garling , Vida Ilderem
发明人： Ting Chen Hsu , Laureen H. Parker , David G. Kolar , Philip J. Tobin , Hsing-Huang Tseng , Lisa K. Garling , Vida Ilderem
IPC分类号： H01L21/32 , H01L21/76
CPC分类号： H01L21/32
摘要： An annealed amorphous silicon layer is formed prior to forming field isolation regions when using in a LOCOS field isolation process. The annealed amorphous silicon layer helps to reduce encroachment compared to conventional LOCOS field isolation process and helps to reduce the likelihood of forming pits within a substrate compared to a PBL field isolation process. The annealed amorphous silicon layer may be used in forming field isolation regions that defines the active regions between transistors including MOSFETs and bipolar transistors. Doped silicon or a silicon-rich silicon nitride layer may be used in place of conventional materials. The anneal of the amorphous silicon layer may be performed after forming a silicon nitride layer if the silicon nitride layer is deposited at a temperature no higher than 600 degrees Celsius.
摘要翻译：在LOCOS场隔离工艺中使用时，形成退火的非晶硅层，形成场隔离区。退火的非晶硅层有助于减少与常规LOCOS场隔离过程相比的侵蚀，并且有助于降低与PBL场隔离工艺相比在衬底内形成凹坑的可能性。退火的非晶硅层可以用于形成场隔离区域，其限定包括MOSFET和双极晶体管的晶体管之间的有源区。可以使用掺杂硅或富硅的氮化硅层代替常规材料。如果在不高于600摄氏度的温度下沉积氮化硅层，则可以在形成氮化硅层之后执行非晶硅层的退火。

22. 发明授权

US5543635A Thin film transistor and method of formation 失效
标题翻译：薄膜晶体管及其形成方法
公开(公告)号：US5543635A
公开(公告)日：1996-08-06
申请号：US455268
申请日：1995-05-31
申请人： Bich-Yen Nguyen , Thomas F. McNelly , Philip J. Tobin , James D. Hayden
发明人： Bich-Yen Nguyen , Thomas F. McNelly , Philip J. Tobin , James D. Hayden
IPC分类号： H01L21/336 , H01L21/8244 , H01L27/11 , H01L29/786 , H01L29/76 , H01L29/04 , H01L31/036 , H01L31/112
CPC分类号： H01L29/66765 , H01L27/11 , H01L27/1108 , H01L29/78618 , H01L29/78624 , H01L29/78678 , Y10S148/109
摘要： An under-gated thin film transistor (54) having low leakage current and a high on/off current ratio is formed using a composite layer (40) of semiconducting material. In one embodiment a composite layer (40) of semiconducting layer is formed by depositing two distinct layers (34, 38) of semiconducting material over the transistor gate electrode (18). The composite layer (40) is then patterned and implanted with ions to form a source region (46) and a drain region (48) within the composite layer (40), and to define a channel region (50) and an offset drain region (52) within the composite layer (40).
摘要翻译：使用半导体材料的复合层（40）形成具有低漏电流和高导通/截止电流比的欠门控薄膜晶体管（54）。在一个实施例中，通过在晶体管栅电极（18）上沉积半导体材料的两个不同的层（34,38）形成半导体层的复合层（40）。然后将复合层（40）图案化并注入离子，以在复合层（40）内形成源区（46）和漏区（48），并且限定沟道区（50）和偏移漏区（52）内。

23. 发明授权

US5407870A Process for fabricating a semiconductor device having a high reliability dielectric material 失效
标题翻译：制造具有高可靠性电介质材料的半导体器件的工艺
公开(公告)号：US5407870A
公开(公告)日：1995-04-18
申请号：US71885
申请日：1993-06-07
申请人： Yoshio Okada , Philip J. Tobin
发明人： Yoshio Okada , Philip J. Tobin
IPC分类号： H01L21/28 , H01L21/336 , H01L29/51 , H01L21/285
CPC分类号： H01L21/28273 , H01L21/28167 , H01L21/28176 , H01L29/511 , H01L29/66825
摘要： A process for fabricating a high-reliability composite dielectric layer (19) includes the formation of a first oxynitride layer (14) on the surface (12) of a silicon substrate (10). The formation of the first oxynitride layer (14) is followed by an oxidation step to form a silicon dioxide layer (16) at the surface (12) of the substrate (10) and underlying the first oxynitride layer (14). The composite dielectric layer (19) is completed by exposing the substrate (10) to nitrous oxide, and diffusing a nitrogen bearing species through both the silicon dioxide layer (16) and the first oxynitride layer (14) to form a second oxynitride layer (18) underlying the silicon dioxide layer (16). The composite dielectric layer (19) exhibits a nitrogen-rich region at the interface between second oxynitride layer (18) and the silicon substrate (10). A second nitrogen rich region is also formed near the surface of the first oxynitride layer (14).
摘要翻译：制造高可靠性复合电介质层（19）的工艺包括在硅衬底（10）的表面（12）上形成第一氮氧化物层（14）。第一氮氧化物层（14）的形成之后是氧化步骤，以在衬底（10）的表面（12）处形成二氧化硅层（16），并且位于第一氮氧化物层（14）下方。通过将基板（10）暴露于一氧化二氮并通过二氧化硅层（16）和第一氮氧化物层（14）两者扩散含氮物质来形成复合介电层（19），以形成第二氮氧化物层 18）位于二氧化硅层（16）下面。复合电介质层（19）在第二氧氮化物层（18）和硅衬底（10）之间的界面处显示富氮区域。在第一氮氧化物层（14）的表面附近还形成有第二富氮区域。

24. 发明授权

US5352615A Denuding a semiconductor substrate 失效
标题翻译：剥离半导体衬底
公开(公告)号：US5352615A
公开(公告)日：1994-10-04
申请号：US185351
申请日：1994-01-24
申请人： Young Limb , Philip J. Tobin
发明人： Young Limb , Philip J. Tobin
IPC分类号： C30B33/00 , H01L21/00 , H01L21/322 , H01L21/306
CPC分类号： H01L21/67115 , C30B33/00 , H01L21/3225 , Y10S148/06
摘要： A semiconductor substrate is denuded using a reducing gas mixture including carbon monoxide and carbon dioxide. Use of the reducing gas mixture allows very low oxygen partial pressure to be achieved in a furnace tube during the step of denuding. Oxygen partial pressure lower than 1E-9 atmosphere may be achieved by adjusting the relative ratio of carbon monoxide and carbon dioxide. Precipitates are grown after forming nucleating sites. Both CZ and FZ substrates may use the process, and the process can be used with silicon, germanium, or other semiconductor materials.
摘要翻译：使用包括一氧化碳和二氧化碳的还原气体混合物来剥蚀半导体衬底。使用还原气体混合物允许在剥离步骤期间在炉管中实现非常低的氧分压。低于1E-9气氛的氧气分压可以通过调节一氧化碳和二氧化碳的相对比例来实现。沉淀物在形成成核位点后生长。 CZ和FZ基板都可以使用该工艺，该工艺可以与硅，锗或其他半导体材料一起使用。

25. 发明授权

US4987102A Process for forming high purity thin films 失效
标题翻译：形成高纯度薄膜的方法
公开(公告)号：US4987102A
公开(公告)日：1991-01-22
申请号：US445220
申请日：1989-12-04
申请人： Bich-Yen Nguyen , Jen-Jiang Lee , Hoang K. Nguyen , Young Limb , Philip J. Tobin
发明人： Bich-Yen Nguyen , Jen-Jiang Lee , Hoang K. Nguyen , Young Limb , Philip J. Tobin
IPC分类号： H01L21/31 , H01L21/316 , H01L21/318
CPC分类号： H01L21/02164 , H01L21/02129 , H01L21/0217 , H01L21/02183 , H01L21/02186 , H01L21/022 , H01L21/02205 , H01L21/02274 , H01L21/31608 , H01L21/31612 , H01L21/318 , H01L21/3185
摘要： A method is described for the formation of high purity thin films on a semiconductor substrate. In the preferred embodiment of the invention a thin film is formed on a semiconductor substrate in a plasma enhanced chemical vapor deposition system. Energized silicon ions are obtained by mass analysis and are accelerated into a hydrogen-free plasma. A reaction occurs between energized atoms within the plasma and the energized silicon ions resulting in the deposition of a thin film on the semiconductor substrate.

26. 发明授权

US06894353B2 Capped dual metal gate transistors for CMOS process and method for making the same 有权
标题翻译：用于CMOS工艺的双金属栅极晶体管及其制造方法
公开(公告)号：US06894353B2
公开(公告)日：2005-05-17
申请号：US10209523
申请日：2002-07-31
申请人： Srikanth B. Samavedam , Philip J. Tobin
发明人： Srikanth B. Samavedam , Philip J. Tobin
IPC分类号： H01L21/8238 , H01L29/76
CPC分类号： H01L21/823835 , H01L21/823814 , H01L21/823842 , H01L21/823864
摘要： A first gate (120) and a second gate (122) are preferably PMOS and NMOS transistors, respectively, formed in an n-type well (104) and a p-type well (106). In a preferred embodiment first gate (120) includes a first metal layer (110) of titanium nitride on a gate dielectric (108), a second metal layer (114) of tantalum silicon nitride and a silicon containing layer (116) of polysilicon. Second gate (122) includes second metal layer (114) of a tantalum silicon nitride layer on the gate dielectric (108) and a silicon containing layer (116) of polysilicon. First spacers (124) are formed adjacent the sidewalls of the gates to protect the metals from chemistries used to remove photoresist masks during implant steps. Since the chemistries used are selective to polysilicon, the spacers (124) need not protect the polysilicon capping layers, thereby increasing the process margin of the spacer etch process. The polysilicon cap also facilitates silicidation of the gates.
摘要翻译：第一栅极（120）和第二栅极（122）分别优选分别形成在n型阱（104）和p型阱（106）中的PMOS和NMOS晶体管。在优选实施例中，第一栅极（120）包括在栅极电介质（108）上的氮化钛的第一金属层（110），氮化硅钽的第二金属层（114）和多晶硅的含硅层（116）。第二栅极（122）包括栅极电介质（108）上的氮化硅钽层的第二金属层（114）和多晶硅的含硅层（116）。邻近门的侧壁形成第一间隔物（124），以在植入步骤期间保护用于去除光致抗蚀剂掩模的化学物质的金属。由于使用的化学物质对多晶硅是选择性的，间隔物（124）不需要保护多晶硅覆盖层，从而增加间隔物蚀刻工艺的工艺边缘。多晶硅帽也有利于栅极的硅化。

27. 发明授权

US06297173B1 Process for forming a semiconductor device 有权
标题翻译：用于形成半导体器件的工艺
公开(公告)号：US06297173B1
公开(公告)日：2001-10-02
申请号：US09383238
申请日：1999-08-26
申请人： Philip J. Tobin , Rama I. Hegde , Hsing-Huang Tseng , David O'Meara , Victor Wang
发明人： Philip J. Tobin , Rama I. Hegde , Hsing-Huang Tseng , David O'Meara , Victor Wang
IPC分类号： H01L2131
CPC分类号： H01L27/11526 , H01L21/28202 , H01L21/28247 , H01L27/105 , H01L27/11546 , H01L29/518 , H01L29/66575
摘要： A method for forming an oxynitride gate dielectric layer (202, 204) begins by providing a semiconductor substrate (200). This semiconductor substrate is cleaned via process steps (10-28). Optional nitridation and oxidation are performed via steps (50 and 60) to form a thin interface layer (202). Bulk oxynitride gate deposition occurs via a step (70) to form a bulk gate dielectric material (204) having custom tailored oxygen and nitrogen profile and concentration. A step (10) is then utilized to in situ cap this bulk dielectric layer (204) with a polysilicon or amorphous silicon layer (208). The layer (208) ensures that the custom tailors oxygen and nitrogen profile and concentration of the underlying gate dielectric (204) is preserved even in the presence of subsequent wafer exposure to oxygen ambients.
摘要翻译：形成氧氮化物栅极电介质层（202,204）的方法由提供半导体衬底（200）开始。通过工艺步骤（10-28）清洁该半导体衬底。通过步骤（50和60）进行可选的氮化和氧化以形成薄界面层（202）。大量氮氧化物栅极沉积通过步骤（70）发生，以形成具有定制的氧和氮分布和浓度的体栅电介质材料（204）。然后使用步骤（10）以多晶硅或非晶硅层（208）原位覆盖该体电介质层（204）。即使在随后的晶片暴露于氧气氛的情况下，层（208）确保定制定制氧气和氮气分布和下层栅极电介质（204）的浓度。

28. 发明授权

US06136682A Method for forming a conductive structure having a composite or amorphous barrier layer 失效
标题翻译：用于形成具有复合或无定形阻挡层的导电结构的方法
公开(公告)号：US06136682A
公开(公告)日：2000-10-24
申请号：US954149
申请日：1997-10-20
申请人： Rama I. Hegde , Dean J. Denning , Jeffrey L. Klein , Philip J. Tobin
发明人： Rama I. Hegde , Dean J. Denning , Jeffrey L. Klein , Philip J. Tobin
IPC分类号： H01L21/768 , H01L23/532 , H01L21/4763
CPC分类号： H01L21/76876 , H01L21/76807 , H01L21/76843 , H01L23/53238 , H01L23/53295 , H01L2924/0002
摘要： A method for forming an improved copper barrier layer begins by providing a silicon-containing layer (10). A physical vapor deposition process is then used to form a thin tantalum nitride amorphous layer (12). A thin amorphous titanium nitride layer (14) is then deposited over the amorphous tantalum nitride layer. A collective thickness of the tantalum nitride and titanium nitride layers 12 and 14 is roughly 400 angstroms or less. A copper material 16 is then deposited on top of the amorphous titanium nitride wherein the composite tantalum nitride layer 12 and titanium nitride layer 14 effectively prevents copper from diffusion from the layer 16 to the layer 10.
摘要翻译： A形成改进的铜阻挡层的方法是通过提供含硅层（10）开始的。然后使用物理气相沉积工艺来形成薄的氮化钽非晶层（12）。然后在非晶氮化钽层上沉积薄的无定形氮化钛层（14）。氮化钽和氮化钛层12和14的总体厚度大致为400埃或更小。然后将铜材料16沉积在非晶氮化钛的顶部上，其中复合氮化钽层12和氮化钛层14有效地防止铜从层16扩散到层10。

29. 发明授权

US6020024A Method for forming high dielectric constant metal oxides 失效
标题翻译：形成高介电常数金属氧化物的方法
公开(公告)号：US6020024A
公开(公告)日：2000-02-01
申请号：US905755
申请日：1997-08-04
申请人： Bikas Maiti , Philip J. Tobin , Rama I. Hegde , Jesus Cuellar
发明人： Bikas Maiti , Philip J. Tobin , Rama I. Hegde , Jesus Cuellar
IPC分类号： H01L21/28 , H01L21/336 , H01L29/49 , H01L29/51 , H01L29/78 , C23C16/00
CPC分类号： H01L21/28185 , H01L21/28194 , H01L21/28202 , H01L21/2822 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/6659
摘要： A method for forming a metal gate (20) structure begins by providing a semiconductor substrate (12). The semiconductor substrate (12) is cleaned to reduce trap sites. A nitrided layer (14) having a thickness of less than approximately 20 Angstroms is formed over the substrate (12). This nitrided layer prevents the formation of an oxide at the substrate interface and has a dielectric constant greater than 3.9. After the formation of the nitrided layer(14), a metal oxide layer (16) having a permittivity value of greater than roughly 8.0 is formed over the nitrided layer (14). A metal gate (20) is formed over the nitrided layer whereby the remaining composite gate dielectric (14 and 16) has a larger physical thickness but a high-performance equivalent oxide thickness (EOT).
摘要翻译：一种用于形成金属栅极（20）结构的方法是通过提供半导体衬底（12）开始的。对半导体衬底（12）进行清洁以减少陷阱位置。在衬底（12）上形成厚度小于约20埃的氮化层（14）。该氮化层防止在衬底界面处形成氧化物并具有大于3.9的介电常数。在形成氮化层（14）之后，在氮化层（14）上形成介电常数值大于大约8.0的金属氧化物层（16）。在氮化层上形成金属栅极（20），由此剩余的复合栅极电介质（14和16）具有较大的物理厚度，但具有高性能的等效氧化物厚度（EOT）。

30. 发明授权

US5552332A Process for fabricating a MOSFET device having reduced reverse short channel effects 失效
标题翻译：具有减小的反向短通道效应的MOSFET器件的制造工艺
公开(公告)号：US5552332A
公开(公告)日：1996-09-03
申请号：US460339
申请日：1995-06-02
申请人： Hsing-Huang Tseng , Philip J. Tobin , Paul G. Y. Tsui , Shih W. Sun , Stephen S. Poon
发明人： Hsing-Huang Tseng , Philip J. Tobin , Paul G. Y. Tsui , Shih W. Sun , Stephen S. Poon
IPC分类号： H01L21/265 , H01L21/28 , H01L21/336 , H01L29/10 , H01L21/02
CPC分类号： H01L29/6659 , H01L21/26513 , H01L21/28176 , H01L29/1033 , H01L29/6656 , H01L29/7842 , Y10S438/91
摘要： A process for the fabrication of an MOSFET device includes the formation of a buffer layer (28) overlying the surface of a semiconductor substrate (14) adjacent to a gate electrode (18). A defect compensating species is diffused through the buffer layer (28) and through a gate dielectric layer (12) to form a defect-compensating region (30) at the surface (14) of the semiconductor substrate (10). The defect-compensating region (30) in conjunction with the buffer layer (28) minimize and control the population of point defects in the channel region (22) of the semiconductor substrate (10). By controlling the population of point defects in the channel region (22), a substantially uniform doping profile is maintained in a shallow doped region (16) formed in the semiconductor substrate (10) at the substrate surface (14). The maintenance of a uniform doping profile in the shallow doped region (16) results in improved threshold voltage stability as the lateral dimension of the channel region (22) is reduced.
摘要翻译：用于制造MOSFET器件的工艺包括形成覆盖在与栅电极（18）相邻的半导体衬底（14）的表面上的缓冲层（28）。缺陷补偿物质通过缓冲层（28）和栅极电介质层（12）扩散，以在半导体衬底（10）的表面（14）处形成缺陷补偿区域（30）。与缓冲层（28）结合的缺陷补偿区域（30）最小化并控制半导体衬底（10）的沟道区域（22）中的点缺陷的群体。通过控制沟道区域（22）中的点缺陷的群体，在衬底表面（14）处形成在半导体衬底（10）中的浅掺杂区域（16）中保持基本均匀的掺杂分布。在浅掺杂区域（16）中维持均匀的掺杂分布导致当沟道区域（22）的横向尺寸减小时阈值电压稳定性得到改善。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式