专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

21. 发明授权

US06140702A Plastic encapsulation for integrated circuits having plated copper top surface level interconnect 失效
标题翻译：具有电镀铜顶表面级互连的集成电路的塑料封装
公开(公告)号：US06140702A
公开(公告)日：2000-10-31
申请号：US864386
申请日：1997-05-28
申请人： Taylor R. Efland , Dale J. Skelton , Quang X. Mai , Charles E. Williams
发明人： Taylor R. Efland , Dale J. Skelton , Quang X. Mai , Charles E. Williams
IPC分类号： H01L21/60 , H01L23/48
CPC分类号： H01L24/05 , H01L24/48 , H01L2224/04042 , H01L2224/05647 , H01L2224/32245 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48247 , H01L2224/48465 , H01L2224/48647 , H01L2224/48747 , H01L2224/48847 , H01L2224/73265 , H01L24/45 , H01L2924/01004 , H01L2924/01013 , H01L2924/01014 , H01L2924/01022 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/10253 , H01L2924/1306 , H01L2924/14 , H01L2924/181
摘要： A plastic packaged integrated circuit (20) having a thick copper plated top surface level interconnection structure. A semiconductor integrated circuit (20) is formed having devices at the surface of a semiconductor substrate (23). First and second metallization layers (27, 31) are formed over the substrate and contacting selected ones of said devices. The first and second levels of metallization may be in contact with one another through vias. A thick top surface level metal interconnect layer (35) is then formed over the second metal layer (31), either physically contacting it or selectively electrically contacting it. The surface level metal (35) is fabricated of a highly conductive copper layer. The thick surface level metal layer (35) substantially lowers the resistance of the interconnect metallization of the device (20) and further eliminates current debiasing and early failure location problems experienced with integrated circuits of the prior art. In one embodiment, the copper surface level interconnect layer (35) is coated with a thin barrier layer of material (37) which may receive a bond wire. The entire structure is then encapsulated in a plastic package (22) such that the plastic is in physical contact with the copper interconnect metal (35). The use of the plastic packaging (22) in physical contact with the copper interconnect metal (35) eliminates the need for the passivation layers of the prior art. Other devices and methods are described.
摘要翻译：一种塑料封装集成电路（20），其具有厚镀铜的顶表面级互连结构。半导体集成电路（20）在半导体衬底（23）的表面形成有器件。第一和第二金属化层（27,31）形成在衬底上并且接触选定的所述器件。金属化的第一和第二层可以通过通孔彼此接触。然后在第二金属层（31）上形成厚的顶表面级金属互连层（35），或者物理地接触第二金属层或选择性地电接触它。表面金属（35）由高导电性铜层制成。厚表面金属层（35）基本上降低了器件（20）的互连金属化的电阻，并且进一步消除了现有技术的集成电路所经历的电流去差和早期故障定位问题。在一个实施例中，铜表面水平互连层（35）涂覆有可以接收接合线的材料（37）的薄阻挡层。然后将整个结构封装在塑料封装（22）中，使得塑料与铜互连金属（35）物理接触。与铜互连金属（35）物理接触的塑料封装（22）的使用消除了对现有技术的钝化层的需要。描述其他设备和方法。

22. 发明授权

US5468984A ESD protection structure using LDMOS diodes with thick copper interconnect 失效
标题翻译：使用具有厚铜互连的LDMOS二极管的ESD保护结构
公开(公告)号：US5468984A
公开(公告)日：1995-11-21
申请号：US333407
申请日：1994-11-02
申请人： Taylor R. Efland , Dave Cotton , Dale J. Skelton
发明人： Taylor R. Efland , Dave Cotton , Dale J. Skelton
IPC分类号： H01L29/78 , H01L21/8234 , H01L27/02 , H01L27/088 , H01L29/866 , H01L27/085
CPC分类号： H01L27/0255 , H01L23/4824 , H01L2924/0002 , Y10S438/983
摘要： An interconnection structure and method for a multiple zener diode ESD protectoin circuit for power semiconductor devices. A plurality of lateral Zener diodes is formed. Each device is formed of a plurality of cathode and anode diffusion regions to be coupled together to form the cathode and anode of one or more Zener diodes. Each diffusion region has a first metal layer stripe formed over it and in electrical contact with it. A second metal layer conductor is formed over a plurality of the first metal layer stripes, and selectively contacts the first metal layer stripes to form a bus. A thick third metal layer is then formed over each second metal layer bus, either physically contacting it or selectively electrically contacting it. The thick third level metal is fabricated of a highly conductive material, such as copper. The resulting Zener diodes are coupled together in an ESD structure using the second level busses and the thick copper third level busses. The ESD structure of the preferred embodiment has low overall resistance and fast time to breakdown and provides excellent protection for the circuits to be protected. Other devices, systems and methods are also disclosed.
摘要翻译：用于功率半导体器件的多齐纳二极管ESD保护电路的互连结构和方法。形成多个侧向齐纳二极管。每个器件由多个阴极和阳极扩散区域形成，以被耦合在一起以形成一个或多个齐纳二极管的阴极和阳极。每个扩散区具有形成在其上并与其电接触的第一金属层条纹。第二金属层导体形成在多个第一金属层条纹上，并且选择性地接触第一金属层条纹以形成总线。然后在每个第二金属层母线上形成厚的第三金属层，或者物理地接触它或选择性地电接触它。厚的第三级金属由诸如铜的高导电材料制成。所得的齐纳二极管使用第二级总线和厚铜第三级总线以ESD结构耦合在一起。优选实施例的ESD结构具有低的总体电阻和快速的击穿时间，并且为要保护的电路提供优异的保护。还公开了其他装置，系统和方法。

23. 发明授权

US5306652A Lateral double diffused insulated gate field effect transistor fabrication process 失效
标题翻译：横向双扩散绝缘栅场效应晶体管制造工艺
公开(公告)号：US5306652A
公开(公告)日：1994-04-26
申请号：US815732
申请日：1991-12-30
申请人： Oh-Kyong Kwon , Taylor R. Efland , Satwinder Malhi , Wai T. Ng
发明人： Oh-Kyong Kwon , Taylor R. Efland , Satwinder Malhi , Wai T. Ng
IPC分类号： H01L29/08 , H01L29/78 , H01L21/336
CPC分类号： H01L29/66681 , H01L29/7801 , H01L29/7816 , H01L29/7835 , H01L29/0847 , H01L29/0878 , Y10S148/096
摘要： A transistor (10) has a thin epitaxial layer (14) of a second conductivity type on a semiconductor substrate (12) of a first conductivity type. A drift region (24) of the second conductivity type is formed extending through the thin epitaxial layer (14) to the substrate (12) . A thick insulator layer (26) is formed on the drift region (24). An IGFET body (28) of the first conductivity type is formed adjacent the drift region (24). A source region (34) of the second conductivity type is formed within the IGFET body (28) and spaced from the drift region (24) defining a channel region (40) within the IGFET body (28). A conductive gate (32) is insulatively disposed over the IGFET body (28) and extends from the source region (34) to the thick insulator layer (26). A drain region (36) is formed adjacent the drift region (24).
摘要翻译：晶体管（10）在第一导电类型的半导体衬底（12）上具有第二导电类型的薄外延层（14）。形成第二导电类型的漂移区（24），延伸穿过薄外延层（14）到衬底（12）。在漂移区（24）上形成厚的绝缘体层（26）。第一导电类型的IGFET体（28）形成在漂移区（24）附近。第二导电类型的源极区域（34）形成在IGFET主体（28）内并且与漂移区域（24）间隔开，以限定IGFET体（28）内的沟道区域（40）。导电栅极（32）被绝缘地设置在IGFET主体（28）上并且从源极区域（34）延伸到厚的绝缘体层（26）。在漂移区（24）附近形成漏区（36）。

24. 发明授权

US07135759B2 Individualized low parasitic power distribution lines deposited over active integrated circuits 有权
标题翻译：沉积在有源集成电路上的个性化的低寄生配电线路
公开(公告)号：US07135759B2
公开(公告)日：2006-11-14
申请号：US10039663
申请日：2001-10-22
申请人： Taylor R. Efland , Milton L. Buschbom , Sameer Pendharkar
发明人： Taylor R. Efland , Milton L. Buschbom , Sameer Pendharkar
IPC分类号： H01L23/495
CPC分类号： H01L24/05 , H01L23/5286 , H01L24/06 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L2224/04042 , H01L2224/05083 , H01L2224/05147 , H01L2224/05155 , H01L2224/05166 , H01L2224/05171 , H01L2224/0518 , H01L2224/05184 , H01L2224/05187 , H01L2224/05554 , H01L2224/05624 , H01L2224/05639 , H01L2224/05644 , H01L2224/05664 , H01L2224/05669 , H01L2224/32245 , H01L2224/45015 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48227 , H01L2224/48247 , H01L2224/48465 , H01L2224/48624 , H01L2224/48639 , H01L2224/48644 , H01L2224/48664 , H01L2224/48669 , H01L2224/48724 , H01L2224/48739 , H01L2224/48744 , H01L2224/48764 , H01L2224/48769 , H01L2224/48824 , H01L2224/48839 , H01L2224/48844 , H01L2224/48864 , H01L2224/49175 , H01L2224/73265 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01019 , H01L2924/01022 , H01L2924/01024 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01031 , H01L2924/01032 , H01L2924/01042 , H01L2924/01047 , H01L2924/01049 , H01L2924/0105 , H01L2924/01074 , H01L2924/01075 , H01L2924/01076 , H01L2924/01078 , H01L2924/01079 , H01L2924/01083 , H01L2924/014 , H01L2924/04941 , H01L2924/05042 , H01L2924/13055 , H01L2924/14 , H01L2924/15724 , H01L2924/181 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/20752 , H01L2924/20753 , H01L2924/30105 , H01L2924/30107 , H01L2924/3011 , H01L2924/00014 , H01L2924/04953 , H01L2924/00 , H01L2924/00012 , H01L2224/48869
摘要： An integrated circuit (IC) chip, mounted on a leadframe, has a network of power distribution lines deposited on the surface of the chip so that these lines are located over active components of the IC, connected vertically by metal-filled vias to selected active components below the lines, and also by conductors to segments of the leadframe. Furthermore, the lines are fabricated with a sheet resistance of less than 1.5 mΩ/□ and the majority of the lines is patterned as straight lines between the vias and the conductors, respectively.
摘要翻译：安装在引线框架上的集成电路（IC）芯片具有沉积在芯片表面上的配电线网络，使得这些线路位于IC的有源元件上方，通过金属填充的通孔垂直连接到选定的有源线路下方的组件，以及引线框架的导体。此外，线路的薄层电阻小于1.5mOmega /□，并且大部分线路分别图案化为通孔和导体之间的直线。

25. 发明授权

US06930005B2 Low cost fabrication method for high voltage, high drain current MOS transistor 有权
标题翻译：低成本高漏极电流MOS晶体管制造方法
公开(公告)号：US06930005B2
公开(公告)日：2005-08-16
申请号：US10725642
申请日：2003-12-02
申请人： Taylor R. Efland , Jozef C. Mitros , Imran Khan
发明人： Taylor R. Efland , Jozef C. Mitros , Imran Khan
IPC分类号： H01L21/336 , H01L21/8234 , H01L29/08 , H01L29/10 , H01L29/423 , H01L29/78
CPC分类号： H01L29/0847 , H01L29/0878 , H01L29/1083 , H01L29/1087 , H01L29/42368 , H01L29/66659 , H01L29/7835
摘要： A method for reducing the drain resistance of a drain-extended MOS transistor in a semiconductor wafer, while maintaining a high transistor breakdown voltage. The method provides a first well (502) of a first conductivity type, operable as the extension of the transistor drain (501) of the first conductivity type; portions of the well are covered by a first insulator (503) having a first thickness. A second well (504) of the opposite conductivity type is intended to contain the transistor source (506) of the first conductivity type; portions of the second well are covered by a second insulator (507) thinner than the first insulator. The first and second wells form a junction (505) that terminates at the second insulator (530a, 530b). The method deposits a photoresist layer (510) over the wafer, which is patterned by opening a window (510a) that extends from the drain to the junction termination. Next, ions (540) of the first conductivity type are implanted through the window into the first well; these said ions have an energy to limit the penetration depth (541) to the first insulator thickness, and a dose to create a well region (560) of high doping concentration adjacent to the junction termination (530a).
摘要翻译：一种在保持高晶体管击穿电压的同时降低半导体晶片中的漏极扩展MOS晶体管的漏极电阻的方法。该方法提供第一导电类型的第一阱（502），其可操作为第一导电类型的晶体管漏极（501）的延伸; 阱的一部分被具有第一厚度的第一绝缘体（503）覆盖。相反导电类型的第二阱（504）旨在包含第一导电类型的晶体管源（506）; 第二阱的部分被比第一绝缘体薄的第二绝缘体（507）覆盖。第一和第二阱形成终止于第二绝缘体（530a，530b）的结（505）。该方法将光致抗蚀剂层（510）沉积在晶片之上，其通过打开从漏极延伸到结终端的窗口（510a）而被图案化。接下来，通过窗口将第一导电类型的离子（540）注入到第一阱中; 这些所述离子具有将穿透深度（541）限制到第一绝缘体厚度的能量，以及用于产生邻近连接终端（530a）的高掺杂浓度的阱区（560）的剂量。

26. 发明授权

US06873021B1 MOS transistors having higher drain current without reduced breakdown voltage 有权
标题翻译： MOS晶体管具有较高的漏极电流，而不降低击穿电压
公开(公告)号：US06873021B1
公开(公告)日：2005-03-29
申请号：US10725641
申请日：2003-12-02
申请人： Jozef C. Mitros , Imran Khan , Taylor R. Efland
发明人： Jozef C. Mitros , Imran Khan , Taylor R. Efland
IPC分类号： H01L21/336 , H01L29/08 , H01L29/10 , H01L29/423 , H01L29/76 , H01L29/78
CPC分类号： H01L29/7816 , H01L29/0878 , H01L29/1095 , H01L29/42368 , H01L29/66681
摘要： A drain-extended MOS transistor in a semiconductor wafer (300) of a first conductivity type comprises a first well (315) of the first conductivity type, operable as the extension of the transistor drain (305) of the first conductivity type, and covered by a first insulator (312) having a first thickness, and further a second well (302) of the opposite conductivity type, intended to contain the transistor source (304) of the first conductivity type, and covered by a second insulator (311) thinner than said first insulator (312). First and second wells form a junction (330) that terminates (320, 321) at the second insulator. The first well has a region (360) in the proximity of the junction termination, which has a higher doping concentration than the remainder of the first well and extends not deeper than the first insulator thickness. Region (360) of higher doping concentration reduces the transistor drain resistance so that the drain current is increased to approximately twice the value it had without the higher doping concentration, while the transistor breakdown voltage remains determined by the (low) doping concentration of the remainder of first well (315).
摘要翻译：第一导电类型的半导体晶片（300）中的漏极扩展MOS晶体管包括第一导电类型的第一阱（315），可用作第一导电类型的晶体管漏极（305）的延伸部分，并且被覆盖通过具有第一厚度的第一绝缘体（312）和另外具有相反导电类型的第二阱（302），用于容纳第一导电类型的晶体管源（304），并被第二绝缘体（311）覆盖，比所述第一绝缘体（312）薄。第一和第二阱形成在第二绝缘体处终止（320,321）的结（330）。第一阱具有在接合端子附近的区域（360），其具有比第一阱的其余部分更高的掺杂浓度，并且延伸不比第一绝缘体厚度更深。掺杂浓度较高的区域（360）降低了晶体管漏极电阻，使得漏极电流增加到其没有较高掺杂浓度的值的两倍，而晶体管击穿电压保持由其余部分的（低）掺杂浓度确定的第一井（315）。

27. 发明授权

US06710427B2 Distributed power device with dual function minority carrier reduction 有权
标题翻译：具有双功能少数载波减少的分布式功率器件
公开(公告)号：US06710427B2
公开(公告)日：2004-03-23
申请号：US10167136
申请日：2002-06-11
申请人： Taylor R. Efland , David A. Grant , Ramanathan Ramani , Chin-Yu Tsai , David D. Briggs , Dale Skelton
发明人： Taylor R. Efland , David A. Grant , Ramanathan Ramani , Chin-Yu Tsai , David D. Briggs , Dale Skelton
IPC分类号： H01L2900
CPC分类号： H01L29/1083 , H01L21/761 , H01L21/765 , H01L29/1045 , H01L29/7835
摘要： A distributed power device (100) including a plurality of tank regions (90) separated from one another by a deep n-type region (16), and having formed in each tank region a plurality of transistors (50). The plurality of transistors (50) in each tank region are interconnected to transistors in other tank regions to form a large power FET, whereby the deep n-type regions isolate the tank regions from one another. A first parasitic diode (D5) is defined from each tank region to a buried layer, and a second parasitic diode (D4) is defined between the buried layer and a substrate. The deep n-type regions distribute the first and second parasitic diodes with respect to the plurality of tank regions, preferably comprised of a P-epi tank. The deep n-type regions also distribute the resistance of an NBL layer (14) formed under the tank regions. The distributed parasitic diodes and resistance of the NBL layer advantageously provides that the parasitic diode (D4) between the NBL layer and the substrate will never be forward biased. In addition, each of the tank regions has a heavily doped p-type region (56) reducing the minority carrier lifetime to provide increased switching speed of the large power FET.
摘要翻译：一种分布式功率器件（100），包括通过深n型区域（16）彼此分离的多个槽区（90），并且在每个槽区中形成有多个晶体管（50）。每个槽区中的多个晶体管（50）与其它罐区中的晶体管相互连接以形成大功率FET，由此深n型区域将罐区彼此隔离。第一寄生二极管（D5）从每个槽区限定到埋层，并且在掩埋层和衬底之间限定第二寄生二极管（D4）。深n型区域相对于多个罐区域分布第一和第二寄生二极管，优选地由P-epi罐组成。深n型区域还分布形成在罐区域下方的NBL层（14）的电阻。分布式寄生二极管和NBL层的电阻有利地提供NBL层和衬底之间的寄生二极管（D4）将永远不会被正向偏置。此外，每个槽区具有重掺杂的p型区（56），减少了少量载流子寿命，以提供大功率FET的提高的开关速度。

28. 发明授权

US6160388A Sensing of current in a synchronous-buck power stage 有权
标题翻译：在同步降压功率级中检测电流
公开(公告)号：US6160388A
公开(公告)日：2000-12-12
申请号：US213681
申请日：1998-12-17
申请人： Dale J. Skelton , Chao-Chih Chiu , Taylor R. Efland
发明人： Dale J. Skelton , Chao-Chih Chiu , Taylor R. Efland
IPC分类号： H02M3/158 , G05F1/563
CPC分类号： H02M3/1588 , H02M2001/0009 , Y02B70/1466
摘要： A DC-DC converter that generates a sense signal representing a voltage drop across a low-side switch when the low-side switch is on. The sense signal is inverted and stored in a "hold" capacitor until the beginning of the next switching cycle. More specifically, an input node receives an input voltage V.sub.IN. A driver stage coupled to the input node and to a reference node chops V.sub.IN into a square wave under control of a PWM signal. The chopped V.sub.IN signal is coupled to an intermediate output node. An output stage coupled to the intermediate output node converts the chopped V.sub.IN signal to an output voltage V.sub.OUT to a load coupled to an output node. A sense unit coupled to sense a voltage on the intermediate output node generates a voltage signal indicating current flowing in the load.
摘要翻译： DC-DC转换器，当低侧开关接通时，产生表示低侧开关上的电压降的感测信号。感测信号被反相并存储在“保持”电容器中，直到下一个开关周期的开始。更具体地，输入节点接收输入电压VIN。耦合到输入节点和参考节点的驱动器级在PWM信号的控制下将VIN划分成方波。斩波的VIN信号耦合到中间输出节点。耦合到中间输出节点的输出级将斩波的VIN信号转换为耦合到输出节点的负载的输出电压VOUT。耦合以感测中间输出节点上的电压的感测单元产生指示在负载中流动的电流的电压信号。

29. 发明授权

US6147526A Ripple regulator with improved initial accuracy and noise immunity 有权
标题翻译：纹波调节器具有提高的初始精度和抗噪声能力
公开(公告)号：US6147526A
公开(公告)日：2000-11-14
申请号：US213308
申请日：1998-12-16
申请人： Dale J. Skelton , Steven C. Jones , Taylor R. Efland , Lester L. Hodson
发明人： Dale J. Skelton , Steven C. Jones , Taylor R. Efland , Lester L. Hodson
IPC分类号： H02M3/156 , H02M3/158 , H03K7/08
CPC分类号： H02M3/1563 , H02M3/1588 , Y02B70/1466
摘要： A DC--DC converter having an input node receiving an input voltage V.sub.IN and generating an output voltage V.sub.OUT. A reference voltage generator provides a voltage V.sub.REF and a hysteresis voltage generator provides a voltage V.sub.HYST. A first comparator generates a signal determined from a difference between V.sub.REF and V.sub.OUT. A second comparator generates a signal determined from a difference between V.sub.OUT and V.sub.HYST. A latch is coupled to receive the outputs of the first and second comparators, and to generate an output. A driver circuit receives the latch output and generates a PWM signal used to switch the output stage. A double pulse suppression circuit masks off the latch inputs for a preselected time during the switching intervals fo the main power transistors to eliminate noise jitter.
摘要翻译：一种具有输入节点接收输入电压VIN并产生输出电压VOUT的DC-DC转换器。参考电压发生器提供电压VREF，并且滞后电压发生器提供电压VHYST。第一比较器产生从VREF和VOUT之间的差确定的信号。第二比较器产生由VOUT和VHYST之间的差确定的信号。锁存器被耦合以接收第一和第二比较器的输出，并且产生输出。驱动器电路接收锁存器输出并产生用于切换输出级的PWM信号。双脉冲抑制电路在主功率晶体管的切换间隔期间屏蔽锁存器输入预选的时间以消除噪声抖动。

30. 发明授权

US5812006A Optimized power output clamping structure 失效
标题翻译：优化功率输出钳位结构
公开(公告)号：US5812006A
公开(公告)日：1998-09-22
申请号：US739375
申请日：1996-10-29
申请人： Ross E. Teggatz , Joseph A. Devore , Kenneth G. Buss , Thomas A. Schmidt , Taylor R. Efland , Stephen C. Kwan
发明人： Ross E. Teggatz , Joseph A. Devore , Kenneth G. Buss , Thomas A. Schmidt , Taylor R. Efland , Stephen C. Kwan
IPC分类号： H03K17/06 , H03K17/082 , H03K5/08
CPC分类号： H03K17/063 , H03K17/0822
摘要： An optimized power output clamping structure, includes a power output transistor having a first breakdown voltage and a breakdown structure having a second breakdown voltage coupled to the power output transistor. The second breakdown voltage is less than the first breakdown voltage and follows the first breakdown voltage across all temperature and semiconductor process variations. This feature allows a reduction in breakdown voltage guardbanding and increases output structure reliability. A method of protecting a circuit from inductive flyback is also disclosed. The method includes the steps of driving an inductive load with drive circuitry, turning off the inductive load, and clamping an inductive voltage at a voltage magnitude that protects the drive circuitry from breakdown across all temperature and processing variations.
摘要翻译：优化的功率输出钳位结构包括具有第一击穿电压的功率输出晶体管和具有耦合到功率输出晶体管的第二击穿电压的击穿结构。第二击穿电压小于第一击穿电压，并且遵循所有温度和半导体工艺变化的第一击穿电压。该特征允许降低击穿电压保护带并增加输出结构的可靠性。还公开了一种保护电路免受感应回扫的方法。该方法包括以下步骤：利用驱动电路驱动感性负载，关闭感性负载，以及钳位感应电压，电压幅度保护驱动电路不受所有温度和处理变化的影响。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式