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21. 发明授权

US07449782B2 Self-aligned metal to form contacts to Ge containing substrates and structure formed thereby 有权
标题翻译：自对准金属与Ge形成的基板和由此形成的结构形成接触
公开(公告)号：US07449782B2
公开(公告)日：2008-11-11
申请号：US10838378
申请日：2004-05-04
申请人： Cyril Cabral, Jr. , Roy A. Carruthers , Christophe Detavernier , Simon Gaudet , Christian Lavoie , Huiling Shang
发明人： Cyril Cabral, Jr. , Roy A. Carruthers , Christophe Detavernier , Simon Gaudet , Christian Lavoie , Huiling Shang
IPC分类号： H01L29/40
CPC分类号： H01L21/28525 , H01L21/28052 , H01L21/28518 , H01L29/665
摘要： A method for forming germano-silicide contacts atop a Ge-containing layer that is more resistant to etching than are conventional silicide contacts that are formed from a pure metal is provided. The method of the present invention includes first providing a structure which comprises a plurality of gate regions located atop a Ge-containing substrate having source/drain regions therein. After this step of the present invention, a Si-containing metal layer is formed atop the said Ge-containing substrate. In areas that are exposed, the Ge-containing substrate is in contact with the Si-containing metal layer. Annealing is then performed to form a germano-silicide compound in the regions in which the Si-containing metal layer and the Ge-containing substrate are in contact; and thereafter, any unreacted Si-containing metal layer is removed from the structure using a selective etch process. In some embodiments, an additional annealing step can follow the removal step. The method of the present invention provides a structure having a germano-silicide contact layer atop a Ge-containing substrate, wherein the germano-silicide contact layer contains more Si than the underlying Ge-containing substrate.
摘要翻译：提供了一种形成锗硅化物的方法，该方法与由纯金属形成的常规硅化物接触相比更能抵抗蚀刻的含Ge层顶部接触。本发明的方法包括首先提供一种结构，该结构包括位于其中具有源极/漏极区域的含Ge衬底顶部的多个栅极区域。在本发明的该步骤之后，在所述含Ge基材上形成含Si金属层。在暴露的区域中，含Ge衬底与含Si金属层接触。然后进行退火以在含Si金属层和含Ge基板接触的区域中形成锗化硅化合物; 此后，使用选择性蚀刻工艺从结构中除去任何未反应的含Si金属层。在一些实施方案中，附加的退火步骤可以跟随去除步骤。本发明的方法提供了一种在含Ge衬底顶上具有锗硅化物接触层的结构，其中锗硅化物接触层含有比下面的含Ge衬底更多的Si。

22. 发明授权

US07410852B2 Opto-thermal annealing methods for forming metal gate and fully silicided gate field effect transistors 有权
标题翻译：用于形成金属栅极和全硅化栅场效应晶体管的光热退火方法
公开(公告)号：US07410852B2
公开(公告)日：2008-08-12
申请号：US11408522
申请日：2006-04-21
申请人： Scott D. Allen , Cyril Cabral, Jr. , Kevin K. Dezfulian , Sunfei Fang , Brian J. Greene , Rajarao Jammy , Christian Lavoie , Zhijiong Luo , Hung Ng , Chun-Yung Sung , Clement H. Wann , Huilong Zhu
发明人： Scott D. Allen , Cyril Cabral, Jr. , Kevin K. Dezfulian , Sunfei Fang , Brian J. Greene , Rajarao Jammy , Christian Lavoie , Zhijiong Luo , Hung Ng , Chun-Yung Sung , Clement H. Wann , Huilong Zhu
IPC分类号： H01L21/8234 , H01L21/42
CPC分类号： H01L21/268 , H01L21/2686 , H01L21/28079 , H01L21/28088 , H01L21/28097 , H01L21/28176 , H01L21/324 , H01L29/517 , H01L29/665
摘要： An opto-thermal annealing method for forming a field effect transistor uses a reflective metal gate so that electrical properties of the metal gate and also interface between the metal gate and a gate dielectric are not compromised when opto-thermal annealing a source/drain region adjacent the metal gate. Another opto-thermal annealing method may be used for simultaneously opto-thermally annealing: (1) a silicon layer and a silicide forming metal layer to form a fully silicided gate; and (2) a source/drain region to form an annealed source/drain region. An additional opto-thermal annealing method may use a thermal insulator layer in conjunction with a thermal absorber layer to selectively opto-thermally anneal a silicon layer and a silicide forming metal layer to form a fully silicide gate.
摘要翻译：用于形成场效应晶体管的光热退火方法使用反射金属栅极，使得当相邻的源极/漏极区域进行光热退火时，金属栅极的电特性以及金属栅极和栅极电介质之间的界面不受损害金属门。另一种光热退火方法可以用于同时光热退火：（1）硅层和形成硅化物的金属层以形成完全硅化的栅极; 和（2）源/漏区以形成退火的源/漏区。附加的光热退火方法可以使用与热吸收层结合的热绝缘体层来选择性地使硅层和形成硅化物的金属层光退火以形成完全硅化物栅极。

23. 发明授权

US07112481B2 Method for forming self-aligned dual salicide in CMOS technologies 失效
标题翻译：在CMOS技术中形成自对准双重自杀机的方法
公开(公告)号：US07112481B2
公开(公告)日：2006-09-26
申请号：US11254929
申请日：2005-10-20
申请人： Sunfei Fang , Cyril Cabral, Jr. , Chester T. Dziobkowski , John J. Ellis-Monaghan , Christian Lavoie , Zhijiong Luo , James S. Nakos , An L. Steegen , Clement H. Wann
发明人： Sunfei Fang , Cyril Cabral, Jr. , Chester T. Dziobkowski , John J. Ellis-Monaghan , Christian Lavoie , Zhijiong Luo , James S. Nakos , An L. Steegen , Clement H. Wann
IPC分类号： H01L21/8238
CPC分类号： H01L21/28518 , H01L21/823814 , H01L21/823835
摘要： A method of fabricating a complementary metal oxide semiconductor (CMOS) device, wherein the method comprises forming a first well region in a semiconductor substrate for accommodation of a first type semiconductor device; forming a second well region in the semiconductor substrate for accommodation of a second type semiconductor device; shielding the first type semiconductor device with a mask; depositing a first metal layer over the second type semiconductor device; performing a first salicide formation on the second type semiconductor device; removing the mask; depositing a second metal layer over the first and second type semiconductor devices; and performing a second salicide formation on the first type semiconductor device. The method requires only one pattern level and it eliminates pattern overlay as it also simplifies the processes to form different silicide material over different devices.
摘要翻译：一种制造互补金属氧化物半导体（CMOS）器件的方法，其中所述方法包括在用于容纳第一类型半导体器件的半导体衬底中形成第一阱区; 在所述半导体衬底中形成用于容纳第二类型半导体器件的第二阱区; 用掩模屏蔽第一类型半导体器件; 在所述第二类型半导体器件上沉积第一金属层; 在所述第二类型半导体器件上执行第一自对准硅化物形成; 去除面膜; 在所述第一和第二类型半导体器件上沉积第二金属层; 以及在所述第一类型半导体器件上执行第二自对准硅化物形成。该方法仅需要一个图案级别，并且消除图案覆盖，因为它也简化了在不同设备上形成不同硅化物材料的工艺。

24. 发明授权

US07102234B2 Method and structure for reduction of contact resistance of metal silicides using a metal-germanium alloy 有权
标题翻译：使用金属锗合金降低金属硅化物的接触电阻的方法和结构
公开(公告)号：US07102234B2
公开(公告)日：2006-09-05
申请号：US10827064
申请日：2004-04-19
申请人： Cyril Cabral, Jr. , Roy Arthur Carruthers , James McKell Edwin Harper , Christian Lavoie , Ronnen Andrew Roy , Yun Yu Wang
发明人： Cyril Cabral, Jr. , Roy Arthur Carruthers , James McKell Edwin Harper , Christian Lavoie , Ronnen Andrew Roy , Yun Yu Wang
IPC分类号： H01L23/48 , H01L29/40
CPC分类号： H01L21/28518
摘要： A method of reducing the contact resistance of metal silicides to the p+ silicon area or the n+ silicon area of the substrate comprising: (a) forming a metal germanium (Ge) layer over a silicon-containing substrate, wherein said metal is selected from the group consisting of Co, Ti, Ni and mixtures thereof; (b) optionally forming an oxygen barrier layer over said metal germanium layer; (c) annealing said metal germanium layer at a temperature which is effective in converting at least a portion thereof into a substantially non-etchable metal silicide layer, while forming a Si—Ge interlayer between said silicon-containing substrate and said substantially non-etchable metal silicide layer; and (d) removing said optional oxygen barrier layer and any remaining alloy layer. When a Co or Ti alloy is employed, e.g., Co—Ge or Ti—Ge, two annealing steps are required to provide the lowest resistance phase of those metals, whereas, when Ni is employed, a single annealing step forms the lowest resistance phase of Ni silicide.
摘要翻译：一种降低金属硅化物与衬底的p +硅区域或n +硅区域的接触电阻的方法，包括：（a）在含硅衬底上形成金属锗（Ge）层，其中所述金属选自由Co，Ti，Ni及其混合物组成的组; （b）任选地在所述金属锗层上形成氧阻隔层; （c）在有效地将其至少一部分转化成基本上不可蚀刻的金属硅化物层的温度下退火所述金属锗层，同时在所述含硅衬底和所述基本上不可蚀刻的衬底之间形成Si-Ge中间层金属硅化物层; 和（d）去除所述任选的氧气阻挡层和任何剩余的合金层。当使用Co或Ti合金时，例如Co-Ge或Ti-Ge，需要两个退火步骤来提供这些金属的最低电阻相，而在使用Ni时，单个退火步骤形成最低的电阻相的Ni硅化物。

25. 发明授权

US07067368B1 Method for forming self-aligned dual salicide in CMOS technologies 有权
公开(公告)号：US07067368B1
公开(公告)日：2006-06-27
申请号：US11254934
申请日：2005-10-20
申请人： Sunfei Fang , Cyril Cabral, Jr. , Chester T. Dziobkowski , John J. Ellis-Monaghan , Christian Lavoie , Zhijiong Luo , James S. Nakos , An L. Steegen , Clement H. Wann
发明人： Sunfei Fang , Cyril Cabral, Jr. , Chester T. Dziobkowski , John J. Ellis-Monaghan , Christian Lavoie , Zhijiong Luo , James S. Nakos , An L. Steegen , Clement H. Wann
IPC分类号： H01L21/8238
CPC分类号： H01L21/28518 , H01L21/823814 , H01L21/823835
摘要： A method of fabricating a complementary metal oxide semiconductor (CMOS) device, wherein the method comprises forming a first well region in a semiconductor substrate for accommodation of a first type semiconductor device; forming a second well region in the semiconductor substrate for accommodation of a second type semiconductor device; shielding the first type semiconductor device with a mask; depositing a first metal layer over the second type semiconductor device; performing a first salicide formation on the second type semiconductor device; removing the mask; depositing a second metal layer over the first and second type semiconductor devices; and performing a second salicide formation on the first type semiconductor device. The method requires only one pattern level and it eliminates pattern overlay as it also simplifies the processes to form different silicide material over different devices.

26. 发明授权

US07064025B1 Method for forming self-aligned dual salicide in CMOS technologies 有权
公开(公告)号：US07064025B1
公开(公告)日：2006-06-20
申请号：US10904884
申请日：2004-12-02
申请人： Sunfei Fang , Cyril Cabral, Jr. , Chester T. Dziobkowski , John J. Ellis-Monaghan , Christian Lavoie , Zhijiong Luo , James S. Nakos , An L. Steegen , Clement H. Wann
发明人： Sunfei Fang , Cyril Cabral, Jr. , Chester T. Dziobkowski , John J. Ellis-Monaghan , Christian Lavoie , Zhijiong Luo , James S. Nakos , An L. Steegen , Clement H. Wann
IPC分类号： H01L21/8238
CPC分类号： H01L21/28518 , H01L21/823814 , H01L21/823835
摘要： A method of fabricating a complementary metal oxide semiconductor (CMOS) device, wherein the method comprises forming a first well region in a semiconductor substrate for accommodation of a first type semiconductor device; forming a second well region in the semiconductor substrate for accommodation of a second type semiconductor device; shielding the first type semiconductor device with a mask; depositing a first metal layer over the second type semiconductor device; performing a first salicide formation on the second type semiconductor device; removing the mask; depositing a second metal layer over the first and second type semiconductor devices; and performing a second salicide formation on the first type semiconductor device. The method requires only one pattern level and it eliminates pattern overlay as it also simplifies the processes to form different silicide material over different devices.

27. 发明授权

US06989322B2 Method of forming ultra-thin silicidation-stop extensions in mosfet devices 有权
标题翻译：在mosfet器件中形成超薄硅化 - 停止延伸的方法
公开(公告)号：US06989322B2
公开(公告)日：2006-01-24
申请号：US10707175
申请日：2003-11-25
申请人： Oleg G. Gluschenkov , Cyril Cabral, Jr. , Omer Dokumaci , Christian Lavoie
发明人： Oleg G. Gluschenkov , Cyril Cabral, Jr. , Omer Dokumaci , Christian Lavoie
IPC分类号： H01L21/3205 , H01L21/4763
CPC分类号： H01L29/0847 , H01L21/28518 , H01L29/665 , H01L29/66636 , H01L29/7833
摘要： Very low resistance, scaled in MOSFET devices are formed by employing thin silicidation-stop extension that act both as a silicidation “stop” barriers and as thin interface layers between source/drain silicide regions and channel region of the MOSFET. By acting as silicidation stops, the silicidation-stop extensions confine silicidation, and are not breached by source/drain silicide. This permits extremely thin, highly-doped silicidation-stop extensions to be formed between the silicide and the channel, providing an essentially ideal, low series resistance interface between the silicide and the channel.
摘要翻译：通过使用薄硅化停止扩展来形成MOSFET器件中的非常低的电阻，其既用作硅化“阻挡”势垒，又作为源/漏硅化物区域和MOSFET的沟道区之间的薄界面层。通过作为硅化停止，硅化 - 停止扩展限制硅化，并且不被源/漏硅化物破坏。这允许在硅化物和沟道之间形成非常薄的，高掺杂的硅化 - 停止延伸，在硅化物和沟道之间提供基本理想的低串联电阻接口。

28. 发明授权

US06905560B2 Retarding agglomeration of Ni monosilicide using Ni alloys 有权
公开(公告)号：US06905560B2
公开(公告)日：2005-06-14
申请号：US10334464
申请日：2002-12-31
申请人： Cyril Cabral, Jr. , Roy A. Carruthers , Christophe Detavernier , James M. E. Harper , Christian Lavoie
发明人： Cyril Cabral, Jr. , Roy A. Carruthers , Christophe Detavernier , James M. E. Harper , Christian Lavoie
IPC分类号： C04B35/58 , C22F1/00 , C23C10/00 , H01L21/283 , H01L21/285 , H01L21/3205 , H01L21/44 , H01L21/60 , H01L21/768
CPC分类号： C04B35/58 , C04B35/58085 , C04B2235/40 , C04B2235/404 , C04B2235/405 , C04B2235/408 , C23C26/00 , C23C30/00 , H01L21/28518 , H01L21/76889
摘要： A method for providing a low resistance non-agglomerated Ni monosilicide contact that is useful in semiconductor devices. Where the inventive method of fabricating a substantially non-agglomerated Ni alloy monosilicide comprises the steps of: forming a metal alloy layer over a portion of a Si-containing substrate, wherein said metal alloy layer comprises of Ni and one or multiple alloying additive(s), where said alloying additive is Ti, V, Ge, Cr, Zr, Nb, Mo, Hf, Ta, W, Re, Rh, Pd or Pt or mixtures thereof; annealing the metal alloy layer at a temperature to convert a portion of said metal alloy layer into a Ni alloy monosilicide layer; and removing remaining metal alloy layer not converted into Ni alloy monosilicide. The alloying additives are selected for phase stability and to retard agglomeration. The alloying additives most efficient in retarding agglomeration are most efficient in producing silicides with low sheet resistance.

29. 发明授权

US06809030B2 Method and structure for controlling the interface roughness of cobalt disilicide 失效
标题翻译：控制二硅化钴界面粗糙度的方法和结构
公开(公告)号：US06809030B2
公开(公告)日：2004-10-26
申请号：US10185547
申请日：2002-06-28
申请人： Paul David Agnello , Cyril Cabral, Jr. , Roy Arthur Carruthers , James McKell Edwin Harper , Christian Lavoie , Kirk David Peterson , Robert Joseph Purtell , Ronnen Andrew Roy , Jean Louise Jordan-Sweet , Yun Yu Wang
发明人： Paul David Agnello , Cyril Cabral, Jr. , Roy Arthur Carruthers , James McKell Edwin Harper , Christian Lavoie , Kirk David Peterson , Robert Joseph Purtell , Ronnen Andrew Roy , Jean Louise Jordan-Sweet , Yun Yu Wang
IPC分类号： H01L2144
CPC分类号： H01L23/485 , H01L21/28518 , H01L2924/0002 , H01L2924/00
摘要： A method of producing electrical contacts having reduced interface roughness as well as the electrical contacts themselves are disclosed herein. The method of the present invention comprises (a) forming an alloy layer having the formula MX, wherein M is a metal selected from the group consisting of Co and Ni and X is an alloying additives over a silicon-containing substrate; (b) optionally forming an optional oxygen barrier layer over said alloy layer; (c) annealing said alloy layer at a temperature sufficient to form a MXSi layer in said structure; (d) removing said optional oxygen barrier layer and any remaining alloy layer; and optionally (e) annealing said MXSi layer at a temperature sufficient to form a MXSi2 layer in said structure.
摘要翻译：本文公开了一种制造具有降低的界面粗糙度的电接触以及电接触本身的方法。本发明的方法包括（a）形成具有式MX的合金层，其中M是选自Co和Ni的金属，X是含硅基体上的合金添加剂; （b）任选地在所述合金层上形成任选的氧阻隔层; （c）在足以在所述结构中形成MXSi层的温度下退火所述合金层; （d）除去所述任选的氧气阻挡层和任何剩余的合金层; 以及任选地（e）在足以在所述结构中形成MXSi 2层的温度下退火所述MXSi层。

30. 发明授权

US06753606B2 Method and structure for reduction of contact resistance of metal silicides using a metal-germanium alloy 有权
标题翻译：使用金属锗合金降低金属硅化物的接触电阻的方法和结构
公开(公告)号：US06753606B2
公开(公告)日：2004-06-22
申请号：US09994954
申请日：2001-11-27
申请人： Cyril Cabral, Jr. , Roy Arthur Carruthers , James McKell Edwin Harper , Christian Lavoie , Ronnen Andrew Roy , Yun Yu Wang
发明人： Cyril Cabral, Jr. , Roy Arthur Carruthers , James McKell Edwin Harper , Christian Lavoie , Ronnen Andrew Roy , Yun Yu Wang
IPC分类号： H01L2348
CPC分类号： H01L21/28518
摘要： A method of reducing the contact resistance of metal silicides to the p+ silicon area or the n+ silicon area of the substrate comprising: (a) forming a metal germanium (Ge) layer over a silicon-containing substrate, wherein said metal is selected from the group consisting of Co, Ti, Ni and mixtures thereof; (b) optionally forming an oxygen barrier layer over said metal germanium layer; (c) annealing said metal germanium layer at a temperature which is effective in converting at least a portion thereof into a substantially non-etchable metal silicide layer, while forming a Si—Ge interlayer between said silicon-containing substrate and said substantially non-etchable metal silicide layer; and (d) removing said optional oxygen barrier layer and any remaining alloy layer. When a Co or Ti alloy is employed, e.g., Co—Ge or Ti—Ge, two annealing steps are required to provide the lowest resistance phase of those metals, whereas, when Ni is employed, a single annealing step forms the lowest resistance phase of Ni silicide.
摘要翻译：一种降低金属硅化物与衬底的p +硅区域或n +硅区域的接触电阻的方法，包括：（a）在含硅衬底上形成金属锗（Ge）层，其中所述金属选自由Co，Ti，Ni及其混合物组成的组; （b）任选地在所述金属锗层上形成氧阻隔层; （c）在有效地将其至少一部分转化成基本上不可蚀刻的金属硅化物层的温度下退火所述金属锗层，同时在所述含硅衬底和所述基本上不可蚀刻的衬底之间形成Si-Ge中间层金属硅化物层; 和（d）去除所述任选的氧气阻挡层和任何剩余的合金层。当使用Co或Ti合金时，例如Co-Ge或Ti-Ge，需要两个退火步骤来提供这些金属的最低电阻相，而在使用Ni时，单个退火步骤形成最低的电阻相的Ni硅化物。

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