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21. 发明授权

US5856891A MR resistive-biasing scheme providing low noise high common-mode rejection and high supply rejection 失效
标题翻译： MR电阻偏置方案提供低噪声高共模抑制和高电源抑制
公开(公告)号：US5856891A
公开(公告)日：1999-01-05
申请号：US786269
申请日：1997-01-22
申请人： Tuan V. Ngo
发明人： Tuan V. Ngo
IPC分类号： G11B5/00 , G11B5/012 , G11B5/48 , H03F3/45 , G11B5/03
CPC分类号： H03F3/45479 , G11B5/012 , G11B2005/0018 , G11B5/4886
摘要： The present invention is a system for reading information stored on a plurality of disk surfaces. The system comprises a plurality of channels each containing a preamplifier having first and second terminals for connection to an MR head. A bias circuit is provided common to all of the plurality of channels. The preamplifier in each channel includes first and second channel select circuits responsive to first and second channel select signals and current output from the bias circuit to output currents based on the current's output from the bias circuit. The preamplifier in each channel also includes first and second complementary output transistor circuits responsive to the current's output from the first and second channel select circuits and to the first and second voltages to provide bias current through the respective MR head connected between the first and second terminals of the respective channel. The system is entirely symmetrical around ground for improved common mode rejection. In another aspect of the system, first and second supply rejection circuits are provided to stabilize voltages at the first and second terminals for variations in the positive and negative power supplies.
摘要翻译：本发明是用于读取存储在多个盘表面上的信息的系统。该系统包括多个通道，每个通道包含具有用于连接到MR头的第一和第二端子的前置放大器。为所述多个通道的所有通道提供偏置电路。每个通道中的前置放大器包括响应于第一和第二通道选择信号的第一和第二通道选择电路以及来自偏置电路的电流输出，以基于来自偏置电路的电流输出来输出电流。每个通道中的前置放大器还包括响应于来自第一和第二通道选择电路的电流输出以及第一和第二电压的第一和第二互补输出晶体管电路，以提供通过连接在第一和第二端子之间的相应MR头的偏置电流的相应通道。该系统在地面上完全对称，以改善共模抑制。在该系统的另一方面，提供第一和第二电源抑制电路以稳定第一和第二端子处的电压，用于正电源和负电源的变化。

22. 发明授权

US5834952A Open-loop current mode biasing scheme for MR head 失效
标题翻译： MR头的开环电流模式偏置方案
公开(公告)号：US5834952A
公开(公告)日：1998-11-10
申请号：US728662
申请日：1996-10-10
申请人： Tuan V. Ngo
发明人： Tuan V. Ngo
IPC分类号： G01R1/07 , G01R33/09 , G11B5/00 , G11B5/012 , G11B5/02 , H03F1/56 , G01R19/00
CPC分类号： G11B5/02 , G01R1/07 , G01R33/09 , G11B5/012 , H03F1/56 , G11B2005/0018
摘要： A biasing circuit for a two terminal sensing element has two separate biasing elements. Both biasing elements are controlled by a transconductance feedback circuit that controls feedback currents based upon a voltage associated with the sensing element. Both biasing elements also receive an activation value from an activation circuit. The activation value activates both biasing elements directly, without using the feedback loop.
摘要翻译：用于双端子感测元件的偏置电路具有两个单独的偏置元件。两个偏置元件由跨导反馈电路控制，跨电反馈电路基于与感测元件相关联的电压来控制反馈电流。两个偏置元件也从激活电路接收激活值。激活值直接激活两个偏置元件，而不使用反馈回路。

23. 发明授权

US5721484A Power supply filter with active element assist 失效
标题翻译：具有有源元件辅助功能的电源滤波器
公开(公告)号：US5721484A
公开(公告)日：1998-02-24
申请号：US769125
申请日：1996-12-19
申请人： Tuan V. Ngo , John D. Leighton
发明人： Tuan V. Ngo , John D. Leighton
IPC分类号： G05F3/26 , G05F3/16
CPC分类号： G05F3/265
摘要： A power supply filter is constructed with a capacitive element and an active element coupled to a filtered node and an impedance coupled between the filtered node and a power supply node. The filtered node for carrying a filtered version of a power supply signal on the power supply node. The active element having electrical characteristics such that the addition of the active element to the power supply filter reduces the amount of capacitance needed from the capacitive element to achieve a desired pole frequency for a given voltage drop across the impedance element.
摘要翻译：电源滤波器由电容元件和耦合到滤波节点的有源元件和耦合在滤波后的节点与电源节点之间的阻抗构成。用于在电源节点上携带电源信号的滤波版本的滤波节点。具有电特性的有源元件使得将有源元件添加到电源滤波器减少了从电容元件所需的电容量，以达到阻抗元件上的给定电压降达到期望的极点频率。

24. 发明授权

US5349253A Logic translator interfacing between five-volt TTL/CMOS and three-volt CML 失效
标题翻译：五伏TTL / CMOS和三伏CML之间的逻辑转换器接口
公开(公告)号：US5349253A
公开(公告)日：1994-09-20
申请号：US992544
申请日：1992-12-17
申请人： Tuan V. Ngo , John J. Price, Jr.
发明人： Tuan V. Ngo , John J. Price, Jr.
IPC分类号： H03K19/018
CPC分类号： H03K19/01812
摘要： A logic translating buffer for low voltage operation for receiving a TTL compatible signal and providing a current mode logic signal. The logic translating buffer includes an emitter coupled differential pair of NPN transistors with the common emitters each being connected to a current source. One of the transistors of the differential pair has a constant voltage bias applied to the base thereof that is equal to the sum of a forward biased PN junction, a forward biased Schottky diode, and the voltage drop across a first resistor. The other transistor of the differential pair is provided a signal that is representative of the logic level input to the translating buffer. A clamping transistor is provided for keeping the other transistor of the differential pair from saturating.
摘要翻译：用于低电压操作的逻辑翻译缓冲器，用于接收TTL兼容信号并提供电流模式逻辑信号。逻辑转换缓冲器包括发射极耦合的NPN晶体管的差分对，每个公共发射极连接到电流源。差分对的晶体管之一具有施加到其基极的恒定电压偏置，其等于正向偏置的PN结，正向偏置的肖特基二极管和跨第一电阻器的电压降的和。差分对的另一晶体管被提供表示输入到转换缓冲器的逻辑电平的信号。提供钳位晶体管用于保持差分对的另一个晶体管饱和。

25. 发明授权

US5291347A Write driver with H-switch synchronizing transistors 失效
标题翻译：用H开关同步晶体管写驱动
公开(公告)号：US5291347A
公开(公告)日：1994-03-01
申请号：US067673
申请日：1993-05-26
申请人： Tuan V. Ngo , Douglas R. Peterson
发明人： Tuan V. Ngo , Douglas R. Peterson
IPC分类号： G11B5/09 , G11B5/02 , G11B5/03
CPC分类号： G11B5/022 , G11B5/09
摘要： A write driver for driving a transducer in a storage system. The write driver includes first and second supply terminals and a H-switch for switching current flow through the transducer between a first direction and a second direction, opposite to the first direction. The H-switch includes pull-up transistors and pull-down transistors connected across the transducer for switching current flow through the transducer. Each pull-up transistor and pull-down transistor has a control terminal for controlling current flow through the transistor. The write driver further includes data input terminals for receiving data signals. A bias circuit is connected between the control terminals of the pull-up and pull-down transistors and the data input terminals for switching the pull-up and pull-down transistors between conducting and non-conducting states as a function of the received data signals. Each pull-down transistor has a corresponding synchronizing transistor connected between the control terminal of the pull-down transistor and the second supply terminal, which pulls current away from the control terminal of the pull-down transistor when the pull-down transistor is switched to the non-conducting state.
摘要翻译：用于驱动存储系统中的换能器的写入驱动器。写入驱动器包括第一和第二电源端子和H开关，用于在与第一方向相反的第一方向和第二方向之间切换通过换能器的电流。 H开关包括连接在换能器上的上拉晶体管和下拉晶体管，用于切换通过换能器的电流。每个上拉晶体管和下拉晶体管具有用于控制通过晶体管的电流的控制端子。写入驱动器还包括用于接收数据信号的数据输入端。偏置电路连接在上拉和下拉晶体管的控制端子和数据输入端之间，用于根据接收的数据信号在导通状态和非导通状态之间切换上拉和下拉晶体管。每个下拉晶体管具有连接在下拉晶体管的控制端子和第二电源端子之间的对应的同步晶体管，当下拉晶体管切换到时，其将电流从下拉晶体管的控制端子拉出非导电状态。

26. 发明授权

US07006313B2 Circuit and method to match common mode flex impedance and to achieve symmetrical switching voltage outputs of write driver 有权
公开(公告)号：US07006313B2
公开(公告)日：2006-02-28
申请号：US10179561
申请日：2002-06-25
申请人： Tuan V. Ngo
发明人： Tuan V. Ngo
IPC分类号： G11B5/09
CPC分类号： G11B5/022 , G11B5/012 , G11B5/02 , G11B2005/001 , G11B2005/0013 , H03K17/663
摘要： A write driver 100, 200, 300 is implemented to provide near-ground common mode output voltages to produce a more symmetrical head voltage swing (i.e. ±0.4V from ground to ±5V supply voltages). These features help to reduce the effects of common mode impedance associated with the interconnection to the disk drive head to improve overall performance. Lower jitter at high data rates can be achieved when compared to prior art techniques for implementing current mode write drivers. Further, the matched impedance between the write driver 100 and the interconnection 106 eliminates unwanted reflections. ECL level voltage swings (200–500 mV) have replaced more conventional CMOS level voltage swings (5V) to further reduce overall power dissipation associated with the write driver. The small ECL level switching further maintains constant power dissipation with changes in operating frequency and results in less NTLS effects due to quieter supplies.

27. 发明授权

US06275347B1 Current bias, current sense preamplifier for a magnetoresistive reader 有权
标题翻译：用于磁阻读取器的电流偏置电流检测前置放大器
公开(公告)号：US06275347B1
公开(公告)日：2001-08-14
申请号：US09285397
申请日：1999-04-02
申请人： Tuan V. Ngo , John D. Leighton
发明人： Tuan V. Ngo , John D. Leighton
IPC分类号： G11B509
CPC分类号： G11B5/02 , G11B5/012 , G11B2005/0018
摘要： A read system for reading information from a storage medium and for providing an output signal to circuitry external from the read system is disclosed. The read system includes individual channel circuitry, a bias current generator for providing a bias current to the read system, and preamplifier circuitry connected between the bias current generator and the individual channel circuitry. The individual channel circuitry further includes a first and a second magnetoresistive element, a first and a second transistor, and a first and a second switch. The preamplifier circuit further includes a first and a second capacitor connected between a low potential and the first and second switches, respectively, and a third capacitor connected between the first and second capacitors. The preamplifier also includes a first and a second operational amplifier having an output connected to a base of the first transistor and a base of the second transistor. respectively, and a feedback unit connected to the bias current generator.
摘要翻译：公开了一种用于从存储介质读取信息并向读取系统外部的电路提供输出信号的读取系统。读取系统包括单独的通道电路，用于向读取系统提供偏置电流的偏置电流发生器以及连接在偏置电流发生器和各个通道电路之间的前置放大器电路。单个通道电路还包括第一和第二磁阻元件，第一和第二晶体管以及第一和第二开关。前置放大器电路还包括分别连接在低电位与第一和第二开关之间的第一和第二电容器，以及连接在第一和第二电容器之间的第三电容器。前置放大器还包括具有连接到第一晶体管的基极和第二晶体管的基极的输出的第一和第二运算放大器。以及连接到偏置电流发生器的反馈单元。

28. 发明授权

US06236246B1 Voltage-mode boosting circuit for write driver 有权
标题翻译：用于写入驱动器的电压模式升压电路
公开(公告)号：US06236246B1
公开(公告)日：2001-05-22
申请号：US09432951
申请日：1999-11-03
申请人： John D. Leighton , Tuan V. Ngo
发明人： John D. Leighton , Tuan V. Ngo
IPC分类号： H03B100
CPC分类号： G11B5/022 , G11B5/012 , G11B5/02 , G11B5/09 , G11B2005/0013 , H03K17/663 , H03K17/6872
摘要： A voltage boost circuit for a write driver includes first and second semiconductor devices, such as Schottky diodes, coupled to respective first and second nodes to conduct write current through respective first or second current switches of the write driver when a forward voltage across the respective first or second semiconductor device exceeds a design voltage. The first and second current switches are responsive to respective complementary first and second input signals to direct write current in opposite directions through the winding between the first and second nodes. First and second storage devices are connected to the respective first and second semiconductor devices, and first and second buffers are responsive to a first state of the respective first and second input signals to operate the respective first or second storage device to increase the forward voltage across the respective first or second semiconductor device. Preferably, each buffer is responsive to a second state of the respective input signal to operate the respective storage device to decrease the forward voltage across the respective semiconductor device.
摘要翻译：用于写入驱动器的升压电路包括耦合到相应的第一和第二节点的第一和第二半导体器件（例如肖特基二极管），以在写入驱动器的相应的第一或第二电流开关导通写入电流时，或第二半导体器件超过设计电压。第一和第二电流开关响应相应的互补的第一和第二输入信号，以通过第一和第二节点之间的绕组在相反方向引导写入电流。第一和第二存储设备连接到相应的第一和第二半导体器件，并且第一和第二缓冲器响应于相应的第一和第二输入信号的第一状态来操作相应的第一或第二存储器件以增加跨过相应的第一或第二半导体器件。优选地，每个缓冲器响应于相应输入信号的第二状态来操作相应的存储装置以减小横跨相应半导体器件的正向电压。

29. 发明授权

US6128146A Undershoot active damping circuit for write drivers 有权
标题翻译：用于写入驱动器的下冲主动阻尼电路
公开(公告)号：US6128146A
公开(公告)日：2000-10-03
申请号：US168495
申请日：1998-10-08
申请人： Tuan V. Ngo
发明人： Tuan V. Ngo
IPC分类号： G11B5/012 , G11B5/02 , G11B5/09
CPC分类号： G11B5/022 , G11B5/012 , G11B5/02 , G11B5/09
摘要： A current driver for supplying write current to an inductive write head of a disk drive includes an H-switch and first and second damping circuits connected across the inductive head. Each damping circuit includes a first controlled resistor (such as a MOS transistor) connected across the head. A delay circuit is connected between a load terminal at one side of the head and the control terminal of the MOS transistor, and is responsive to a transient voltage at the load terminal to delay the transient voltage to the control terminal of the MOS transistor for a predetermined delay period. The MOS transistor is responsive to the delayed transient voltage to provide a predetermined electrical resistance across the head to dampen undershoot and ringing in the driver. The MOS transistor turns off when the voltage at the load terminals stabilizes, thereby removing the damping resistance from the circuit.
摘要翻译：用于向磁盘驱动器的感应写入头提供写入电流的电流驱动器包括H形开关以及连接在感应头上的第一和第二阻尼电路。每个阻尼电路包括跨越头部连接的第一受控电阻器（例如MOS晶体管）。延迟电路连接在头部一侧的负载端子与MOS晶体管的控制端子之间，并响应于负载端子处的瞬态电压，将瞬态电压延迟到MOS晶体管的控制端子预定的延迟期。 MOS晶体管响应于延迟的瞬态电压以在头部上提供预定的电阻以抑制驱动器中的下冲和振铃。当负载端子的电压稳定时，MOS晶体管截止，从而消除电路的阻尼电阻。

30. 发明授权

US5751171A Predriver for fast current switching through a two-terminal inductive load 失效
标题翻译：预驱动器通过两端感性负载进行快速电流切换
公开(公告)号：US5751171A
公开(公告)日：1998-05-12
申请号：US725729
申请日：1996-10-04
申请人： Tuan V. Ngo
发明人： Tuan V. Ngo
IPC分类号： G11B5/09 , G11B15/12 , G11B19/04 , H03K17/66 , H03K3/00
CPC分类号： G11B5/09 , G11B5/022 , H03K17/662 , G11B15/12 , G11B19/04
摘要： A write driver drives a current through a two-terminal inductive load. A switching circuit drives current through the inductive load, and connects to the inductive load and to at least one control node. A driver circuit charges and discharges the control node in response to an input signal. The driver circuit has at least one charging path to charge the control node and at least two active discharging paths to discharge the control node.
摘要翻译：写入驱动器通过两端感性负载驱动电流。开关电路驱动电流通过感性负载，并连接到感性负载和至少一个控制节点。驱动器电路响应于输入信号对控制节点进行充电和放电。驱动器电路具有至少一个充电路径以对控制节点和至少两个有效放电路径充电以对控制节点进行放电。

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