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21. 发明授权

US07013254B2 Low-complexity, high accuracy model of a CPU power distribution system 有权
公开(公告)号：US07013254B2
公开(公告)日：2006-03-14
申请号：US09819773
申请日：2001-03-28
申请人： Claude R. Gauthier , Brian W. Amick
发明人： Claude R. Gauthier , Brian W. Amick
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F2217/78 , Y02E60/76 , Y04S40/22 , Y10T307/707
摘要： A low-complexity, high accuracy model of a CPU power distribution system has been developed. The model includes models of multiple power converters that input to a board model. The board model then inputs to a package model. Finally, the package model inputs to a chip model. The model provides a high degree of accuracy with an acceptable simulation time.

22. 发明授权

US06975977B2 Low-complexity, high accuracy model of a CPU anti-resonance system 有权
标题翻译： CPU反共振系统的低复杂度，高精度模型
公开(公告)号：US06975977B2
公开(公告)日：2005-12-13
申请号：US09819198
申请日：2001-03-28
申请人： Claude R. Gauthier , Brian W. Amick
发明人： Claude R. Gauthier , Brian W. Amick
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： A low-complexity, high accuracy model of a CPU anti-resonance system has been developed. The model includes a simulated load model, a simulated transistor that simulates the performance of a high frequency capacitor, and a simulated capacitor that simulates the performance of an intrinsic capacitance of a section of the microprocessor. All of the elements of the model are connected in parallel.
摘要翻译：已经开发了一种低复杂度，高精度的CPU反共振系统模型。该模型包括模拟负载模型，模拟高频电容器性能的模拟晶体管，以及模拟微处理器部分本征电容性能的模拟电容器。模型的所有元素并行连接。

23. 发明授权

US06873503B2 SSTL pull-up pre-driver design using regulated power supply 有权
标题翻译： SSTL上拉预驱动器设计采用稳压电源
公开(公告)号：US06873503B2
公开(公告)日：2005-03-29
申请号：US10247082
申请日：2002-09-19
申请人： Brian W. Amick , Lynn Warriner , Claude R. Gauthier , Tri Tran
发明人： Brian W. Amick , Lynn Warriner , Claude R. Gauthier , Tri Tran
IPC分类号： H03K19/003 , H03K19/0185 , H02H3/20
CPC分类号： H03K19/018521 , H03K19/00315
摘要： A SSTL memory interface pre-driver stage that uses a voltage regulator to generate a ‘virtual’ ground reference voltage is provided. The ‘virtual’ ground voltage reference, being greater than a zero volt ground voltage, allows low voltage transistors to be used, thereby improving interface performance and decreasing system power consumption. The pre-driver stage uses a biasing circuit to bias the voltage regulator, formed by a transistor arranged in a source follower configuration, to generate the ‘virtual’ ground reference voltage off which a voltage translator stage of the pre-driver stage operates to generate an output of the pre-driver stage.
摘要翻译：提供了使用电压调节器产生“虚拟”接地参考电压的SSTL存储器接口预驱动器级。大于零伏接地电压的“虚拟”接地电压基准允许使用低压晶体管，从而提高接口性能并降低系统功耗。预驱动器级使用偏置电路来偏置由以源极跟随器配置布置的晶体管形成的稳压器，以产生“虚拟”接地参考电压，预驱动器级的电压转换器级工作以产生预驱动阶段的输出。

24. 发明授权

US06814485B2 On-die thermal monitoring technique 有权
标题翻译：模内热监测技术
公开(公告)号：US06814485B2
公开(公告)日：2004-11-09
申请号：US10349645
申请日：2003-01-23
申请人： Claude R. Gauthier , Gin S. Yee
发明人： Claude R. Gauthier , Gin S. Yee
IPC分类号： G01K700
CPC分类号： G01K7/01
摘要： A method and apparatus for monitoring a temperature on an integrated circuit that includes a thin gate oxide transistor. A temperature monitoring system that includes a thick gate oxide transistor is provided. The temperature monitoring system includes a temperature independent voltage generator, a temperature dependent voltage generator that includes a thick gate oxide transistor, and a quantifier operatively connected to the temperature independent voltage generator and temperature dependent voltage generator.
摘要翻译：一种用于监测包括薄栅极氧化物晶体管的集成电路的温度的方法和装置。提供了包括厚栅极氧化物晶体管的温度监测系统。温度监测系统包括一个独立于温度的电压发生器，一个温度相关的电压发生器，它包括一个厚栅极氧化物晶体管，和一个与温度无关的电压发生器和与温度相关的电压发生器可操作地连接的量子

25. 发明授权

US06774665B2 Cascode SSTL output buffer using source followers 有权
标题翻译： Cascode SSTL输出缓冲区使用源跟随器
公开(公告)号：US06774665B2
公开(公告)日：2004-08-10
申请号：US10255341
申请日：2002-09-26
申请人： Brian W. Amick , Lynn A. Warriner , Claude R. Gauthier , Tri K. Tran
发明人： Brian W. Amick , Lynn A. Warriner , Claude R. Gauthier , Tri K. Tran
IPC分类号： H03K1716
CPC分类号： H03K19/00384 , H03K19/018507
摘要： A cascode SSTL output buffer using a source follower circuit includes a biasing circuit arranged to generate a first bias signal. The source follower circuit is responsive to the first bias signal and generates a second bias signal which is then used by a cascode circuit that receives an input signal to the SSTL output buffer to drive an output signal from the SSTL output buffer.
摘要翻译：使用源极跟随器电路的共源共栅SSTL输出缓冲器包括被配置为产生第一偏置信号的偏置电路。源极跟随器电路响应于第一偏置信号并产生第二偏置信号，然后由共源共栅电路使用该信号，其接收到SSTL输出缓冲器的输入信号以驱动来自SSTL输出缓冲器的输出信号。

26. 发明授权

US06628135B2 Analog-based on-chip voltage sensor 有权
标题翻译：基于模拟的片上电压传感器
公开(公告)号：US06628135B2
公开(公告)日：2003-09-30
申请号：US09954883
申请日：2001-09-18
申请人： Claude R. Gauthier , Brian W. Amick , Spencer Gold
发明人： Claude R. Gauthier , Brian W. Amick , Spencer Gold
IPC分类号： G01R3102
CPC分类号： G01R31/275
摘要： An on-chip voltage sensor that selectively eliminates noise from a voltage measurement is provided. The on-chip voltage sensor has resistive and capacitive components in the voltage divider, thus allowing a voltage on a section of a computer chip to be measured exclusive of high-frequency noise. Further, a method for measuring a voltage on a section of a computer chip using a voltage divider having a resistor and a capacitor is provided. Further, a computer chip having an on-chip voltage sensor is provided. Further, a method and apparatus for observing voltages at multiple locations on an integrated circuit.
摘要翻译：提供了选择性地消除电压测量中的噪声的片上电压传感器。片上电压传感器在分压器中具有电阻和电容分量，从而允许测量计算机芯片的一部分上的电压，而不考虑高频噪声。此外，提供了一种使用具有电阻器和电容器的分压器来测量计算机芯片的一部分上的电压的方法。此外，提供具有片上电压传感器的计算机芯片。此外，还提供了用于在集成电路上的多个位置观察电压的方法和装置。

27. 发明授权

US06573770B1 Programmable leakage current offset for delay locked loop 有权
标题翻译：用于延迟锁定环路的可编程漏电流补偿
公开(公告)号：US06573770B1
公开(公告)日：2003-06-03
申请号：US10230726
申请日：2002-08-29
申请人： Claude R. Gauthier , Pradeep R. Trivedi , Brian W. Amick , Dean Liu
发明人： Claude R. Gauthier , Pradeep R. Trivedi , Brian W. Amick , Dean Liu
IPC分类号： H03L706
CPC分类号： H03L7/0812 , H03L7/0891
摘要： A method and apparatus for post-fabrication adjustment of a delay locked loop leakage current is provided. The adjustment system includes an adjustment circuit that adjusts a leakage current offset circuit to compensate for the leakage current of a capacitor in the delay locked loop. The capacitor connects to a control voltage of the delay locked loop. Such control of the leakage current in the delay locked loop allows a designer to achieve a desired delay locked loop operating characteristic after the delay locked loop has been fabricated.
摘要翻译：提供了延迟锁定环路漏电流的制造后调整方法和装置。调整系统包括调整电路，调整漏电流补偿电路以补偿延迟锁定环中的电容器的漏电流。电容器连接到延迟锁定环路的控制电压。在延迟锁定环路中的这种对漏电流的控制允许设计者在制造延迟锁定环路之后实现期望的延迟锁定环路工作特性。

28. 发明授权

US06570421B1 Programmable leakage current offset for phase locked loop 有权
标题翻译：用于锁相环的可编程泄漏电流偏移
公开(公告)号：US06570421B1
公开(公告)日：2003-05-27
申请号：US10230862
申请日：2002-08-29
申请人： Claude R. Gauthier , Pradeep R. Trivedi , Brian W. Amick
发明人： Claude R. Gauthier , Pradeep R. Trivedi , Brian W. Amick
IPC分类号： H03L706
CPC分类号： H03L7/0893 , H03L7/18
摘要： A method and apparatus for post-fabrication adjustment of a phase locked loop leakage current is provided. The adjustment system includes an adjustment circuit that adjusts a leakage current offset circuit to compensate for the leakage current of a capacitor in the phase locked loop. The capacitor connects to a control voltage of the phase locked loop. Such control of the leakage current in the phase locked loop allows a designer to achieve a desired phase locked loop operating characteristic after the phase locked loop has been fabricated.
摘要翻译：提供了一种用于制造后调整锁相环漏电流的方法和装置。调整系统包括调整电路，调整漏电流补偿电路以补偿锁相环中的电容器的漏电流。电容器连接到锁相环的控制电压。在锁相环中的泄漏电流的这种控制允许设计者在制造了锁相环之后实现期望的锁相环工作特性。

29. 发明授权

US06549030B2 Clock induced supply noise reduction method for a latch based circuit 有权
标题翻译：用于基于锁存器的电路的时钟感应电源降噪方法
公开(公告)号：US06549030B2
公开(公告)日：2003-04-15
申请号：US09918744
申请日：2001-07-31
申请人： Brian W. Amick , Claude R. Gauthier
发明人： Brian W. Amick , Claude R. Gauthier
IPC分类号： H03K1716
CPC分类号： H03K3/013 , H03K3/037 , H03K3/0375
摘要： A method for reducing the noise associated with a clock signal for a latch based circuit has been developed. The method includes storing a charge at a pre-determined time of the clock cycle and releasing the stored charge also at a pre-determined time of the clock cycle. The charge is released onto the power grid of the system served by the clock signal in synchronization with the operation of the latch.
摘要翻译：已经开发了用于减少与基于锁存器的电路的时钟信号相关联的噪声的方法。该方法包括将电荷存储在时钟周期的预定时间，并在时钟周期的预定时间内释放存储的电荷。与锁存器的操作同步，电荷被释放到由时钟信号服务的系统的电网上。

30. 发明授权

US06483341B2 CMOS-microprocessor chip and package anti-resonance apparatus 有权
标题翻译： CMOS微处理器芯片和封装反谐振装置
公开(公告)号：US06483341B2
公开(公告)日：2002-11-19
申请号：US09754564
申请日：2001-01-04
申请人： Claude R. Gauthier , Tyler J. Thorp , Richard L. Wheeler , Brian Amick
发明人： Claude R. Gauthier , Tyler J. Thorp , Richard L. Wheeler , Brian Amick
IPC分类号： H03K1716
CPC分类号： H02M3/00 , H02M1/44 , H02M3/07
摘要： An apparatus for regulating resonance in a micro-chip has been developed. The method includes connecting a de-coupled capacitance across the supply and ground voltages, and connecting a band-pass shunt regulator that is in parallel to the capacitor across the supply and ground voltages. The regulator will short circuit the supply and ground voltages at a pre-determined frequency to reduce the resonance effect on the micro-chip.
摘要翻译：已经开发了用于调节微芯片中的共振的装置。该方法包括在电源和接地电压之间连接去耦合电容，以及在电源和接地电压之间连接与电容器并联的带通分流调节器。调节器将以预定频率将电源和接地电压短路，以减少对微芯片的共振效应。

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