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21. 发明申请

US20120218885A1 SELECTION OF RECEIVE-QUEUE BASED ON PACKET ATTRIBUTES 失效
标题翻译：基于分组属性选择接收队列
公开(公告)号：US20120218885A1
公开(公告)日：2012-08-30
申请号：US13466914
申请日：2012-05-08
申请人： Francois Abel , Claude Basso , Jean L. Calvignac , Natarajan Vaidhyanathan , Fabrice Verplanken , Colin B. Verrilli
发明人： Francois Abel , Claude Basso , Jean L. Calvignac , Natarajan Vaidhyanathan , Fabrice Verplanken , Colin B. Verrilli
IPC分类号： H04L12/24
CPC分类号： H04L47/6215
摘要： According to embodiments of the invention, there is provided a method for operating a network processor. The network processor receiving a first data packet in a stream of data packets and a set of receive-queues adapted to store receive data packets. The network processor processing the first data packet by reading a flow identification in the first data packet; determining a quality of service for the first data packet; mapping the flow identification and the quality of service into an index for selecting a first receive-queue for routing the first data packet; and utilizing the index to route the first data packet to the first receive-queue.
摘要翻译：根据本发明的实施例，提供了一种用于操作网络处理器的方法。网络处理器接收数据包流中的第一数据包和适于存储接收数据包的一组接收队列。网络处理器通过读取第一数据分组中的流标识来处理第一数据分组; 确定第一数据分组的服务质量; 将流标识和服务质量映射到用于选择用于路由第一数据分组的第一接收队列的索引; 以及利用所述索引将所述第一数据分组路由到所述第一接收队列。

22. 发明申请

US20120155267A1 SELECTION OF RECEIVE-QUEUE BASED ON PACKET ATTRIBUTES 审中-公开
标题翻译：基于分组属性选择接收队列
公开(公告)号：US20120155267A1
公开(公告)日：2012-06-21
申请号：US13302285
申请日：2011-11-22
申请人： Francois Abel , Claude Basso , Jean L. Calvignac , Natarajan Vaidhyanathan , Fabrice Verplanken , Colin B. Verrilli
发明人： Francois Abel , Claude Basso , Jean L. Calvignac , Natarajan Vaidhyanathan , Fabrice Verplanken , Colin B. Verrilli
IPC分类号： H04L12/26
CPC分类号： H04L47/6215
摘要： According to embodiments of the invention, there is provided a method, a system, and a computer program product for operating a network processor. The network processor processing a received data packet by reading a flow identification in the data packet; determining a quality of service criteria (QoSC) for the data packet; mapping the flow identification and the QoSC into an index for selecting a receive-queue for routing the data packet; and utilizing the index to route the data packet to the receive-queue.
摘要翻译：根据本发明的实施例，提供了一种用于操作网络处理器的方法，系统和计算机程序产品。网络处理器通过读取数据分组中的流标识来处理接收到的数据分组; 确定数据包的服务质量标准（QoSC）; 将流标识和QoSC映射到用于选择用于路由数据分组的接收队列的索引; 并利用索引将数据包路由到接收队列。

23. 发明授权

US08675660B2 Selection of receive-queue based on packet attributes 失效
标题翻译：基于分组属性选择接收队列
公开(公告)号：US08675660B2
公开(公告)日：2014-03-18
申请号：US13466914
申请日：2012-05-08
申请人： Francois Abel , Claude Basso , Jean L. Calvignac , Natarajan Vaidhyanathan , Fabrice Jean Verplanken , Colin B. Verrilli
发明人： Francois Abel , Claude Basso , Jean L. Calvignac , Natarajan Vaidhyanathan , Fabrice Jean Verplanken , Colin B. Verrilli
IPC分类号： H04L12/28 , H04L12/54 , G06F15/173
CPC分类号： H04L47/6215
摘要： According to embodiments of the invention, there is provided a method for operating a network processor. The network processor receiving a first data packet in a stream of data packets and a set of receive-queues adapted to store receive data packets. The network processor processing the first data packet by reading a flow identification in the first data packet; determining a quality of service for the first data packet; mapping the flow identification and the quality of service into an index for selecting a first receive-queue for routing the first data packet; and utilizing the index to route the first data packet to the first receive-queue.
摘要翻译：根据本发明的实施例，提供了一种用于操作网络处理器的方法。网络处理器接收数据包流中的第一数据包和适于存储接收数据包的一组接收队列。网络处理器通过读取第一数据分组中的流标识来处理第一数据分组; 确定第一数据分组的服务质量; 将流标识和服务质量映射到用于选择用于路由第一数据分组的第一接收队列的索引; 以及利用所述索引将所述第一数据分组路由到所述第一接收队列。

24. 发明授权

US08942095B2 Identification of QoS classification based on packet attributes 有权
标题翻译：基于分组属性的QoS分类识别
公开(公告)号：US08942095B2
公开(公告)日：2015-01-27
申请号：US13302489
申请日：2011-11-22
申请人： Francois Abel , Claude Basso , Jean L. Calvignac , Natarajan Vaidhyanathan , Fabrice Jean Verplanken , Colin B. Verrilli
发明人： Francois Abel , Claude Basso , Jean L. Calvignac , Natarajan Vaidhyanathan , Fabrice Jean Verplanken , Colin B. Verrilli
IPC分类号： H04L12/54 , H04L12/851 , H04L29/06
CPC分类号： H04L47/2441 , H04L69/22
摘要： A method, a system, and a computer program product is disclosed for identifying a quality of service (QoS) classification of a packet in a network by a network processor. The method comprising: providing a table wherein a priority value with a maximum of N values is used as an index into the table to retrieve a QoS classification having a maximum of M values with M less than N; receiving a data packet in a stream of data packets; extracting at least two priority indicator values from the packet; converting the at least two priority indicator values into a priority value; utilizing the priority value as an index into the table; extracting the entry in the table corresponding to the priority value as the QoS classification of the packet; and utilizing the QoS classification for subsequent processing of the data packet.
摘要翻译：公开了一种方法，系统和计算机程序产品，用于通过网络处理器来识别网络中的分组的服务质量（QoS）分类。该方法包括：提供一个表，其中将具有最大N个值的优先级值用作表中的索引以检索具有M小于N的最大M个值的QoS分类; 在数据包流中接收数据包; 从分组中提取至少两个优先级指示符值; 将所述至少两个优先级指示符值转换为优先级值; 利用优先级值作为表中的索引; 提取对应于优先级值的表中的条目作为分组的QoS分类; 并利用QoS分类来对数据分组进行后续处理。

25. 发明申请

US20120300630A1 IDENTIFICATION OF QOS CLASSIFICATION BASED ON PACKET ATTRIBUTES 有权
标题翻译：基于分组属性的QOS分类识别
公开(公告)号：US20120300630A1
公开(公告)日：2012-11-29
申请号：US13302489
申请日：2011-11-22
申请人： Francois Abel , Claude Basso , Jean L. Calvignac , Natarajan Vaidhyanathan , Fabrice Verplanken , Colin B. Verrilli
发明人： Francois Abel , Claude Basso , Jean L. Calvignac , Natarajan Vaidhyanathan , Fabrice Verplanken , Colin B. Verrilli
IPC分类号： H04L12/24
CPC分类号： H04L47/2441 , H04L69/22
摘要： A method, a system, and a computer program product is disclosed for identifying a quality of service (QoS) classification of a packet in a network by a network processor. The method comprising: providing a table wherein a priority value with a maximum of N values is used as an index into the table to retrieve a QoS classification having a maximum of M values with M less than N; receiving a data packet in a stream of data packets; extracting at least two priority indicator values from the packet; converting the at least two priority indicator values into a priority value; utilizing the priority value as an index into the table; extracting the entry in the table corresponding to the priority value as the QoS classification of the packet; and utilizing the QoS classification for subsequent processing of the data packet.
摘要翻译：公开了一种方法，系统和计算机程序产品，用于通过网络处理器来识别网络中的分组的服务质量（QoS）分类。该方法包括：提供一个表，其中将具有最大N个值的优先级值用作表中的索引以检索具有M小于N的最大M个值的QoS分类; 在数据包流中接收数据包; 从分组中提取至少两个优先级指示符值; 将所述至少两个优先级指示符值转换为优先级值; 利用优先级值作为表中的索引; 提取对应于优先级值的表中的条目作为分组的QoS分类; 并利用QoS分类来对数据分组进行后续处理。

26. 发明授权

US07929438B2 Scheduler pipeline design for hierarchical link sharing 失效
标题翻译：调度器管道设计用于分层链路共享
公开(公告)号：US07929438B2
公开(公告)日：2011-04-19
申请号：US12175479
申请日：2008-07-18
申请人： Claude Basso , Jean L. Calvignac , Chih-jen Chang , Gordon T. Davis , Fabrice J. Verplanken
发明人： Claude Basso , Jean L. Calvignac , Chih-jen Chang , Gordon T. Davis , Fabrice J. Verplanken
IPC分类号： H04J1/16
CPC分类号： H04L47/60 , H04L47/15 , H04L47/50 , H04L47/52 , H04L49/90
摘要： A pipeline configuration is described for use in network traffic management for the hardware scheduling of events arranged in a hierarchical linkage. The configuration reduces costs by minimizing the use of external SRAM memory devices. This results in some external memory devices being shared by different types of control blocks, such as flow queue control blocks, frame control blocks and hierarchy control blocks. Both SRAM and DRAM memory devices are used, depending on the content of the control block (Read-Modify-Write or ‘read’ only) at enqueue and dequeue, or Read-Modify-Write solely at dequeue. The scheduler utilizes time-based calendars and weighted fair queueing calendars in the egress calendar design. Control blocks that are accessed infrequently are stored in DRAM memory while those accessed frequently are stored in SRAM.
摘要翻译：描述了用于网络流量管理中的流水线配置，用于以分层链接排列的事件的硬件调度。该配置通过最小化外部SRAM存储器件的使用来降低成本。这导致一些外部存储器设备被不同类型的控制块共享，例如流队列控制块，帧控制块和层次控制块。使用SRAM和DRAM存储器件，这取决于控制块的内容（仅读取 - 修改 - 写入或仅读取）在排队和出队，或仅读出 - 修改 - 写出。调度器在出口日历设计中使用基于时间的日历和加权公平排队日历。不频繁访问的控制块存储在DRAM存储器中，而频繁访问的控制块存储在SRAM中。

27. 发明授权

US07457241B2 Structure for scheduler pipeline design for hierarchical link sharing 失效
标题翻译：用于分层链路共享的调度器流水线设计的结构
公开(公告)号：US07457241B2
公开(公告)日：2008-11-25
申请号：US10772737
申请日：2004-02-05
申请人： Claude Basso , Jean L. Calvignac , Chih-jen Chang , Gordon T. Davis , Fabrice J. Verplanken
发明人： Claude Basso , Jean L. Calvignac , Chih-jen Chang , Gordon T. Davis , Fabrice J. Verplanken
IPC分类号： H04J1/16
CPC分类号： H04L47/60 , H04L47/15 , H04L47/50 , H04L47/52 , H04L49/90
摘要： A pipeline configuration is described for use in network traffic management for the hardware scheduling of events arranged in a hierarchical linkage. The configuration reduces costs by minimizing the use of external SRAM memory devices. This results in some external memory devices being shared by different types of control blocks, such as flow queue control blocks, frame control blocks and hierarchy control blocks. Both SRAM and DRAM memory devices are used, depending on the content of the control block (Read-Modify-Write or ‘read’ only) at enqueue and dequeue, or Read-Modify-Write solely at dequeue. The scheduler utilizes time-based calendars and weighted fair queueing calendars in the egress calendar design. Control blocks that are accessed infrequently are stored in DRAM memory while those accessed frequently are stored in SRAM.
摘要翻译：描述了用于网络流量管理中的流水线配置，用于以分层链接排列的事件的硬件调度。该配置通过最小化外部SRAM存储器件的使用来降低成本。这导致一些外部存储器设备被不同类型的控制块共享，例如流队列控制块，帧控制块和层次控制块。使用SRAM和DRAM存储器件，这取决于控制块的内容（仅读取 - 修改 - 写入或仅读取）在排队和出队，或仅读出 - 修改 - 写出。调度器在出口日历设计中使用基于时间的日历和加权公平排队日历。不频繁访问的控制块存储在DRAM存储器中，而频繁访问的控制块存储在SRAM中。

28. 发明授权

US07406080B2 Method and structure for enqueuing data packets for processing 失效
标题翻译：排队处理数据包的方法和结构
公开(公告)号：US07406080B2
公开(公告)日：2008-07-29
申请号：US10868725
申请日：2004-06-15
申请人： Claude Basso , Jean L. Calvignac , Chih-jen Chang , Gordon T. Davis , Fabrice J. Verplanken
发明人： Claude Basso , Jean L. Calvignac , Chih-jen Chang , Gordon T. Davis , Fabrice J. Verplanken
IPC分类号： H04L12/56
CPC分类号： H04L49/90 , H04L49/9042 , H04L49/9073 , H04L69/22
摘要： A method and structure is provided for buffering data packets having a header and a remainder in a network processor system. The network processor system has a processor on a chip and at least one buffer on the chip. Each buffer on the chip is configured to buffer the header of the packets in a preselected order before execution in the processor, and the remainder of the packet is stored in an external buffer apart from the chip. The method comprises utilizing the header information to identify the location and extent of the remainder of the packet. The entire selected packet is stored in the external buffer when the buffer of the stored header of the given packet is full, and moving only the header of a selected packet stored in the external buffer to the buffer on the chip when the buffer on the chip has space therefor.
摘要翻译：提供了一种在网络处理器系统中缓冲具有报头和余数的数据分组的方法和结构。网络处理器系统在芯片上具有处理器和芯片上的至少一个缓冲器。芯片上的每个缓冲器被配置为在处理器中执行之前以预先选择的顺序缓冲数据包的报头，并且数据包的剩余部分存储在与芯片分离的外部缓冲器中。该方法包括利用报头信息来识别分组的其余部分的位置和范围。当给定分组的存储报头的缓冲器已满时，整个所选分组被存储在外部缓冲器中，并且当芯片上的缓冲器仅将存储在外部缓冲器中的选定分组的报头移动到芯片上的缓冲器时有空间。

29. 发明授权

US07522621B2 Apparatus and method for efficiently modifying network data frames 失效
标题翻译：用于有效修改网络数据帧的装置和方法
公开(公告)号：US07522621B2
公开(公告)日：2009-04-21
申请号：US11030344
申请日：2005-01-06
申请人： Claude Basso , Jean L. Calvignac , Chih-jen Chang , Fabrice J. Verplanken
发明人： Claude Basso , Jean L. Calvignac , Chih-jen Chang , Fabrice J. Verplanken
IPC分类号： H04L12/56
CPC分类号： H04L49/901 , H04L49/90 , H04L49/9021
摘要： Apparatus and method for storing network frame data which is to be modified. A plurality of buffers stores the network data which is arranged in a data structure identified by a frame control block and buffer control block. A plurality of buffer control blocks associated with each buffer storing the frame data establishes a sequence of the buffers. Each buffer control block has data for identifying a subsequent buffer within the sequence. The first buffer is identified by a field of a frame control block as well as the beginning and ending address of the frame data. The frame data can be modified without rewriting the data to memory by altering the buffer control block and/or frame control block contents without having to copy or rewrite the data in order to modify it.
摘要翻译：用于存储要修改的网络帧数据的装置和方法。多个缓冲器存储布置在由帧控制块和缓冲器控制块所标识的数据结构中的网络数据。与存储帧数据的每个缓冲器相关联的多个缓冲器控制块建立缓冲器的序列。每个缓冲器控制块具有用于识别序列内的后续缓冲器的数据。第一缓冲器由帧控制块的字段以及帧数据的开始和结束地址来标识。可以通过改变缓冲器控制块和/或帧控制块内容而不将数据重写到存储器来修改帧数据，而不必复制或重写数据以便修改它。

30. 发明申请

US20080298372A1 STRUCTURE AND METHOD FOR SCHEDULER PIPELINE DESIGN FOR HIERARCHICAL LINK SHARING 失效
标题翻译：用于分层链路共享的调度器管道设计的结构和方法
公开(公告)号：US20080298372A1
公开(公告)日：2008-12-04
申请号：US12175479
申请日：2008-07-18
申请人： Claude Basso , Jean L. Calvignac , Chih-jen Chang , Gordon T. Davis , Fabrice J. Verplanken
发明人： Claude Basso , Jean L. Calvignac , Chih-jen Chang , Gordon T. Davis , Fabrice J. Verplanken
IPC分类号： H04L12/56
CPC分类号： H04L47/60 , H04L47/15 , H04L47/50 , H04L47/52 , H04L49/90
摘要： A pipeline configuration is described for use in network traffic management for the hardware scheduling of events arranged in a hierarchical linkage. The configuration reduces costs by minimizing the use of external SRAM memory devices. This results in some external memory devices being shared by different types of control blocks, such as flow queue control blocks, frame control blocks and hierarchy control blocks. Both SRAM and DRAM memory devices are used, depending on the content of the control block (Read-Modify-Write or ‘read’ only) at enqueue and dequeue, or Read-Modify-Write solely at dequeue. The scheduler utilizes time-based calendars and weighted fair queueing calendars in the egress calendar design. Control blocks that are accessed infrequently are stored in DRAM memory while those accessed frequently are stored in SRAM.
摘要翻译：描述了用于网络流量管理中的流水线配置，用于以分层链接排列的事件的硬件调度。该配置通过最小化外部SRAM存储器件的使用来降低成本。这导致一些外部存储器设备被不同类型的控制块共享，例如流队列控制块，帧控制块和层次控制块。使用SRAM和DRAM存储器件，这取决于控制块的内容（仅读取 - 修改 - 写入或仅读取）在排队和出队，或仅读出 - 修改 - 写出。调度器在出口日历设计中使用基于时间的日历和加权公平排队日历。不频繁访问的控制块存储在DRAM存储器中，而频繁访问的控制块存储在SRAM中。

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