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21. 发明授权

US08587991B2 Recycling charges 有权
标题翻译：回收费用
公开(公告)号：US08587991B2
公开(公告)日：2013-11-19
申请号：US13429082
申请日：2012-03-23
申请人： Young Seog Kim , Kuoyuan (Peter) Hsu , Derek C. Tao , Young Suk Kim
发明人： Young Seog Kim , Kuoyuan (Peter) Hsu , Derek C. Tao , Young Suk Kim
IPC分类号： G11C11/00 , G11C7/00 , G11C5/14
CPC分类号： G11C11/412
摘要： A circuit includes a first node; a second node; a first PMOS transistor having a source coupled to the first node, a drain coupled to a first control transistor, and a gate driven by a first voltage; and a first NMOS transistor having a source coupled to the second node, a drain coupled to the first control transistor, and a gate driven by a second voltage. The first PMOS transistor is configured to automatically turn off based on the first voltage and a first node voltage at the first node. The first NMOS transistor is configured to automatically turn off based on the second voltage and a second node voltage at the second node. When the first PMOS transistor, the control transistor, and the first NMOS transistor are on, the first node voltage is lowered while the second voltage is raised.
摘要翻译：电路包括第一节点; 第二个节点; 具有耦合到第一节点的源极的第一PMOS晶体管，耦合到第一控制晶体管的漏极和由第一电压驱动的栅极; 以及第一NMOS晶体管，其具有耦合到第二节点的源极，耦合到第一控制晶体管的漏极和由第二电压驱动的栅极。第一PMOS晶体管被配置为基于第一节点处的第一电压和第一节点电压自动关闭。第一NMOS晶体管被配置为基于第二节点处的第二电压和第二节点电压自动关闭。当第一PMOS晶体管，控制晶体管和第一NMOS晶体管导通时，第一节点电压降低，而第二电压升高。

22. 发明授权

US08929154B2 Layout of memory cells 有权
标题翻译：存储单元布局
公开(公告)号：US08929154B2
公开(公告)日：2015-01-06
申请号：US13267235
申请日：2011-10-06
申请人： Jacklyn Chang , Derek C. Tao , Yukit Tang , Kuoyuan (Peter) Hsu
发明人： Jacklyn Chang , Derek C. Tao , Yukit Tang , Kuoyuan (Peter) Hsu
IPC分类号： G11C7/10 , G11C7/18 , H01L27/02 , G11C11/412 , G11C11/413 , H01L27/11
CPC分类号： G11C7/18 , G11C11/412 , G11C11/413 , H01L27/0207 , H01L27/1104
摘要： A semiconductor structure includes a first strap cell, a first read port, and a first VSS terminal. The first strap cell has a first strap cell VSS region. The first read port has a first read port VSS region, a first read port read bit line region, and a first read port poly region. The first VSS terminal is configured to electrically couple the first strap cell VSS region and the first read port VSS region.
摘要翻译：半导体结构包括第一带状电池，第一读取端口和第一VSS端子。第一带状电池具有第一带电池VSS区域。第一读取端口具有第一读取端口VSS区域，第一读取端口读取位线区域和第一读取端口聚合区域。第一VSS端子被配置为电耦合第一带电池VSS区域和第一读取端口VSS区域。

23. 发明授权

US08704376B2 Layout of memory strap cell 有权
标题翻译：记忆带细胞布局
公开(公告)号：US08704376B2
公开(公告)日：2014-04-22
申请号：US13443467
申请日：2012-04-10
申请人： Jacklyn Chang , Evan Yong Zhang , Derek C. Tao , Kuoyuan (Peter) Hsu
发明人： Jacklyn Chang , Evan Yong Zhang , Derek C. Tao , Kuoyuan (Peter) Hsu
IPC分类号： H01L23/498
CPC分类号： H01L27/1104 , H01L27/0207
摘要： A layout structure includes a substrate, a well, a first dopant area, a second dopant area, a first poly region, a third dopant area, a fourth dopant area, and a second poly region. The well is in the substrate. The first poly region is in between the first dopant area and the second dopant area. The second poly region is in between the third dopant area and the fourth dopant area. The first dopant area, the second dopant area, the third dopant area, and the fourth dopant area are in the well. The first dopant area is configured to serve as a source of a transistor and to receive a first voltage value from a first power supply source. The well is configured to serve as a bulk of the transistor and to receive a second voltage value from a second power supply source.
摘要翻译：布局结构包括衬底，阱，第一掺杂区，第二掺杂区，第一多晶区，第三掺杂区，第四掺杂区和第二多晶区。井在底层。第一多晶硅区位于第一掺杂区和第二掺杂区之间。第二聚合区位于第三掺杂区和第四掺杂区之间。第一掺杂剂区域，第二掺杂剂区域，第三掺杂剂区域和第四掺杂剂区域在井中。第一掺杂剂区域被配置为用作晶体管的源极并且从第一电源接收第一电压值。阱被配置为用作晶体管的体积并从第二电源接收第二电压值。

24. 发明授权

US08643422B1 Slicer and method of operating the same 有权
标题翻译：切片机及其操作方法
公开(公告)号：US08643422B1
公开(公告)日：2014-02-04
申请号：US13547396
申请日：2012-07-12
申请人： Ming-Chieh Huang , Chan-Hong Chern , Tao Wen Chung , Chih-Chang Lin , Tsung-Ching Huang , Derek C. Tao
发明人： Ming-Chieh Huang , Chan-Hong Chern , Tao Wen Chung , Chih-Chang Lin , Tsung-Ching Huang , Derek C. Tao
IPC分类号： H03K3/356
CPC分类号： H03K5/08 , H03K3/356139 , H04L27/01
摘要： This description relates to a slicer including a first latch. The first latch includes an evaluating transistor configured to receive a first clock signal and a developing transistor configured to receive a second clock signal. The first clock signal is different from the second clock signal. The first latch includes first and second input transistors configured to receive first and second complementary inputs. The first latch includes at least one pre-charging transistor configured to receive a third clock signal. The first latch further at least one cross-latched pair of transistors, the at least one cross-latched transistor pair connected between the evaluating transistor and the first and second output nodes. The slicer includes a second latch connected to the first and second output nodes and to a third output node. The slicer includes a buffer connected to the third output node and configured to generate a final output signal.
摘要翻译：该描述涉及包括第一锁存器的限幅器。第一锁存器包括被配置为接收第一时钟信号的评估晶体管和被配置为接收第二时钟信号的显影晶体管。第一时钟信号与第二时钟信号不同。第一锁存器包括被配置为接收第一和第二互补输入的第一和第二输入晶体管。第一锁存器包括配置成接收第三时钟信号的至少一个预充电晶体管。第一锁存器还包括至少一个交叉锁存晶体管对，该至少一个交叉锁存晶体管对连接在评估晶体管与第一和第二输出节点之间。切片器包括连接到第一和第二输出节点和第三输出节点的第二锁存器。切片器包括连接到第三输出节点并被配置为产生最终输出信号的缓冲器。

25. 发明申请

US20140032871A1 TRACKING MECHANISM FOR WRITING TO A MEMORY CELL 有权
标题翻译：跟踪机制写入记忆体
公开(公告)号：US20140032871A1
公开(公告)日：2014-01-30
申请号：US13560461
申请日：2012-07-27
申请人： Kuoyuan (Peter) Hsu , Bing Wang , Derek C. Tao , Yukit Tang , Kai Fan
发明人： Kuoyuan (Peter) Hsu , Bing Wang , Derek C. Tao , Yukit Tang , Kai Fan
IPC分类号： G06F12/00 , G11C7/00
CPC分类号： G11C7/222 , G11C7/12 , G11C7/227 , G11C11/419
摘要： A circuit includes a tracking write circuit and a write circuit. Various write signals of the write circuit are generated based on tracking signals of the tracking write circuit. The write signals are used in a write operation of a memory cell.
摘要翻译：电路包括跟踪写入电路和写入电路。基于跟踪写入电路的跟踪信号产生写入电路的各种写入信号。写信号用于存储单元的写入操作。

26. 发明授权

US08406078B2 Memory circuits having a plurality of keepers 有权
标题翻译：存储电路具有多个保持器
公开(公告)号：US08406078B2
公开(公告)日：2013-03-26
申请号：US13025668
申请日：2011-02-11
申请人： Annie Lum , Derek C. Tao , Young Seog Kim
发明人： Annie Lum , Derek C. Tao , Young Seog Kim
IPC分类号： G11C8/00
CPC分类号： G11C7/12 , G11C5/147 , G11C11/412 , G11C11/413
摘要： A memory circuit includes a first plurality of memory arrays disposed in a column fashion. The memory circuit includes a first plurality of keepers each of which is electrically coupled with a corresponding one of the first plurality of memory arrays. A first current limiter is electrically coupled with and shared by the first plurality of keepers. A first plurality of sector switches each are electrically coupled between the first current limiter and a respective one of the first plurality of keepers.
摘要翻译：存储电路包括以列方式设置的第一多个存储器阵列。存储器电路包括第一多个保持器，每个保持器与第一多个存储器阵列中的对应的一个存储器阵列电耦合。第一限流器与第一多个保持器电耦合并共享。第一多个扇区开关各自在第一限流器和第一多个保持器中的相应一个之间电耦合。

27. 发明授权

US08305827B2 Dual rail memory 有权
标题翻译：双轨内存
公开(公告)号：US08305827B2
公开(公告)日：2012-11-06
申请号：US12835197
申请日：2010-07-13
申请人： Derek C. Tao , Kuoyuan (Peter) Hsu , Dong Sik Jeong , Young Suk Kim , Young Seog Kim , Yukit Tang
发明人： Derek C. Tao , Kuoyuan (Peter) Hsu , Dong Sik Jeong , Young Suk Kim , Young Seog Kim , Yukit Tang
IPC分类号： G11C5/14
CPC分类号： G11C5/14
摘要： A memory array comprises a plurality of memory cells arranged in a plurality of rows and a plurality of columns. A column of the plurality of columns includes a first power supply node configured to provide a first voltage, a second power supply node configured to provide a second voltage, and a plurality of internal supply nodes electrically coupled together and configured to receive the first voltage or the second voltage for a plurality of memory cells in the column and a plurality of internal ground nodes. The internal ground nodes are electrically coupled together and configured to provide at least two current paths for the plurality of memory cells in the column.
摘要翻译：存储器阵列包括以多行和多列布置的多个存储单元。多列的列包括被配置为提供第一电压的第一电源节点，被配置为提供第二电压的第二电源节点和电耦合在一起并被配置为接收第一电压的多个内部供电节点，该列中的多个存储单元的第二电压和多个内部接地节点。内部接地节点电耦合在一起并且被配置为为列中的多个存储器单元提供至少两个电流路径。

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