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21. 发明授权

US07626416B2 Method and apparatus for high resolution ZQ calibration 有权
标题翻译：用于高分辨率ZQ校准的方法和装置
公开(公告)号：US07626416B2
公开(公告)日：2009-12-01
申请号：US11299888
申请日：2005-12-12
申请人： Kang Yong Kim
发明人： Kang Yong Kim
IPC分类号： H03K17/16 , H03K19/003 , G11C7/10
CPC分类号： H03K19/0005 , H04L25/0278
摘要： A method is disclosed for controlling an output impedance of an electronic device of the type having an impedance control terminal to which an external load is to be connected such that a predetermined value of the voltage at the impedance control terminal controls the output impedance of the device. The method is comprised of comparing a reference voltage to a voltage at the impedance control terminal. A variable count signal representing a count value is produced in response to the comparing. The impedance of a variable impedance circuit is varied in response to the count signal, wherein the impedance of the variable impedance circuit controls the voltage at the impedance control terminal. A device connected in parallel with the variable impedance circuit is periodically operated to change (increase/decrease) the impedance of the variable impedance circuit. An apparatus for performing the method is also disclosed. Because of the rules governing abstracts, this abstract should not be used to construe the claims.
摘要翻译：公开了一种用于控制具有要连接外部负载的阻抗控制端子的类型的电子设备的输出阻抗的方法，使得阻抗控制端子处的电压的预定值控制该设备的输出阻抗。该方法包括将参考电压与阻抗控制端子处的电压进行比较。响应于比较而产生表示计数值的可变计数信号。可变阻抗电路的阻抗响应于计数信号而变化，其中可变阻抗电路的阻抗控制阻抗控制端子处的电压。周期性地操作与可变阻抗电路并联连接的装置，以改变（增加/减少）可变阻抗电路的阻抗。还公开了一种用于执行该方法的装置。

22. 发明授权

US07489568B2 Delay stage-interweaved analog DLL/PLL 有权
标题翻译：延迟级交织模拟DLL / PLL
公开(公告)号：US07489568B2
公开(公告)日：2009-02-10
申请号：US11297184
申请日：2005-12-08
申请人： Kang Yong Kim , Dong Myung Choi
发明人： Kang Yong Kim , Dong Myung Choi
IPC分类号： G11C7/00
CPC分类号： G11C7/22 , G11C7/222 , G11C29/02 , G11C29/028 , G11C29/50012 , G11C2207/2254 , H03L7/0802 , H03L7/0812 , H03L7/0814 , H03L7/0891 , H03L7/10
摘要： A methodology is disclosed that enables the delay stages of an analog delay locked loop (DLL) or phase locked loop (PLL) to be programmed according to the operating condition, which may depend on the frequency of the input reference clock. The resulting optimized delay stages allow for a broad frequency range of operation, fast locking time over a wide range of input clock frequencies, and a lower current consumption at high clock frequencies. Better performance is achieved by allowing the number of analog delay stages active during a given operation to be flexibly set. The deactivation or turning off of unused delay stages conserves power at higher frequencies. The high frequency range of operation is increased by using a flexible number of delay stages for various input clock frequencies. Because of the rules governing abstracts, this abstract should not be used to construe the claims.
摘要翻译：公开了一种使得可以根据可能取决于输入参考时钟的频率的操作条件对模拟延迟锁定环（DLL）或锁相环（PLL）的延迟级进行编程的方法。所产生的优化延迟级允许宽的频率范围的操作，在宽的输入时钟频率范围内的快速锁定时间以及在高时钟频率下的较低的电流消耗。通过允许在给定操作期间激活的模拟延迟级的数量被灵活地设置来实现更好的性能。未使用的延迟级的停用或关闭在较高频率下节省功率。通过为各种输入时钟频率使用灵活数量的延迟级来增加操作的高频范围。由于管理摘要的规则，本摘要不应用于解释索赔。

23. 发明授权

US07417478B2 Delay line circuit 有权
标题翻译：延迟线电路
公开(公告)号：US07417478B2
公开(公告)日：2008-08-26
申请号：US11349397
申请日：2006-02-06
申请人： Kang Yong Kim , Jongtae Kwak
发明人： Kang Yong Kim , Jongtae Kwak
IPC分类号： H03L7/06
CPC分类号： G11C7/22 , G11C7/222
摘要： Methods, circuits, devices, and systems are provided, including a delay line for a delay-locked loop. One method includes providing a reference clock to a first delay unit in a delay line. The delay line includes a number of delay units coupled together. Even delay units, among the delay units, are coupled to an even clock line to generate a first intermediate clock. Odd delay units are coupled to an odd clock line to generate a second intermediate clock. The even and odd delay units are configured to in a manner intended to restrict an increase in drive to load ratio and to intrinsic delay as additional delay units are coupled to the number of delay units.
摘要翻译：提供了方法，电路，设备和系统，包括用于延迟锁定环路的延迟线。一种方法包括向延迟线中的第一延迟单元提供参考时钟。延迟线包括耦合在一起的多个延迟单元。延迟单元中的偶数延迟单元耦合到偶数时钟线以产生第一中间时钟。奇数延迟单元耦合到奇数时钟线以产生第二中间时钟。偶数和奇数延迟单元被配置为以附加延迟单元耦合到延迟单元的数量来限制驱动与负载比的增加以及固有延迟。

24. 发明申请

US20080136475A1 Control of a Variable Delay Line Using Line Entry Point to Modify Line Power Supply Voltage 有权
标题翻译：使用线路入口点控制可变延迟线来修改线路电源电压
公开(公告)号：US20080136475A1
公开(公告)日：2008-06-12
申请号：US11608903
申请日：2006-12-11
申请人： Tyler Gomm , Kang Yong Kim , Jongtae Kwak
发明人： Tyler Gomm , Kang Yong Kim , Jongtae Kwak
IPC分类号： H03L7/06 , H03L7/00
CPC分类号： H03L7/0814
摘要： Disclosed herein is a VDL/DLL architecture in which the power supply to the VDL, VccVDL, is regulated at least as a function of the entry point of the input signal (ClkIn) into the VDL. Specifically, VccVDL is regulated to be higher when the delay through the VDL is relatively small (when the entry point is toward the right (or minimum delay) edge of the VDL) and is reduced when the delay is relatively high (when the entry point is toward the left (or maximum delay) edge of the VDL). This provides for graduated delays across the stages of the VDL, but without the need to design each stage separately. Other benefits include a VDL/DLL design operable over a wider range of frequencies, and a reduced number of stages, including a reduced number of buffer stages. Moreover, when the disclosed technique is used, buffer stages may be dispensed with altogether. Additionally, the disclosed VDL architecture can be used in any situation where it might be advantageous to delay a signal through a variable delay as a function of VDL entry point.
摘要翻译：本文公开了一种VDL / DLL架构，其中至少将VDL，VccVDL的电源调节为输入信号（ClkIn）入口到VDL中的函数。具体地说，当通过VDL的延迟相对较小（当入口点朝向VDL的右侧（或最小延迟）边缘）时，VccVDL被调节为较高，并且当延迟相对较高时（当入口点朝向VDL的左侧（或最大延迟）边缘）。这提供了在VDL的各个阶段的分级延迟，但是不需要分别设计每个阶段。其他优点包括可在更宽的频率范围内操作的VDL / DLL设计，以及减少的级数，包括减少数量的缓冲级。此外，当使用所公开的技术时，可以完全省去缓冲阶段。另外，所公开的VDL架构可以用于可能有利的是通过作为VDL入口点的函数的可变延迟来延迟信号的任何情况。

25. 发明申请

US20120106241A1 SPIN-TRANSFER TORQUE MEMORY SELF-REFERENCE READ METHOD 有权
标题翻译：旋转转矩记忆自参考读取方法
公开(公告)号：US20120106241A1
公开(公告)日：2012-05-03
申请号：US13349052
申请日：2012-01-12
申请人： Hai Li , Yiran Chen , Hongyue Liu , Kang Yong Kim , Dimitar V. Dimitrov , Henry F. Huang
发明人： Hai Li , Yiran Chen , Hongyue Liu , Kang Yong Kim , Dimitar V. Dimitrov , Henry F. Huang
IPC分类号： G11C11/02
CPC分类号： G11C11/1673 , G11C7/06 , G11C7/065 , G11C29/02 , G11C29/021 , G11C29/028 , G11C2029/5006 , Y10S977/933
摘要： A spin-transfer torque memory apparatus and self-reference read schemes are described. One method of self-reference reading a spin-transfer torque memory unit includes applying a first read current through a magnetic tunnel junction data cell and forming a first bit line read voltage, the magnetic tunnel junction data cell having a first resistance state and storing the first bit line read voltage in a first voltage storage device. Then applying a low resistance state polarized write current through the magnetic tunnel junction data cell, forming a low second resistance state magnetic tunnel junction data cell. A second read current is applied through the low second resistance state magnetic tunnel junction data cell to forming a second bit line read voltage. The second bit line read voltage is stored in a second voltage storage device. The method also includes comparing the first bit line read voltage with the second bit line read voltage to determine whether the first resistance state of the magnetic tunnel junction data cell was a high resistance state or low resistance state.
摘要翻译：描述了自旋转移力矩存储装置和自参考读取方案。读取自旋传递转矩存储单元的一种自参考方法包括：通过磁性隧道结数据单元施加第一读取电流并形成第一位线读取电压，所述磁性隧道结数据单元具有第一电阻状态并存储第一电压存储装置中的第一位线读取电压。然后通过磁性隧道结数据单元施加低电阻状态的极化写入电流，形成低的第二电阻状态磁隧道结数据单元。第二读取电流通过低的第二电阻状态磁隧道结数据单元施加以形成第二位线读取电压。第二位线读取电压被存储在第二电压存储装置中。该方法还包括将第一位线读取电压与第二位线读取电压进行比较，以确定磁性隧道结数据单元的第一电阻状态是高电阻状态还是低电阻状态。

26. 发明申请

US20120051493A1 CONTINOUS HIGH-FREQUENCY EVENT FILTER 有权
标题翻译：连续高频事件滤波器
公开(公告)号：US20120051493A1
公开(公告)日：2012-03-01
申请号：US13294083
申请日：2011-11-10
申请人： Tyler Gomm , Kang Yong Kim
发明人： Tyler Gomm , Kang Yong Kim
IPC分类号： H03K23/00
CPC分类号： H03L7/0814 , G06F7/62 , G11C7/22 , G11C7/222 , H03L7/0805 , H03L7/085 , H03L7/089
摘要： A circuit and method for generating an active output signal in response to detecting N events, which are represented by an event signal. A counter circuit is configured to increment and decrement through a sequence of values in response to the event signal. Detection logic coupled to the counter circuit is configured to detect at least first and second values of the sequence. The detection logic is further configured to generate the active output signal and switch to detecting the second value in response to detecting the first value and generate the active output signal and switch to detecting the first value in response to detecting the second value. The first and second values are separated by N counts.
摘要翻译：一种用于响应于由事件信号表示的N个事件来产生有效输出信号的电路和方法。计数器电路被配置为响应于事件信号递增和递减一系列值。耦合到计数器电路的检测逻辑被配置为检测序列的至少第一和第二值。检测逻辑还被配置为产生有效输出信号并且响应于检测到第一值而切换到检测第二值，并且产生有效输出信号并且响应于检测到第二值而切换到检测第一值。第一个值和第二个值用N个数值分隔。

27. 发明申请

US20110134712A1 APPARATUS AND METHOD FOR TRIMMING STATIC DELAY OF A SYNCHRONIZING CIRCUIT 有权
标题翻译：用于调整同步电路的静态延迟的装置和方法
公开(公告)号：US20110134712A1
公开(公告)日：2011-06-09
申请号：US13025012
申请日：2011-02-10
申请人： Tyler Gomm , Kang Yong Kim
发明人： Tyler Gomm , Kang Yong Kim
IPC分类号： G11C8/18
CPC分类号： G11C29/02 , G11C7/22 , G11C7/222 , G11C11/4076 , G11C29/023 , G11C29/028 , G11C29/50012 , G11C2207/2254 , H03L7/0812
摘要： A system and method for trimming an unadjusted forward delay of a delay-locked loop (DLL) and trimming a duty cycle of first and second output clock signals provided by a DLL. For trimming an unadjusted forward delay, delay is added to one of a feedback clock signal path and an input clock signal path and a feedback clock signal is provided from the feedback clock signal path and an input clock signal is provided from the input clock signal path for phase comparison. For trimming a duty cycle of first and second output clock signals, one of a first delayed input clock signal and a second delayed input clock signal is delayed. The first and second delayed input clock signals are complementary. The delayed clock signal and the other clock signal are provided as the first and second output clock signals.
摘要翻译：一种用于修整延迟锁定环（DLL）的未经调整的前向延迟并修剪由DLL提供的第一和第二输出时钟信号的占空比的系统和方法。为了调整未调整的正向延迟，将延迟添加到反馈时钟信号路径和输入时钟信号路径之一，并且从反馈时钟信号路径提供反馈时钟信号，并且从输入时钟信号路径提供输入时钟信号进行相位比较。为了调整第一和第二输出时钟信号的占空比，第一延迟输入时钟信号和第二延迟输入时钟信号之一被延迟。第一和第二延迟输入时钟信号是互补的。延迟的时钟信号和另一个时钟信号被提供为第一和第二输出时钟信号。

28. 发明授权

US07898290B2 Method and apparatus for high resolution ZQ calibration 有权
标题翻译：用于高分辨率ZQ校准的方法和装置
公开(公告)号：US07898290B2
公开(公告)日：2011-03-01
申请号：US12613632
申请日：2009-11-06
申请人： Kang Yong Kim
发明人： Kang Yong Kim
IPC分类号： H03K17/16 , H03K19/003 , G11C11/00
CPC分类号： H03K19/0005 , H04L25/0278
摘要： A method is disclosed for controlling an output impedance of an electronic device of the type having an impedance control terminal to which an external load is to be connected such that a predetermined value of the voltage at the impedance control terminal controls the output impedance of the device. The method is comprised of comparing a reference voltage to a voltage at the impedance control terminal. A variable count signal representing a count value is produced in response to the comparing. The impedance of a variable impedance circuit is varied in response to the count signal, wherein the impedance of the variable impedance circuit controls the voltage at the impedance control terminal. A device connected in parallel with the variable impedance circuit is periodically operated to change (increase/decrease) the impedance of the variable impedance circuit. An apparatus for performing the method is also disclosed.
摘要翻译：公开了一种用于控制具有要连接外部负载的阻抗控制端子的类型的电子设备的输出阻抗的方法，使得阻抗控制端子处的电压的预定值控制该设备的输出阻抗。该方法包括将参考电压与阻抗控制端子处的电压进行比较。响应于比较而产生表示计数值的可变计数信号。可变阻抗电路的阻抗响应于计数信号而变化，其中可变阻抗电路的阻抗控制阻抗控制端子处的电压。周期性地操作与可变阻抗电路并联连接的装置，以改变（增加/减少）可变阻抗电路的阻抗。还公开了一种用于执行该方法的装置。

29. 发明授权

US07835205B2 Delay stage-interweaved analog DLL/PLL 有权
标题翻译：延迟级交织模拟DLL / PLL
公开(公告)号：US07835205B2
公开(公告)日：2010-11-16
申请号：US12252618
申请日：2008-10-16
申请人： Kang Yong Kim , Dong Myung Choi
发明人： Kang Yong Kim , Dong Myung Choi
IPC分类号： G11C7/00
CPC分类号： G11C7/22 , G11C7/222 , G11C29/02 , G11C29/028 , G11C29/50012 , G11C2207/2254 , H03L7/0802 , H03L7/0812 , H03L7/0814 , H03L7/0891 , H03L7/10
摘要： A methodology is disclosed that enables the delay stages of an analog delay locked loop (DLL) or phase locked loop (PLL) to be programmed according to the operating condition, which may depend on the frequency of the input reference clock. The resulting optimized delay stages allow for a broad frequency range of operation, fast locking time over a wide range of input clock frequencies, and a lower current consumption at high clock frequencies. Better performance is achieved by allowing the number of analog delay stages active during a given operation to be flexibly set. The deactivation or turning off of unused delay stages conserves power at higher frequencies. The high frequency range of operation is increased by using a flexible number of delay stages for various input clock frequencies. Because of the rules governing abstracts, this abstract should not be used to construe the claims.
摘要翻译：公开了一种使得可以根据可能取决于输入参考时钟的频率的操作条件对模拟延迟锁定环（DLL）或锁相环（PLL）的延迟级进行编程的方法。所产生的优化延迟级允许宽的频率范围的操作，在宽的输入时钟频率范围内的快速锁定时间以及在高时钟频率下的较低的电流消耗。通过允许在给定操作期间激活的模拟延迟级的数量被灵活地设置来实现更好的性能。未使用的延迟级的停用或关闭在较高频率下节省功率。通过为各种输入时钟频率使用灵活数量的延迟级来增加操作的高频范围。由于管理摘要的规则，本摘要不应用于解释索赔。

30. 发明申请

US20100060335A1 Seamless Coarse and Fine Delay Structure for High Performance DLL 有权
标题翻译：高性能DLL的无缝粗略和精细延迟结构
公开(公告)号：US20100060335A1
公开(公告)日：2010-03-11
申请号：US12620041
申请日：2009-11-17
申请人： Jongtae Kwak , Kang Yong Kim
发明人： Jongtae Kwak , Kang Yong Kim
IPC分类号： H03L7/06 , G06F1/04 , H03H11/26
CPC分类号： H03L7/00 , G11C7/1072 , G11C7/222 , H03L7/0814
摘要： A clock synchronization system and method avoids output clock jitter at high frequencies and also achieves a smooth phase transition at the boundary of the coarse and fine delays. The system may use a single coarse delay line configured to generate two intermediate clocks from the input reference clock and having a fixed phase difference therebetween. The coarse delay line may have a hierarchical or a non-hierarchical structure. A phase mixer receives these two intermediate clocks and generates the final output clock having a phase between the phases of the intermediate clocks. The coarse shifting in the delay line at high clock frequencies does not affect the phase relationship between the intermediate clocks fed into the phase mixer. The output clock from the phase mixer is time synchronized with the input reference clock and does not exhibit any jitter or noise even at high clock frequency inputs. Because of the rules governing abstracts, this abstract should not be used to construe the claims.
摘要翻译：时钟同步系统和方法避免了高频时的输出时钟抖动，并且在粗略和精细延迟的边界处实现了平滑的相位转变。该系统可以使用单个粗延迟线，其被配置为从输入参考时钟产生两个中间时钟并且在它们之间具有固定的相位差。粗延迟线可以具有分层结构或非分层结构。相位混合器接收这两个中间时钟并产生具有在中间时钟的相位之间的相位的最终输出时钟。在高时钟频率下延迟线中的粗略移位不影响馈送到相位混频器中的中间时钟之间的相位关系。来自相位混频器的输出时钟与输入参考时钟同步，即使在高时钟频率输入时也不会出现任何抖动或噪音。由于管理摘要的规则，本摘要不应用于解释索赔。

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