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21. 发明授权

US06951818B2 Method of manufacturing an electronic device 有权
标题翻译：制造电子装置的方法
公开(公告)号：US06951818B2
公开(公告)日：2005-10-04
申请号：US10476708
申请日：2002-05-06
申请人： Michel Marcel Jose Decre , Andreas Hubertus Montree , Jacobus Bernardus Giesbers , Gerwin Hermanus Gelinck , Martin Hillebrand Blees
发明人： Michel Marcel Jose Decre , Andreas Hubertus Montree , Jacobus Bernardus Giesbers , Gerwin Hermanus Gelinck , Martin Hillebrand Blees
IPC分类号： H01L21/027 , H01L21/306 , H01L21/312 , H01L21/768 , H01L21/31 , H01L21/311
CPC分类号： H01L21/02118 , B82Y30/00 , H01L21/312 , H01L21/76802 , H01L21/76829 , H01L21/76838
摘要： A vertical interconnect (15) in an electronic device (10) is manufactured non-photolithographically. This is done by modifying a surface (20,30) of either a metal layer (3) or an intermediate layer of an electrically insulating material (21), and subsequently depositing a composition with a first and a second polymer. Phase separation of the two polymers will lead to a first (6) and a second sub-layer (7), of which the first sub-layer (6) is removed. An upper layer (9) of electrically conducting material can be deposited then or after a further etching step. This results in the vertical interconnect (15).
摘要翻译：电子设备（10）中的垂直互连（15）被非光刻地制造。这通过改变金属层（3）或电绝缘材料（21）的中间层的表面（20,30），随后沉积具有第一和第二聚合物的组合物来完成。两个聚合物的相分离将导致第一子层（6）被去除的第一子层（6）和第二子层（7）。可以在另外的蚀刻步骤之后或之后沉积导电材料的上层（9）。这导致了垂直互连（15）。

22. 发明授权

US06818920B2 Integrated circuit provided with a substrate and memory transponder 失效
标题翻译：集成电路配有基板和存储器应答器
公开(公告)号：US06818920B2
公开(公告)日：2004-11-16
申请号：US09817107
申请日：2001-03-26
申请人： Dagobert Michel De Leeuw , Cornelis Maria Hart , Gerwin Hermanus Gelinck
发明人： Dagobert Michel De Leeuw , Cornelis Maria Hart , Gerwin Hermanus Gelinck
IPC分类号： H01L2358
CPC分类号： H01L27/285 , B82Y10/00 , G11C13/0014 , H01L23/5256 , H01L27/28 , H01L51/0035 , H01L51/0036 , H01L2924/0002 , H01L2924/12044 , H01L2924/00
摘要： The integrated circuit (10) has a substrate and a memory with a first memory unit (30) containing organic material. The first memory unit (30) has a first (26) and a second electrode (28), which are in the non-programmed state electrically connected by an interconnection (27). On programming, the interconnection (27) is at least partially broken in that it is locally heated. This heating can be effected electrically and optically. By preference the first memory unit (30) is integrated in a first layer (6) of organic material, which also has a first electrode (25) of the integrated circuit (10). The integrated circuit (10) can be used in a transponder which is electrically programmable. In the method of programming, the local heating is effected electrically, by applying a voltage across the first memory unit (30).
摘要翻译：集成电路（10）具有衬底和具有含有有机材料的第一存储单元（30）的存储器。第一存储器单元（30）具有通过互连（27）电连接的处于非编程状态的第一电极（26）和第二电极（28）。在编程中，互连（27）至少部分地被断开，因为其被局部加热。这种加热可以电和光学地进行。优选地，第一存储器单元（30）集成在有机材料的第一层（6）中，其还具有集成电路（10）的第一电极（25）。集成电路（10）可用于电可编程的应答器。在编程方法中，通过在第一存储单元（30）上施加电压来实现局部加热。

23. 发明申请

US20120292717A1 INTEGRATED CIRCUIT 审中-公开
标题翻译：集成电路
公开(公告)号：US20120292717A1
公开(公告)日：2012-11-22
申请号：US13497047
申请日：2010-09-22
申请人： Gerwin Hermanus Gelinck , Birgitta Katarina Charlotte Kjellander
发明人： Gerwin Hermanus Gelinck , Birgitta Katarina Charlotte Kjellander
IPC分类号： H01L27/088
CPC分类号： H01L27/283 , H01L51/0545 , H01L51/10
摘要： An integrated circuit, comprising a first insulating layer; a semiconductor layer; a first layer of conductors in near-ohmic or ohmic contact with the semiconductor layer and a second layer of conductors separated from the semiconductor layer by the first insulating layer, the first and second layers of conductors being patterned to form a plurality of functional blocks comprising a plurality of transistors, the first layer conductors serving as source/drain electrodes and the second layer conductors serving as gate electrodes; wherein each functional block comprises a corresponding island of the semiconductor layer isolated from that of another functional block by portions of a second insulating layer, the functional blocks being arranged such that (i) source/drain electrodes that are from different transistors and neighbour one another are arranged to be at the same potential and (ii) no conductors are present between said neighbouring electrodes.
摘要翻译：一种集成电路，包括第一绝缘层; 半导体层; 与半导体层接近欧姆或欧姆接触的第一导体层和由第一绝缘层与半导体层分离的第二导体层，第一和第二导体层被图案化以形成多个功能块，包括多个晶体管，第一层导体用作源/漏电极，第二层导体用作栅电极; 其中每个功能块包括通过第二绝缘层的一部分与另一个功能块的相应的隔离的半导体层的岛，所述功能块被布置为使得（i）来自不同晶体管并且彼此相邻的源/漏电极被布置成处于相同的电位，并且（ii）在所述相邻电极之间不存在导体。

24. 发明申请

US20110227084A1 METHOD OF MANUFACTURING A FLEXIBLE ELECTRONIC DEVICE AND FLEXIBLE DEVICE 有权
标题翻译：制造柔性电子器件和柔性器件的方法
公开(公告)号：US20110227084A1
公开(公告)日：2011-09-22
申请号：US13118556
申请日：2011-05-30
申请人： Jacobus Bernardus Giesbers , Monique Johanna Beenhakkers , Cornelis Johannus Hermanus Antonius Rijpert , Gerwin Hermanus Gelinck , Fredericus Johannes Touwslager
发明人： Jacobus Bernardus Giesbers , Monique Johanna Beenhakkers , Cornelis Johannus Hermanus Antonius Rijpert , Gerwin Hermanus Gelinck , Fredericus Johannes Touwslager
IPC分类号： H01L33/08
CPC分类号： H01L27/1214 , H01L21/76251 , H01L23/49572 , H01L23/4985 , H01L23/5387 , H01L29/78681 , H01L51/0001 , H01L51/0097 , H01L51/052 , H01L51/0545 , H01L2924/0002 , Y02E10/549 , Y02P70/521 , H01L2924/00
摘要： An electrical element, such as a thin-film transistor, is defined on a flexible substrate, in that the substrate is attached to a carrier by an adhesive layer, and is delaminated after definition of the transistor. This is for instance due to illumination by UV-radiation. An opaque coating is provided to protect any semiconductor material. A heat treatment is preferably given before application of the layers of the transistor to reduce stress in the adhesive layer.
摘要翻译：在柔性基板上限定了诸如薄膜晶体管的电气元件，因为基板通过粘合剂层附着到载体上，并且在晶体管定义之后被分层。这是因为例如由于UV辐射的照明。提供不透明涂层以保护任何半导体材料。在施加晶体管层之前优选进行热处理以减少粘合剂层中的应力。

25. 发明授权

US07951687B2 Method of manufacturing a flexible electronic device and flexible device 有权
标题翻译：制造柔性电子装置和柔性装置的方法
公开(公告)号：US07951687B2
公开(公告)日：2011-05-31
申请号：US10551309
申请日：2004-03-30
申请人： Jacobus Bernardus Giesbers , Monique Johanna Beenhakkers , Cornelis Johannus Hermanus Antonius Rijpert , Gerwin Hermanus Gelinck , Fredericus Johannes Touwslager
发明人： Jacobus Bernardus Giesbers , Monique Johanna Beenhakkers , Cornelis Johannus Hermanus Antonius Rijpert , Gerwin Hermanus Gelinck , Fredericus Johannes Touwslager
IPC分类号： H01L21/46
CPC分类号： H01L27/1214 , H01L21/76251 , H01L23/49572 , H01L23/4985 , H01L23/5387 , H01L29/78681 , H01L51/0001 , H01L51/0097 , H01L51/052 , H01L51/0545 , H01L2924/0002 , Y02E10/549 , Y02P70/521 , H01L2924/00
摘要： An electrical element, such as a thin-film transistor, is defined on a flexible substrate, in that the substrate is attached to a carrier by an adhesive layer, and is delaminated after definition of the transistor. This is for instance due to illumination by UV-radiation. An opaque coating is provided to protect any semiconductor material. A heat treatment is preferably given before application of the layers of the transistor to reduce stress in the adhesive layer.
摘要翻译：在柔性基板上限定了诸如薄膜晶体管的电气元件，因为基板通过粘合剂层附着到载体上，并且在晶体管定义之后被分层。这是因为例如由于UV辐射的照明。提供不透明涂层以保护任何半导体材料。在施加晶体管层之前优选进行热处理以减少粘合剂层中的应力。

26. 发明申请

US20110048619A1 STACKED FOIL SHEET DEVICE 失效
标题翻译：堆叠式盖片装置
公开(公告)号：US20110048619A1
公开(公告)日：2011-03-03
申请号：US12823946
申请日：2010-06-25
申请人： Erwin Rinaldo Meinders , Gerwin Hermanus Gelinck
发明人： Erwin Rinaldo Meinders , Gerwin Hermanus Gelinck
IPC分类号： B32B38/00 , B32B38/10
CPC分类号： H05K3/4638 , H05K1/0393 , H05K3/4069 , H05K3/4635 , H05K2201/051 , H05K2201/09036 , H05K2201/09045 , H05K2201/09063 , H05K2201/091 , H05K2203/0108 , H05K2203/0228 , H05K2203/167 , Y10T29/49117 , Y10T29/49155 , Y10T156/1039
摘要： The invention relates to a method of aligning a flexible foil sheet having a general first foil sheet length direction to form stacked foil sheet layers on a reel having a reel diameter. The method comprises providing multiple alignment markers in the foil sheet. distanced conform the reel diameter and each having an mark length direction transverse to the first foil sheet length direction, to form protrusions and corresponding recesses on opposite faces of the foil sheet; winding the foil sheet on the reel in the first foil sheet length direction of the foil sheet; and co-aligning the alignment markers to have protrusions of one mark matching with a recess of another mark, so as to block relative movement of the stacked foil sheet layers in the first foil sheet length direction. Preferably, the foil sheet layers are provided with device functionality to form a stacked foil sheet layered device.
摘要翻译：本发明涉及一种对准具有一般第一箔片长度方向的柔性箔片的方法，以在具有卷轴直径的卷轴上形成叠层的箔片层。该方法包括在箔片中提供多个对准标记。间距适应卷轴直径并且每个具有横向于第一箔片长度方向的标记长度方向，以在箔片的相对面上形成突起和相应的凹槽; 在箔片的第一箔片长度方向上将箔片卷绕在卷轴上; 并且使对准标记共同对准具有与另一标记的凹部匹配的一个标记的突起，以阻止层叠的箔片层在第一箔片长度方向上的相对移动。优选地，箔片层具有器件功能以形成层叠的箔片层状器件。

27. 发明授权

US07651957B2 Structure for a semiconductor arrangement and a method of manufacturing a semiconductor arrangement 有权
标题翻译：半导体装置的结构和制造半导体装置的方法
公开(公告)号：US07651957B2
公开(公告)日：2010-01-26
申请号：US10557622
申请日：2004-05-13
申请人： Paulus Cornelis Duineveld , Gerwin Hermanus Gelinck
发明人： Paulus Cornelis Duineveld , Gerwin Hermanus Gelinck
IPC分类号： H01L21/31 , H01L21/469
CPC分类号： H01L29/41758 , H01L27/28 , H01L51/0004 , H01L51/0016 , H01L51/0037 , H01L51/0508 , H01L51/0545
摘要： The invention relates to a structure for a semiconductor arrangement. A resist structure for supporting deposition of a solution containing a semiconductor is directly or through intervening layers coupled to a substrate. The resist structure comprises a depression (301) for depositing of the solution containing the semiconductor (309) and a trough (305) aligning at least part of an edge of the depression (309) and separated from the depression (309) by a protrusion (307). The trough (305) preferably surrounds the depression (309). The trough provides a pinning effect on the solution containing the semiconductor thereby improving the wettability and accordingly allowing for increased volume of semiconductor to be applied to a given area.
摘要翻译：本发明涉及一种用于半导体装置的结构。用于支持含有半导体的溶液的沉积的抗蚀剂结构直接地或通过耦合到衬底的中间层。抗蚀剂结构包括用于沉积含有半导体（309）的溶液的凹陷（301）和将凹部（309）的边缘的至少一部分对准的凹槽（305）并与凹部（309）分离的凹槽（301）（307）。槽（305）优选围绕凹陷（309）。槽对含有半导体的溶液提供钉扎效应，从而提高润湿性，从而允许将半导体的体积增加到给定区域。

28. 发明申请

US20090065782A1 FIELD SHIELD DIELECTRIC AS A MASK DURING SEMICONDUCTOR INK JET PRINTING 有权
标题翻译：作为半导体喷墨印刷领域的屏蔽电介质
公开(公告)号：US20090065782A1
公开(公告)日：2009-03-12
申请号：US12063398
申请日：2006-08-04
申请人： Fredericus Johannes Touwslager , Gerwin Hermanus Gelinck
发明人： Fredericus Johannes Touwslager , Gerwin Hermanus Gelinck
IPC分类号： H01L33/00 , H01L21/84
CPC分类号： H01L51/0005 , G02F1/167 , H01L51/0036 , H01L51/0055 , H01L51/0097 , H01L51/052 , H01L51/0545
摘要： A display device and method for fabricating includes patterning a field shield dielectric layer to expose conductors and form a cavity over the conductors. InkJet printing a semiconductor material fills a portion of the cavity in contact with the conductors. An insulation material is deposited on the semiconductor material. A pixel pad is formed over the insulation material and the field shield dielectric layer. A pixel is formed which includes a thin film transistor with an ink jet printed semiconductor layer.
摘要翻译：一种显示装置和制造方法包括：图案化场屏蔽介电层以暴露导体并在导体上形成空腔。喷墨打印半导体材料填充与导体接触的腔的一部分。绝缘材料沉积在半导体材料上。在绝缘材料和场屏蔽介电层上方形成像素焊盘。形成像素，其包括具有喷墨印刷半导体层的薄膜晶体管。

29. 发明授权

US06635406B1 Method of producing vertical interconnects between thin film microelectronic devices and products comprising such vertical interconnects 有权
标题翻译：在薄膜微电子器件和包括这种垂直互连的产品之间产生垂直互连的方法
公开(公告)号：US06635406B1
公开(公告)日：2003-10-21
申请号：US09704519
申请日：2000-11-02
申请人： Dagobert Michel De Leeuw , Gerwin Hermanus Gelinck , Marco Matters
发明人： Dagobert Michel De Leeuw , Gerwin Hermanus Gelinck , Marco Matters
IPC分类号： H01L2100
CPC分类号： H01L51/052 , H01L21/76877 , H01L23/5328 , H01L51/0014 , H01L51/0015 , H01L51/0021 , H01L51/0034 , H01L51/0035 , H01L51/0036 , H01L51/0037 , H01L51/0052 , H01L51/0545 , H01L2924/0002 , H01L2924/12044 , H01L2924/00
摘要： The present invention provides a method of photochemically producing a vertical interconnect between a first and a second thin-film microelectronic device in an vertical interconnect area which comprises an overlap of a stack of a first electrically conducting area, optionally an organic electrically semiconducting area, an organic electrically insulating area comprising adapted photoresist material and a second organic electrically conducting area, wherein the organic electrically insulating area is removed within the overlapping area and substituted by an electrically conducting area which is extended from at least said first or said second electrically conducting area. The method is useful in the manufacture of electronic devices, preferably integrated circuits, consisting substantially of organic materials.
摘要翻译：本发明提供了一种在垂直互连区域中光电化生产第一和第二薄膜微电子器件之间的垂直互连的方法，其包括第一导电区域，任选的有机电半导体区域，有机电绝缘区域包括适应的光致抗蚀剂材料和第二有机导电区域，其中所述有机电绝缘区域在所述重叠区域内被移除并被从至少所述第一或所述第二导电区域延伸的导电区域代替。该方法可用于制造基本上由有机材料组成的电子器件，优选集成电路。

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