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21. 发明申请

US20120025392A1 Increased Stability of a Complex Material Stack in a Semiconductor Device by Providing Fluorine Enriched Interfaces 有权
标题翻译：通过提供富含氟的界面增加半导体器件中复杂材料堆叠的稳定性
公开(公告)号：US20120025392A1
公开(公告)日：2012-02-02
申请号：US13115192
申请日：2011-05-25
申请人： Christof Streck , Hartmut Ruelke , Heinz-Juergen Voss
发明人： Christof Streck , Hartmut Ruelke , Heinz-Juergen Voss
IPC分类号： H01L23/48 , H01L21/31 , H01L21/28 , B82Y99/00
CPC分类号： H01L23/53295 , H01L21/76801 , H01L21/76826 , H01L21/76829 , H01L2924/0002 , H01L2924/00
摘要： When forming complex metallization systems, a sensitive material, such as a ULK material, may be deposited on a silicon-containing dielectric material, such as an etch stop material, with superior adhesion by performing a surface treatment on the basis of fluorine radicals. Due to the fluorine treatment, silicon-fluorine bonds are generated, which are then broken up upon interacting with the chemically active component during the further deposition process. Consequently, the subsequent material layer is chemically bonded to the underlying material, thereby imparting superior stability to the interface, which in turn may result in superior robustness and reliability of the metallization system upon performing reflowing processes and operating complex packaged semiconductor devices.
摘要翻译：当形成复杂的金属化系统时，诸如ULK材料的敏感材料可以通过基于氟自由基进行表面处理而沉积在具有优异粘附性的含硅介电材料（例如蚀刻停止材料）上。由于氟处理，产生硅 - 氟键，然后在进一步沉积过程中与化学活性组分相互作用时会分解硅 - 氟键。因此，随后的材料层化学键合到下面的材料上，从而赋予界面更好的稳定性，这又可以在执行回流工艺和操作复杂封装的半导体器件时导致金属化系统的优异的鲁棒性和可靠性。

22. 发明申请

US20100025855A1 ENHANCING STRUCTURAL INTEGRITY AND DEFINING CRITICAL DIMENSIONS OF METALLIZATION SYSTEMS OF SEMICONDUCTOR DEVICES BY USING ALD TECHNIQUES 有权
标题翻译：通过使用ALD技术提高结构完整性和定义半导体器件金属化系统的关键尺寸
公开(公告)号：US20100025855A1
公开(公告)日：2010-02-04
申请号：US12472824
申请日：2009-05-27
申请人： Christof Streck , Volker Kahlert , John A. Iacoponi
发明人： Christof Streck , Volker Kahlert , John A. Iacoponi
IPC分类号： H01L23/522 , H01L21/768
CPC分类号： H01L21/76814 , H01L21/76816 , H01L21/76831
摘要： During the patterning of sophisticated metallization systems, a damaged surface portion of a sensitive low-k dielectric material may be efficiently replaced by a well-controlled dielectric material, thereby enabling an adaptation of the material characteristics and/or the layer thickness of the replacement material. Thus, established lithography and etch techniques may be used in combination with reduced critical dimensions and dielectric materials of even further reduced permittivity.
摘要翻译：在复杂的金属化系统的图案化期间，敏感的低k电介质材料的受损表面部分可以被良好控制的电介质材料有效地代替，从而能够改变替代材料的材料特性和/或层厚度。因此，所建立的光刻和蚀刻技术可以与降低的介电常数的降低的临界尺寸和电介质材料结合使用。

23. 发明申请

US20080179741A1 INCREASING RELIABILITY OF COPPER-BASED METALLIZATION STRUCTURES IN A MICROSTRUCTURE DEVICE BY USING ALUMINUM NITRIDE 有权
标题翻译：通过使用氮化铝在微结构器件中提高基于铜的金属化结构的可靠性
公开(公告)号：US20080179741A1
公开(公告)日：2008-07-31
申请号：US11948245
申请日：2007-11-30
申请人： Christof Streck , Volker Kahlert
发明人： Christof Streck , Volker Kahlert
IPC分类号： H01L23/48 , C23C16/00
CPC分类号： H01L21/02178 , C23C16/303 , C23C16/45525 , H01L21/0228 , H01L21/318 , H01L21/76832 , H01L21/76834 , H01L21/76849 , H01L21/76867
摘要： By forming an aluminum nitride layer by a self-limiting process sequence, the interface characteristics of a copper-based metallization layer may be significantly enhanced while nevertheless maintaining the overall permittivity of the layer stack at a lower level.
摘要翻译：通过自限制工艺顺序形成氮化铝层，可以显着提高铜基金属化层的界面特性，同时保持层叠的整体介电常数处于较低水平。

24. 发明申请

US20060043588A1 Semiconductor device including a low-k metallization layer stack for enhanced resistance against electromigration 审中-公开
标题翻译：半导体器件包括用于增强抵抗电迁移的低k金属化层堆叠
公开(公告)号：US20060043588A1
公开(公告)日：2006-03-02
申请号：US11114335
申请日：2005-04-26
申请人： Christof Streck , Hartmut Ruelke , Michael Kiene
发明人： Christof Streck , Hartmut Ruelke , Michael Kiene
IPC分类号： H01L23/48
CPC分类号： H01L21/76834 , H01L21/02126 , H01L21/02164 , H01L21/02274 , H01L21/02282 , H01L21/02362 , H01L21/3124 , H01L21/31612 , H01L21/31629 , H01L21/31633 , H01L21/76807 , H01L21/76829 , H01L21/76832 , H01L21/76835 , H01L23/53238 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A technique is disclosed which enables the formation of a metallization layer being substantially comprised of a low-k dielectric material, wherein a compressive stress layer provides enhanced electromigration behavior of the metallization layer. In particular embodiments, a compressive silicon dioxide layer may be formed on or in the vicinity of a dielectric barrier layer and a metallization layer based on SiCOH.
摘要翻译：公开了一种能够形成基本上由低k介电材料组成的金属化层的技术，其中压应力层提供金属化层的增强的电迁移行为。在具体实施方案中，压电二氧化硅层可以形成在基于SiCOH的介电阻挡层和金属化层附近或附近。

25. 发明申请

US20060001168A1 Technique for forming a dielectric interlayer above a structure including closely spaced lines 有权
标题翻译：在包括紧密间隔的线的结构之上形成电介质中间层的技术
公开(公告)号：US20060001168A1
公开(公告)日：2006-01-05
申请号：US11082156
申请日：2005-03-16
申请人： Hartmut Ruelke , Christof Streck , Kai Frohberg
发明人： Hartmut Ruelke , Christof Streck , Kai Frohberg
IPC分类号： H01L23/52 , H01L21/4763
CPC分类号： H01L23/53295 , H01L21/76801 , H01L21/76829 , H01L21/76837 , H01L2924/0002 , H01L2924/00
摘要： By depositing the lower portion of a silicon dioxide interlayer dielectric by means of SACVD or HDP-CVD techniques, the generation of voids may be reliably avoided even for devices having spaces between closely spaced lines on the order of 200 nm or less. Moreover, the bulk silicon dioxide material is deposited by well-established plasma enhanced CVD techniques, thereby providing the potential for using well-established process recipes for the subsequent CMP process, so that production yield and cost of ownership may be maintained at a low level.
摘要翻译：通过用SACVD或HDP-CVD技术沉积二氧化硅层间电介质的下部，即使对于在200nm以下的间隔线之间具有空间的器件也可以可靠地避免空穴的产生。此外，本体二氧化硅材料通过公认的等离子体增强CVD技术沉积，从而为后续CMP工艺提供使用确定的工艺配方的潜力，从而可将生产产量和所有权成本维持在较低水平。

26. 发明授权

US06927161B2 Low-k dielectric layer stack including an etch indicator layer for use in the dual damascene technique 失效
标题翻译：包括用于双镶嵌技术的蚀刻指示层的低k介电层堆叠
公开(公告)号：US06927161B2
公开(公告)日：2005-08-09
申请号：US10420214
申请日：2003-04-22
申请人： Hartmut Ruelke , Christof Streck , Georg Sulzer
发明人： Hartmut Ruelke , Christof Streck , Georg Sulzer
IPC分类号： H01L21/768 , H01L23/532 , H01L21/4763
CPC分类号： H01L21/76829 , H01L21/76807 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A low-k dielectric layer stack is provided including a silicon based dielectric material with a low permittivity, wherein an intermediate silicon oxide based etch indicator layer is arranged at a depth that represents the depth of a trench to be formed in the dielectric layer stack. A thickness of the etch indicator layer is sufficiently small to not unduly compromise the overall permittivity of the dielectric layer stack. On the other hand, the etch indicator layer provides a prominent optical emission spectrum to reliably determine the time point when the etch process has reached the etch indicator layer. Thus, the depth of trenches in highly sophisticated low-k dielectric layer stacks may reliably be adjusted to minimize resistance variations of the metal lines.
摘要翻译：提供了一种低k电介质层堆叠，其包括具有低介电常数的硅基电介质材料，其中基于中间氧化硅的蚀刻指示剂层布置在表示要在电介质层堆叠中形成的沟槽的深度的深度处。蚀刻指示层的厚度足够小以至不会不利地损害介电层叠层的整个介电常数。另一方面，蚀刻指示层提供突出的发射光谱，以可靠地确定蚀刻工艺已经到达蚀刻指示层的时间点。因此，可以可靠地调整高度复杂的低k电介质层叠层中的沟槽的深度，以最小化金属线的电阻变化。

27. 发明授权

US06317642B1 Apparatus and methods for uniform scan dispensing of spin-on materials 有权
标题翻译：用于均匀扫描分配旋涂材料的装置和方法
公开(公告)号：US06317642B1
公开(公告)日：2001-11-13
申请号：US09191438
申请日：1998-11-12
申请人： Lu You , Dawn Hopper , Christof Streck , John Pellerin , Richard J. Huang
发明人： Lu You , Dawn Hopper , Christof Streck , John Pellerin , Richard J. Huang
IPC分类号： G06F1900
CPC分类号： H01L21/6715 , B05D1/005
摘要： This invention describes improved apparatus and methods for spin-on deposition of semiconductor thin films. The improved apparatus provides for controlled temperature, pressure and gas compositions within the deposition chamber. The improved methods comprise dispensing of solutions containing thin film precursor via a moveable dispensing device and the careful regulation of the pattern of deposition of the precursor solution onto the wafer. The invention also comprises the careful regulation of deposition variables including dispensation time, wafer rpm, stop time and rates of wafer rotation. In one embodiment, the precursor solution is dispensed from the outer edge of the wafer toward the center. In alternative embodiments, processors regulate the movement of the dispensing arm and the precursor pump to provide an evenly dispensed layer of precursor solution. The invention also describes improved methods for evaporating solvents and curing thin films. The methods of this invention enable the production of spin-on thin films, which have more even film thickness and uniformity. The semiconductor thin films produced by the methods of this invention are useful for the manufacture of semiconductor devices comprising interlevel dielectric materials.
摘要翻译：本发明描述了用于半导体薄膜的旋涂沉积的改进的装置和方法。改进的装置提供沉积室内的受控温度，压力和气体组成。改进的方法包括通过可移动的分配装置分配含有薄膜前体的溶液，以及仔细调节前体溶液沉积在晶片上的图案。本发明还包括仔细调节沉积变量，包括分配时间，晶片转速，停止时间和晶片旋转速率。在一个实施方案中，前体溶液从晶片的外边缘向中心分配。在替代实施例中，处理器调节分配臂和前驱泵的运动，以提供均匀分配的前体溶液层。本发明还描述了用于蒸发溶剂和固化薄膜的改进方法。本发明的方法能够生产具有更均匀的膜厚度和均匀性的旋涂薄膜。通过本发明的方法生产的半导体薄膜可用于制造包括层间电介质材料的半导体器件。

28. 发明授权

US6066574A Hot plate cure process for BCB low k interlevel dielectric 有权
标题翻译： BCB低k层间电介质的热板固化工艺
公开(公告)号：US6066574A
公开(公告)日：2000-05-23
申请号：US187429
申请日：1998-11-06
申请人： Lu You , Dawn Hopper , Christof Streck
发明人： Lu You , Dawn Hopper , Christof Streck
IPC分类号： H01L21/3105 , H01L21/312 , H01L21/768 , H01L21/31
CPC分类号： H01L21/31058 , H01L21/312
摘要： A dielectric layer comprising a benzocyclobutene (BCB)-based low dielectric constant (low k) material is formed on a surface of a semiconductor wafer substrate by (a) spin coating a layer of a fluid material comprising BCB in a liquid solvent or dispersant vehicle on the substrate; (b) baking the coated substrate at a first temperature and for a first time interval to remove the solvent; (c) curing the baked coating by heating at a second temperature higher than the first temperature, and for a second time interval; and (d) subjecting the substrate with cured coating thereon to a cool-down treatment at a third temperature and for a third time interval. Embodiments include performing steps (a)-(d) consecutively and in the same apparatus. Other embodiments include processing in an "on track" type automated semiconductor processing apparatus.
摘要翻译：通过以下步骤，在半导体晶片衬底的表面上形成包含基于苯并环丁烯（BCB）的低介电常数（低k）材料的电介质层：（a）在液体溶剂或分散剂载体中旋涂包含BCB的流体材料层在基材上（b）在第一温度和第一时间间隔烘烤涂覆的基材以除去溶剂; （c）通过在高于第一温度的第二温度下加热固化烘烤的涂层，并且持续第二时间间隔; 和（d）在其上固化的涂层对基板进行第三温度和第三时间间隔的冷却处理。实施例包括在相同的装置中连续执行步骤（a） - （d）。其他实施例包括在“轨道”型自动半导体处理装置中的处理。

29. 发明授权

US08432035B2 Metal cap layer with enhanced etch resistivity for copper-based metal regions in semiconductor devices 有权
标题翻译：具有增强的半导体器件中铜基金属区域的蚀刻电阻率的金属覆盖层
公开(公告)号：US08432035B2
公开(公告)日：2013-04-30
申请号：US13297860
申请日：2011-11-16
申请人： Volker Kahlert , Christof Streck
发明人： Volker Kahlert , Christof Streck
IPC分类号： H01L23/48 , H01L21/4763
CPC分类号： H01L21/76849 , H01L21/76814 , H01L21/76843 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： During the fabrication of sophisticated metallization systems of semiconductor devices, material deterioration of conductive cap layers may be significantly reduced by providing a noble metal on exposed surface areas after the patterning of the corresponding via openings. In one embodiment, a semiconductor device is provided that includes a metallization system formed above a substrate. The metallization system includes a metal line formed in a dielectric layer and having a top surface. The metallization system also includes a conductive cap layer formed on the top surface. A via extends through the conductive cap layer and connects to the top surface of the metal line. A conductive barrier layer is formed on sidewalls of the via. An interface layer is formed of a noble metal between the conductive cap layer and the conductive barrier layer and between the top surface of the metal line and the conductive barrier layer.
摘要翻译：在制造半导体器件的复杂的金属化系统期间，通过在对应的通路孔的图案化之后在暴露的表面区域上提供贵金属可以显着降低导电盖层的材料劣化。在一个实施例中，提供了一种半导体器件，其包括在衬底上形成的金属化系统。金属化系统包括形成在电介质层中并具有顶表面的金属线。金属化系统还包括形成在顶表面上的导电盖层。通孔延伸穿过导电盖层并连接到金属线的顶表面。导电阻挡层形成在通孔的侧壁上。界面层由导电盖层和导电阻挡层之间以及金属线的顶表面和导电阻挡层之间的贵金属形成。

30. 发明申请

US20100078821A1 METAL CAP LAYER WITH ENHANCED ETCH RESISTIVITY FOR COPPER-BASED METAL REGIONS IN SEMICONDUCTOR DEVICES 有权
标题翻译：金属层与半导体器件中铜基金属区域的增强蚀刻电阻率
公开(公告)号：US20100078821A1
公开(公告)日：2010-04-01
申请号：US12493366
申请日：2009-06-29
申请人： Volker Kahlert , Christof Streck
发明人： Volker Kahlert , Christof Streck
IPC分类号： H01L23/522 , H01L21/768
CPC分类号： H01L21/76849 , H01L21/76814 , H01L21/76843 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： During the fabrication of sophisticated metallization systems of semiconductor devices, material deterioration of conductive cap layers may be significantly reduced by providing a noble metal on exposed surface areas after the patterning of the corresponding via openings. Hence, well-established wet chemical etch chemistries may be used while not unduly contributing to process complexity.
摘要翻译：在制造半导体器件的复杂的金属化系统期间，通过在对应的通路孔的图案化之后在暴露的表面区域上提供贵金属可以显着降低导电盖层的材料劣化。因此，可以使用公认的湿化学蚀刻化学品，而不会过度地造成工艺复杂性。

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