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21. 发明授权

US06710397B1 Nonvolatile semiconductor memory device having divided bit lines 失效
标题翻译：具有划分位线的非易失性半导体存储器件
公开(公告)号：US06710397B1
公开(公告)日：2004-03-23
申请号：US10604406
申请日：2003-07-17
申请人： Ching-Hsiang Hsu , Ching-Sung Yang
发明人： Ching-Hsiang Hsu , Ching-Sung Yang
IPC分类号： H01L29788
CPC分类号： G11C16/24
摘要： A non-volatile semiconuctor memory device having divided bit lines. A main bit line controlled by at least one bit line selection device to transfer its potential selected sub bit line, such that memory cells in a selected work and overloading of the bit line generated by a parasitic capacitance can be prevented. The memory cells and the bit line selection device arranged in parallel in a P-well and a N-well, respectively, thereby preventing disturbances during programming or erasing the bit line.
摘要翻译：具有划分位线的非易失性半导体存储器件。由至少一个位线选择装置控制的主位线传送其潜在的选择的子位线，使得可以防止所选择的工作中的存储器单元和由寄生电容产生的位线的过载。存储单元和位线选择装置分别并排布置在P阱和N阱中，从而防止在编程或擦除位线期间的干扰。

22. 发明授权

US06678190B2 Single poly embedded eprom 有权
标题翻译：单聚嵌入eprom
公开(公告)号：US06678190B2
公开(公告)日：2004-01-13
申请号：US10055047
申请日：2002-01-25
申请人： Ching-Sung Yang , Shih-Jye Shen , Ching-Hsiang Hsu
发明人： Ching-Sung Yang , Shih-Jye Shen , Ching-Hsiang Hsu
IPC分类号： G11C1604
CPC分类号： H01L27/11521 , G11C16/0408 , G11C16/0433 , G11C2216/10 , H01L27/11558
摘要： An erasable programmable read only memory comprising two serially connected P-type metal-oxide semiconductor (MOS) transistors wherein the control gate is omitted in the structure for layout as the bias is not necessary to apply to the floating gate during the programming mode.
摘要翻译：一种可擦除可编程只读存储器，包括两个串联连接的P型金属氧化物半导体（MOS）晶体管，其中在布局结构中省略了控制栅极，因为在编程模式期间偏置不需要应用于浮动栅极。

23. 发明授权

US06677198B2 Structure of a low-voltage channel write/erase flash memory cell and fabricating method thereof 失效
标题翻译：低电压通道写入/擦除闪存单元的结构及其制造方法
公开(公告)号：US06677198B2
公开(公告)日：2004-01-13
申请号：US10064109
申请日：2002-06-12
申请人： Ching-Hsiang Hsu , Ching-Sung Yang
发明人： Ching-Hsiang Hsu , Ching-Sung Yang
IPC分类号： H01L21336
CPC分类号： H01L29/66825 , H01L21/28273 , H01L29/7883
摘要： The present invention relates to a structure of a low-voltage channel write/erase flash memory cell and a fabricating method thereof, which structure comprises an N-substrate, a deep P-well formed on the substrate, and an N-well formed on the deep P-well. A deep p-type region and a shallow p-type region are ion-implanted in the N-well. The deep p-type region is connected to the shallow p-type region. An n-type region is ion-implanted in the deep p-type region to be electrically shorted with the deep p-type region and be used as a drain. Another n-type region is also ion-implanted at one side of the shallow p-type region to be used as a source. The present invention can apply the same voltage to the deep P-well and the N-well on the N-substrate by adding in a triple well architecture so that the leakage current capably generated can be reduced to minimum, thereby effectively reducing end voltages when performing the operation of erasing, simplifying the design complexity of a charge pump circuit required by the whole structure, and enhancing the operating efficiency.
摘要翻译：本发明涉及一种低电压通道写入/擦除闪速存储单元的结构及其制造方法，该结构包括N衬底，在衬底上形成的深P阱以及形成在N阱上的N阱深P井。将深P型区域和浅P型区域离子注入到N阱中。深P型区域连接到浅P型区域。在深p型区域中离子注入n型区域，与深p型区域电短路并用作漏极。另一个n型区域也被离子注入在用作源的浅P型区域的一侧。本发明可以通过添加三阱结构将相同的电压施加在N衬底上的深P阱和N阱上，使得可以产生的泄漏电流可以减小到最小，从而有效地减少最终电压，当执行擦除操作，简化了整个结构所需的电荷泵电路的设计复杂度，提高了运行效率。

24. 发明授权

US06673624B2 Method and device for diagnosing disease patterns in Traditional Chinese Medicine 失效
标题翻译：中医诊断疾病模式的方法与装置
公开(公告)号：US06673624B2
公开(公告)日：2004-01-06
申请号：US09834296
申请日：2001-04-12
申请人： Ching-Hsiang Hsu
发明人： Ching-Hsiang Hsu
IPC分类号： G01N3300
CPC分类号： G01N33/6863 , G01N33/68 , G01N33/6854
摘要： The present invention provides a method of facilitating the diagnosis, monitoring and treatment of a human patient by measuring the ECP level in the patient's blood, and determining whether the patient is within the heat pattern group or the non-heat pattern group based on the measure ECP level.
摘要翻译：本发明提供了一种通过测量患者血液中的ECP水平来确定患者是否处于热模式组或非热模式组内的方式来促进人类患者的诊断，监测和治疗的方法， ECP等级。

25. 发明授权

US06489202B1 Structure of an embedded channel write-erase flash memory cell and fabricating method thereof 失效
标题翻译：嵌入式通道写入 - 擦除闪存单元的结构及其制造方法
公开(公告)号：US06489202B1
公开(公告)日：2002-12-03
申请号：US09865432
申请日：2001-05-29
申请人： Ching-Hsiang Hsu , Ching-Sung Yang
发明人： Ching-Hsiang Hsu , Ching-Sung Yang
IPC分类号： H01L218247
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/115 , H01L27/11546
摘要： The present invention relates to a structure of an embedded channel write/erase flash memory cell and a fabricating method thereof and, more particularly, to a structure combining CMOS devices and flash memory cells, wherein flash memory cell structures and CMOS devices are simultaneously fabricated on a substrate to reduce the cost and to simplify the process flow. Moreover, CMOS devices capable of performing high-voltage and low-voltage operations are reserved. Therefore, the present invention can not only effectively improve the operating efficiency of flash memory cells and CMOS devices, but its whole volume is also smaller than that obtained by combining separately designed and fabricated CMOS devices and flash memory cells.
摘要翻译：本发明涉及嵌入式通道写入/擦除闪存单元的结构及其制造方法，更具体地说，涉及组合CMOS器件和闪存单元的结构，其中闪存单元结构和CMOS器件同时制造在一种降低成本并简化工艺流程的基板。此外，保留能够执行高电压和低电压操作的CMOS器件。因此，本发明不仅可以有效提高闪存单元和CMOS器件的工作效率，而且其整体体积也小于通过组合分别设计和制造的CMOS器件和闪存单元获得的整体体积。

26. 发明授权

US06441443B1 Embedded type flash memory structure and method for operating the same 失效
标题翻译：嵌入式闪存结构及其操作方法
公开(公告)号：US06441443B1
公开(公告)日：2002-08-27
申请号：US09781430
申请日：2001-02-13
申请人： Ching-Hsiang Hsu , Ching-Sung Yang
发明人： Ching-Hsiang Hsu , Ching-Sung Yang
IPC分类号： H01L2976
CPC分类号： H01L27/115 , G11C16/0416 , H01L29/792
摘要： The present invention provides an embedded type flash memory structure and a method for operating the same. The memory structure of the present invention comprises a first deep doped-region formed on the surface of a semiconductor substrate. A second doped-region is implanted in the first deep doped-region. A plurality of first shallow doped-regions are respectively formed in the second doped-region and the first deep doped-region to be used as drains and sources. A dielectric insulating layer and a poly-silicon gate are stacked above the first deep doped-region between the source and the drain. The present invention also proposes programming, erasing, and reading processes corresponding to the flash memory cell structure.
摘要翻译：本发明提供一种嵌入式闪速存储器结构及其操作方法。本发明的存储器结构包括在半导体衬底的表面上形成的第一深掺杂区域。在第一深掺杂区域中注入第二掺杂区域。多个第一浅掺杂区域分别形成在第二掺杂区域和第一深掺杂区域中，用作下水和源。在源极和漏极之间的第一深掺杂区域的上方堆叠介电绝缘层和多晶硅栅极。本发明还提出了对应于闪存单元结构的编程，擦除和读取处理。

27. 发明授权

US06429081B1 Parasitic surface transfer transistor cell (PASTT cell) for bi-level and multi-level NAND flash memory 有权
标题翻译：用于双电平和多电平NAND闪存的寄生面转移晶体管单元（PASTT cell）
公开(公告)号：US06429081B1
公开(公告)日：2002-08-06
申请号：US09858530
申请日：2001-05-17
申请人： Kelvin Yin-Yuh Doong , Ching-Hsiang Hsu
发明人： Kelvin Yin-Yuh Doong , Ching-Hsiang Hsu
IPC分类号： H01L21336
CPC分类号： H01L27/11521 , G11C2211/5641 , H01L27/115
摘要： A new Flash memory cell device with a parasitic surface transfer transistor (PASTT) and a method of manufacture are achieved. The device comprises, first, a semiconductor substrate. The semiconductor substrate further comprises an active area and an isolation barrier region. A source junction is in the active area. A drain junction is in the active area. A cell channel is in the active area extending from the drain junction to the source junction. A parasitic channel is in the active area on the top surface of the semiconductor substrate extending from the drain junction to the source junction. The parasitic channel is bounded on one side by the isolation barrier region and on another side by the cell channel. A floating gate comprises a first conductive layer overlying the cell channel with a tunneling oxide layer therebetween. The floating gate does not overlie the parasitic channel. A control gate comprises a second conductive layer overlying the floating gate with an interlevel dielectric layer therebetween. A parasitic surface transfer-transistor (PASTT) gate comprises the second conductive layer overlying the parasitic channel with the interlevel dielectric layer therebetween.
摘要翻译：实现了具有寄生面转移晶体管（PASTT）和制造方法的新的闪存单元器件。该器件首先包括半导体衬底。半导体衬底还包括有源区和隔离屏障区。源结点处于活动区域。漏极结处于有源区。电池通道在从漏极结延伸到源极结的有源区中。寄生沟道位于半导体衬底的顶表面上的从漏极结延伸到源极结的有源区中。寄生通道在一侧由隔离屏障区域限定，另一侧由单元通道限制。浮动栅极包括覆盖电池沟道的第一导电层，其间具有隧道氧化物层。浮动栅极不会覆盖寄生通道。控制栅极包括覆盖浮置栅极的第二导电层，其间具有层间电介质层。寄生表面转移晶体管（PASTT）栅极包括覆盖寄生沟道的第二导电层，其间具有层间电介质层。

28. 发明授权

US06188614B1 Structure of a channel write/erase flash memory cell and manufacturing method and operating method thereof 失效
公开(公告)号：US06188614B1
公开(公告)日：2001-02-13
申请号：US09564819
申请日：2000-05-04
申请人： Ching-Hsiang Hsu , Ching-Song Yang
发明人： Ching-Hsiang Hsu , Ching-Song Yang
IPC分类号： G11C1604
CPC分类号： H01L29/66825 , G11C16/10 , H01L29/7885
摘要： A channel write/erase flash memory cell structure together with its method of manufacture and mode of operation. The flash memory cell structure is formed by implanting P-type ions into a substrate to form a shallow-doped region, and then implanting N-type ions to form the drain terminal of the flash memory cell. Next, a deep-doped region that acts as a P-well is formed underneath the drain terminal. Method of manufacturing the channel write/erase memory cell and its mode of operation is also discussed.

29. 发明授权

US6054348A Self-aligned source process 失效
标题翻译：自对准源程序
公开(公告)号：US6054348A
公开(公告)日：2000-04-25
申请号：US79880
申请日：1998-05-15
申请人： Ruei-Ling Lin , Ching-Hsiang Hsu , Mong-Song Liang
发明人： Ruei-Ling Lin , Ching-Hsiang Hsu , Mong-Song Liang
IPC分类号： H01L21/336 , H01L21/8247
CPC分类号： H01L27/11519 , H01L27/11521 , H01L29/66659
摘要： A process for creating a semiconductor memory device, featuring the formation of FOX regions, after the creation of a source region, has been developed. The process features a source region, self-aligned to a first set of stacked gate structures, with the subsequent FOX region placed perpendicular to the source region, between a second set of stacked gate structures.
摘要翻译：已经开发了在创建源区域之后形成FOX区域的半导体存储器件的制造工艺。该过程的特征在于源区域与第一组堆叠的栅极结构自对准，随后的FOX区域垂直于源区域放置在第二组堆叠栅极结构之间。

30. 发明授权

US5726070A Silicon-rich tunnel oxide formed by oxygen implantation for flash EEPROM 失效
标题翻译：富氧隧道氧化物通过氧气注入形成快闪EEPROM
公开(公告)号：US5726070A
公开(公告)日：1998-03-10
申请号：US622692
申请日：1996-03-26
申请人： Gary Hong , Ching-Hsiang Hsu
发明人： Gary Hong , Ching-Hsiang Hsu
IPC分类号： H01L21/28 , H01L21/336 , H01L29/51 , H01L29/788 , H01L21/8247
CPC分类号： H01L21/28185 , H01L29/513 , H01L29/66825 , H01L29/7882 , H01L21/28194
摘要： A process for forming an EEPROM having silicon rich tunnel oxide is disclosed. This oxide is used in the formation of flash EEPROMs and results in high tunneling current at low voltages. The oxide also results in EEPROMs having good endurance. A layer of silicon enriched with oxygen is formed between the substrate and the insulating layer separating the substrate from the floating gate.
摘要翻译：公开了一种形成具有富硅隧道氧化物的EEPROM的工艺。该氧化物用于形成快速EEPROM，并在低电压下产生高隧穿电流。氧化物还导致具有良好耐久性的EEPROM。在衬底和将衬底与浮动栅极分离的绝缘层之间形成富含氧的一层硅。

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