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21. 发明申请

US20130326455A1 ELEMENT PLACEMENT IN CIRCUIT DESIGN BASED ON PREFERRED LOCATION 有权
标题翻译：基于优选位置的电路设计中的元件放置
公开(公告)号：US20130326455A1
公开(公告)日：2013-12-05
申请号：US13485828
申请日：2012-05-31
申请人： Charles J. Alpert , Gi-Joon Nam , Chin Ngai Sze , Paul G. Villarrubia , Natarajan Viswanathan
发明人： Charles J. Alpert , Gi-Joon Nam , Chin Ngai Sze , Paul G. Villarrubia , Natarajan Viswanathan
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , G06F17/5068 , G06F17/5081
摘要： An improved circuit design system may include a computer processor to perform a placement for a circuit by physical synthesis. The system may also include a controller to compute a preferred location of at least one selected element of the circuit, and to calculate placement constraints for each selected element. The system may further include an updated design for the circuit generated by performing another round of physical synthesis with the placement constraints.
摘要翻译：改进的电路设计系统可以包括计算机处理器，以通过物理合成来执行电路的放置。该系统还可以包括控制器，用于计算电路的至少一个选定元件的优选位置，并且计算每个选定元件的放置约束。该系统可以进一步包括通过用放置约束执行另一轮物理合成而产生的电路的更新设计。

22. 发明授权

US09524363B2 Element placement in circuit design based on preferred location 有权
标题翻译：基于优选位置的电路设计元素放置
公开(公告)号：US09524363B2
公开(公告)日：2016-12-20
申请号：US13485828
申请日：2012-05-31
申请人： Charles J. Alpert , Gi-Joon Nam , Chin Ngai Sze , Paul G. Villarrubia , Natarajan Viswanathan
发明人： Charles J. Alpert , Gi-Joon Nam , Chin Ngai Sze , Paul G. Villarrubia , Natarajan Viswanathan
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , G06F17/5068 , G06F17/5081
摘要： An improved circuit design system may include a computer processor to perform a placement for a circuit by physical synthesis. The system may also include a controller to compute a preferred location of at least one selected element of the circuit, and to calculate placement constraints for each selected element. The system may further include an updated design for the circuit generated by performing another round of physical synthesis with the placement constraints.
摘要翻译：改进的电路设计系统可以包括计算机处理器，以通过物理合成来执行电路的放置。该系统还可以包括控制器，用于计算电路的至少一个选定元件的优选位置，并且计算每个选定元件的放置约束。该系统可以进一步包括通过用放置约束执行另一轮物理合成而产生的电路的更新设计。

23. 发明申请

US20080295051A1 SLEW CONSTRAINED MINIMUM COST BUFFERING 有权
标题翻译： SLEW约束最小成本缓冲
公开(公告)号：US20080295051A1
公开(公告)日：2008-11-27
申请号：US12168153
申请日：2008-07-06
申请人： Charles J. Alpert , Arvind K. Karandikar , Tuhin Mahmud , Stephen T. Quay , Chin Ngai Sze
发明人： Charles J. Alpert , Arvind K. Karandikar , Tuhin Mahmud , Stephen T. Quay , Chin Ngai Sze
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： A buffer insertion technique addresses slew constraints while minimizing buffer cost. The method builds initial solutions for the sinks, each having an associated cost, slew and capacitance. As a solution propagates toward a source, wire capacitance and wire slew are added to the solution. When a buffer is selected for possible insertion, the slew of the solution is set to zero while the cost of the solution is incremented based on the selected buffer and the capacitance is set to an intrinsic capacitance of the buffer. The solutions of two intersecting wire branches are merged by adding branch capacitances and costs, and selecting the highest branch slew. The solution sets are updated by disregarding solutions which have a slew component greater than a slew constraint, and any solution that is dominated by another solution is eliminated. The solution having the smallest cost is selected as the final solution.
摘要翻译：缓冲插入技术解决了压摆约束，同时最大限度地减少了缓冲区成本。该方法构建了汇的初始解决方案，每个都具有相关的成本，压摆和电容。当解决方案向源传播时，将线电容和线压力加到解决方案中。当选择缓冲器进行可能的插入时，将解决方案的电压设置为零，同时根据所选择的缓冲器增加解决方案的成本，并将电容设置为缓冲器的固有电容。通过增加分支电容和成本，并选择最高的分支电压，合并两条相交线分支的解决方案。解决方案集通过忽略具有大于压摆约束的转矩分量的解决方案来更新，并且消除由另一解决方案主导的任何解决方案。选择具有最小成本的解决方案作为最终解决方案。

24. 发明申请

US20080148203A1 Latch Placement for High Performance and Low Power Circuits 有权
标题翻译：用于高性能和低功耗电路的锁存放置
公开(公告)号：US20080148203A1
公开(公告)日：2008-06-19
申请号：US11610567
申请日：2006-12-14
申请人： Charles J. Alpert , Shyam Ramji , Chin Ngai Sze , Paul G Villarrubia
发明人： Charles J. Alpert , Shyam Ramji , Chin Ngai Sze , Paul G Villarrubia
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： A novel iterative latch placement scheme wherein the latches are gradually pulled by increasing attraction force until they are eventually placed next to a clock distribution structure such as a local clock buffer (LCB). During the iterations, timing optimizations such as gate sizing and re-buffering are invoked in order to keep the timing estimation accurate. By applying the iterative clock net weighting adjustment, the present invention allows tighter interaction between logic placement and clock placement which leads to higher quality timing and significant power savings.
摘要翻译：一种新颖的迭代锁存器放置方案，其中锁存器通过增加吸引力而逐渐拉动，直到它们最终被放置在诸如本地时钟缓冲器（LCB）之类的时钟分布结构旁边。在迭代期间，调用诸如门尺寸和重新缓冲之类的定时优化，以便使时序估计保持准确。通过应用迭代时钟网络加权调整，本发明允许逻辑放置和时钟布置之间的更紧密的交互，这导致更高的质量定时和显着的功率节省。

25. 发明授权

US07549137B2 Latch placement for high performance and low power circuits 有权
标题翻译：用于高性能和低功耗电路的锁存放置
公开(公告)号：US07549137B2
公开(公告)日：2009-06-16
申请号：US11610567
申请日：2006-12-14
申请人： Charles J. Alpert , Shyam Ramji , Chin Ngai Sze , Paul G. Villarrubia
发明人： Charles J. Alpert , Shyam Ramji , Chin Ngai Sze , Paul G. Villarrubia
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： A novel iterative latch placement scheme wherein the latches are gradually pulled by increasing attraction force until they are eventually placed next to a clock distribution structure such as a local clock buffer (LCB). During the iterations, timing optimizations such as gate sizing and re-buffering are invoked in order to keep the timing estimation accurate. By applying the iterative clock net weighting adjustment, the present invention allows tighter interaction between logic placement and clock placement which leads to higher quality timing and significant power savings.
摘要翻译：一种新颖的迭代锁存器放置方案，其中锁存器通过增加吸引力而逐渐拉动，直到它们最终被放置在诸如本地时钟缓冲器（LCB）之类的时钟分布结构旁边。在迭代期间，调用诸如门尺寸和重新缓冲之类的定时优化，以便使时序估计保持准确。通过应用迭代时钟网络加权调整，本发明允许逻辑放置和时钟布置之间的更紧密的交互，这导致更高的质量定时和显着的功率节省。

26. 发明授权

US07448007B2 Slew constrained minimum cost buffering 有权
标题翻译：压缩约束最低成本缓冲
公开(公告)号：US07448007B2
公开(公告)日：2008-11-04
申请号：US11457495
申请日：2006-07-14
申请人： Charles J. Alpert , Arvind K. Karandikar , Tuhin Mahmud , Stephen T. Quay , Chin Ngai Sze
发明人： Charles J. Alpert , Arvind K. Karandikar , Tuhin Mahmud , Stephen T. Quay , Chin Ngai Sze
IPC分类号： G06F17/50 , G06F9/45
CPC分类号： G06F17/5045
摘要： A buffer insertion technique addresses slew constraints while minimizing buffer cost. The method builds initial solutions for the sinks, each having an associated cost, slew and capacitance. As a solution propagates toward a source, wire capacitance and wire slew are added to the solution. When a buffer is selected for possible insertion, the slew of the solution is set to zero while the cost of the solution is incremented based on the selected buffer and the capacitance is set to an intrinsic capacitance of the buffer. The solutions of two intersecting wire branches are merged by adding branch capacitances and costs, and selecting the highest branch slew. The solution sets are updated by disregarding solutions which have a slew component greater than a slew constraint, and any solution that is dominated by another solution is eliminated. The solution having the smallest cost is selected as the final solution.
摘要翻译：缓冲插入技术解决了压摆约束，同时最大限度地减少了缓冲区成本。该方法构建了汇的初始解决方案，每个都具有相关的成本，压摆和电容。当解决方案向源传播时，将线电容和线压力加到解决方案中。当选择缓冲器进行可能的插入时，将解决方案的电压设置为零，同时根据所选择的缓冲器增加解决方案的成本，并将电容设置为缓冲器的固有电容。通过增加分支电容和成本，并选择最高的分支电压，合并两条相交线分支的解决方案。解决方案集通过忽略具有大于压摆约束的转矩分量的解决方案来更新，并且消除由另一解决方案主导的任何解决方案。选择具有最小成本的解决方案作为最终解决方案。

27. 发明申请

US20080016479A1 Slew Constrained Minimum Cost Buffering 有权
标题翻译：压缩约束最小成本缓冲
公开(公告)号：US20080016479A1
公开(公告)日：2008-01-17
申请号：US11457495
申请日：2006-07-14
申请人： Charles J. Alpert , Arvind K. Karandikar , Tuhin Mahmud , Stephen T. Quay , Chin Ngai Sze
发明人： Charles J. Alpert , Arvind K. Karandikar , Tuhin Mahmud , Stephen T. Quay , Chin Ngai Sze
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： A buffer insertion technique addresses slew constraints while minimizing buffer cost. The method builds initial solutions for the sinks, each having an associated cost, slew and capacitance. As a solution propagates toward a source, wire capacitance and wire slew arc added to the solution. When a buffer is selected for possible insertion, the slew of the solution is set to zero while the cost of the solution is incremented based on the selected buffer and the capacitance is set to an intrinsic capacitance of the buffer. The solutions of two intersecting wire branches are merged by adding branch capacitances and costs, and selecting the highest branch slew. The solution sets are updated by disregarding solutions which have a slew component greater than a slew constraint, and any solution that is dominated by another solution is eliminated. The solution having the smallest cost is selected as the final solution.
摘要翻译：缓冲插入技术解决了压摆约束，同时最大限度地减少了缓冲区成本。该方法构建了汇的初始解决方案，每个都具有相关的成本，压摆和电容。当解决方案向源传播时，将线电容和电线电弧加到溶液中。当选择缓冲器进行可能的插入时，将解决方案的电压设置为零，同时根据所选择的缓冲器增加解决方案的成本，并将电容设置为缓冲器的固有电容。通过增加分支电容和成本，并选择最高的分支电压，合并两条相交线分支的解决方案。解决方案集通过忽略具有大于压摆约束的转矩分量的解决方案来更新，并且消除由另一解决方案主导的任何解决方案。选择具有最小成本的解决方案作为最终解决方案。

28. 发明授权

US08010926B2 Clock power minimization with regular physical placement of clock repeater components 失效
标题翻译：时钟功率最小化，具有定时物理放置的时钟中继器组件
公开(公告)号：US08010926B2
公开(公告)日：2011-08-30
申请号：US12022849
申请日：2008-01-30
申请人： Charles J. Alpert , Ruchir Puri , Shyam Ramji , Ashish K. Singh , Chin Ngai Sze
发明人： Charles J. Alpert , Ruchir Puri , Shyam Ramji , Ashish K. Singh , Chin Ngai Sze
IPC分类号： G06F17/50
CPC分类号： G06F17/5077 , G06F2217/62
摘要： Power, routability and electromigration have become crucial issues in modern microprocessor designs. In high performance designs, clocks are the highest consumer of power. Arranging clocking components with regularity so as to minimize the capacitance on the clock nets can help reduce clock power, however, it may hurt performance due to some loss of flexibility in physically placing those components. The present invention provides techniques to optimally place clock components in a regular fashion so as to minimize clock power within a performance constraint. A rectangular grid is created and clock distribution structures are assigned to the grid intersection points. Latches are then located around the clock distribution structures to minimize an overall distance for connections between the latches and respective clock distribution structures. The horizontal and vertical pitches of the grid may be independently adjusted to achieve a more uniform spread of the clock distribution structures.
摘要翻译：电力，可布线性和电迁移在现代微处理器设计中成为关键问题。在高性能设计中，时钟是功耗最大的消费者。排列时钟元件的规律性，以便最小化时钟网络上的电容可以帮助降低时钟功率，但是，由于物理放置这些组件的灵活性会有所损失，可能会损害性能。本发明提供了以规则方式最佳地放置时钟组件以便在性能约束内最小化时钟功率的技术。创建矩形网格，并将时钟分配结构分配给网格交点。然后锁存器位于时钟分布结构周围，以最小化锁存器和相应时钟分配结构之间的连接的总距离。可以独立地调整网格的水平和垂直间距以实现时钟分配结构的更均匀的扩展。

29. 发明授权

US07890905B2 Slew constrained minimum cost buffering 有权
标题翻译：压缩约束最低成本缓冲
公开(公告)号：US07890905B2
公开(公告)日：2011-02-15
申请号：US12168153
申请日：2008-07-06
申请人： Charles J. Alpert , Arvind K. Karandikar , Tuhin Mahmud , Stephen T. Quay , Chin Ngai Sze
发明人： Charles J. Alpert , Arvind K. Karandikar , Tuhin Mahmud , Stephen T. Quay , Chin Ngai Sze
IPC分类号： G06F17/50 , G06F9/45
CPC分类号： G06F17/5045
摘要： A buffer insertion technique addresses slew constraints while minimizing buffer cost. The method builds initial solutions for the sinks, each having an associated cost, slew and capacitance. As a solution propagates toward a source, wire capacitance and wire slew are added to the solution. When a buffer is selected for possible insertion, the slew of the solution is set to zero while the cost of the solution is incremented based on the selected buffer and the capacitance is set to an intrinsic capacitance of the buffer. The solutions of two intersecting wire branches are merged by adding branch capacitances and costs, and selecting the highest branch slew. The solution sets are updated by disregarding solutions which have a slew component greater than a slew constraint, and any solution that is dominated by another solution is eliminated. The solution having the smallest cost is selected as the final solution.
摘要翻译：缓冲插入技术解决了压摆约束，同时最大限度地减少了缓冲区成本。该方法构建了汇的初始解决方案，每个都具有相关的成本，压摆和电容。当解决方案向源传播时，将线电容和线压力加到解决方案中。当选择缓冲器进行可能的插入时，将解决方案的电压设置为零，同时根据所选择的缓冲器增加解决方案的成本，并将电容设置为缓冲器的固有电容。通过增加分支电容和成本，并选择最高的分支电压，合并两条相交线分支的解决方案。解决方案集通过忽略具有大于压摆约束的转矩分量的解决方案来更新，并且消除由另一解决方案主导的任何解决方案。选择具有最小成本的解决方案作为最终解决方案。

30. 发明申请

US20090193376A1 CLOCK POWER MINIMIZATION WITH REGULAR PHYSICAL PLACEMENT OF CLOCK REPEATER COMPONENTS 失效
标题翻译：时钟功率最小化与定时重放组件的正常放置
公开(公告)号：US20090193376A1
公开(公告)日：2009-07-30
申请号：US12022849
申请日：2008-01-30
申请人： Charles J. Alpert , Ruchir Puri , Shyam Ramji , Ashish K. Singh , Chin Ngai Sze
发明人： Charles J. Alpert , Ruchir Puri , Shyam Ramji , Ashish K. Singh , Chin Ngai Sze
IPC分类号： G06F17/50
CPC分类号： G06F17/5077 , G06F2217/62
摘要： Power, routability and electromigration have become crucial issues in modem microprocessor designs. In high performance designs, clocks are the highest consumer of power. Arranging clocking components with regularity so as to minimize the capacitance on the clock nets can help reduce clock power, however, it may hurt performance due to some loss of flexibility in physically placing those components. The present invention provides techniques to optimally place clock components in a regular fashion so as to minimize clock power within a performance constraint. A rectangular grid is created and clock distribution structures are assigned to the grid intersection points. Latches are then located around the clock distribution structures to minimize an overall distance for connections between the latches and respective clock distribution structures. The horizontal and vertical pitches of the grid may be independently adjusted to achieve a more uniform spread of the clock distribution structures.
摘要翻译：电源，路由和电迁移已成为现代微处理器设计中的关键问题。在高性能设计中，时钟是功耗最大的消费者。排列时钟元件的规律性，以便最小化时钟网络上的电容可以帮助降低时钟功率，但是，由于物理放置这些组件的一些灵活性可能会损害性能。本发明提供了以规则方式最佳地放置时钟组件以便在性能约束内最小化时钟功率的技术。创建矩形网格，并将时钟分配结构分配给网格交点。然后锁存器位于时钟分布结构周围，以最小化锁存器和相应时钟分配结构之间的连接的总距离。可以独立地调整网格的水平和垂直间距以实现时钟分配结构的更均匀的扩展。

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