专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

21. 发明授权

US06277764B1 Interlayered dielectric layer of semiconductor device and method of manufacturing the same 有权
标题翻译：半导体器件的层间绝缘层及其制造方法
公开(公告)号：US06277764B1
公开(公告)日：2001-08-21
申请号：US09224560
申请日：1998-12-30
申请人： Hong-jae Shin , Hee-sook Park , Sung-jin Kim
发明人： Hong-jae Shin , Hee-sook Park , Sung-jin Kim
IPC分类号： H01L2131
CPC分类号： H01L21/02131 , H01L21/02134 , H01L21/022 , H01L21/02211 , H01L21/02274 , H01L21/02282 , H01L21/31053 , H01L21/3124 , H01L21/3127 , H01L21/314 , H01L21/31629 , H01L21/76801 , H01L21/76835 , H01L21/76837
摘要： A method of forming an interlayer dielectric layer of a semiconductor device and an interlayer dielectric layer using the same. By the method, a semiconductor substrate formed metal interconnect lines thereon is provided, a first insulating layer of a low dielectric material is formed on the semiconductor substrate, by a spin coating, and a second insulating layer of a low dielectric material is formed on the first insulating layer, by the high density plasma chemical vapor deposition (CVD). The second insulating layer is planarized through a chemical mechanical polishing (CMP) process.
摘要翻译：一种形成半导体器件的层间电介质层的方法和使用其的层间电介质层。通过该方法，在其上形成有金属互连线的半导体衬底，通过旋涂在半导体衬底上形成低介电材料的第一绝缘层，并且在第二绝缘层上形成低电介质材料的第二绝缘层第一绝缘层，通过高密度等离子体化学气相沉积（CVD）。通过化学机械抛光（CMP）工艺对第二绝缘层进行平面化处理。

22. 发明申请

US20070221998A1 Semiconductor integrated circuit device and related method 有权
标题翻译：半导体集成电路器件及相关方法
公开(公告)号：US20070221998A1
公开(公告)日：2007-09-27
申请号：US11723725
申请日：2007-03-21
申请人： Hee-sook Park
发明人： Hee-sook Park
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L27/105 , H01L27/1052 , H01L29/66628
摘要： Embodiments of the invention provide a semiconductor integrated circuit device and a method for fabricating the device. In one embodiment, the method comprises forming a plurality of preliminary gate electrode structures in a cell array region and a peripheral circuit region of a semiconductor substrate; forming selective epitaxial films on the semiconductor substrate in the cell array region and the peripheral region; implanting impurities into at least some of the selective epitaxial films to form elevated source/drain regions in the cell array region and the peripheral circuit region; forming a first interlayer insulating film; and patterning the first interlayer insulating film to form a plurality of first openings exposing the elevated source/drain regions. The method further comprises forming a first ohmic film, a first barrier film, and a metal film; and removing portions of each of the metal film, the first barrier film, and the first ohmic film.
摘要翻译：本发明的实施例提供一种半导体集成电路器件及其制造方法。在一个实施例中，该方法包括在半导体衬底的单元阵列区域和外围电路区域中形成多个预选栅电极结构; 在电池阵列区域和外围区域中的半导体衬底上形成选择性外延膜; 将杂质注入到至少一些选择性外延膜中以在电池阵列区域和外围电路区域中形成升高的源极/漏极区域; 形成第一层间绝缘膜; 以及图案化所述第一层间绝缘膜以形成暴露所述升高的源极/漏极区域的多个第一开口。该方法还包括形成第一欧姆膜，第一阻挡膜和金属膜; 以及去除金属膜，第一阻挡膜和第一欧姆膜中的每一个的部分。

23. 发明授权

US06485815B1 Multi-layered dielectric layer including insulating layer having Si-CH3 bond therein and method for fabricating the same 有权
标题翻译：包含其中具有Si-CH3键的绝缘层的多层电介质层及其制造方法
公开(公告)号：US06485815B1
公开(公告)日：2002-11-26
申请号：US09577075
申请日：2000-05-23
申请人： Hyun-dam Jeong , Hee-sook Park , Hong-jae Shin , Byeong-jun Kim
发明人： Hyun-dam Jeong , Hee-sook Park , Hong-jae Shin , Byeong-jun Kim
IPC分类号： B32B2700
CPC分类号： H01L23/53295 , C04B35/5603 , C04B35/565 , H01L21/02137 , H01L21/0214 , H01L21/02282 , H01L21/02332 , H01L21/0234 , H01L21/02362 , H01L21/3122 , H01L21/76801 , H01L21/76826 , H01L21/76829 , H01L21/76835 , H01L23/5222 , H01L23/5226 , H01L23/5329 , H01L2924/0002 , Y10T428/24843 , Y10T428/24926 , Y10T428/263 , Y10T428/31663 , H01L2924/00
摘要： A multi-layered dielectric layer wherein the adhesion characteristic of an insulating layer including a Si—CH3 bond is improved, and a method of forming the same are provided. The multi-layered dielectric layer is formed on conductive patterns and includes a first insulating layer formed of a layer having a low dielectric constant including the Si—CH3 bond. In order to improve the adhesion characteristic of the first insulating layer, an adhesion surface is formed on the surface of the first insulating layer by treating the first insulating layer with plasma. In an alternative, the adhesion characteristics of the first insulating layer is improved by forming a buffer layer on the first insulating layer so that dipole-dipole interaction occurs between the first insulating layer and the buffer layer.
摘要翻译：提供了包括Si-CH 3键的绝缘层的粘合特性的多层电介质层，并且提供了其形成方法。多层电介质层形成在导电图案上，并且包括由具有包含Si-CH3键的低介电常数的层形成的第一绝缘层。为了改善第一绝缘层的附着特性，通过用等离子体处理第一绝缘层，在第一绝缘层的表面上形成粘合表面。或者，通过在第一绝缘层上形成缓冲层，在第一绝缘层和缓冲层之间产生偶极 - 偶极相互作用，来提高第一绝缘层的粘合特性。

24. 发明授权

US07956464B2 Sputtering target and semiconductor device manufactured using the same 失效
标题翻译：溅射靶和使用其制造的半导体器件
公开(公告)号：US07956464B2
公开(公告)日：2011-06-07
申请号：US12573437
申请日：2009-10-05
申请人： Taek-jung Kim , Hee-sook Park , Jong-min Back , Su-kyoung Kim , Yu-gyun Shin , Sun-ghil Lee
发明人： Taek-jung Kim , Hee-sook Park , Jong-min Back , Su-kyoung Kim , Yu-gyun Shin , Sun-ghil Lee
IPC分类号： H01L23/532
CPC分类号： H01L23/53266 , C23C14/185 , C23C14/3414 , H01L21/28088 , H01L2924/0002 , H01L2924/00
摘要： A sputtering target includes a tungsten (W)-nickel (Ni) alloy, wherein the nickel (Ni) is present in an amount of between about 0.01 weight % and about 1 weight %.
摘要翻译：溅射靶包括钨（W） - 镍（Ni）合金，其中镍（Ni）的存在量为约0.01重量％至约1重量％。

25. 发明授权

US06573147B2 Method of forming a semiconductor device having contact using crack-protecting layer 有权
标题翻译：使用裂纹保护层形成具有接触的半导体器件的方法
公开(公告)号：US06573147B2
公开(公告)日：2003-06-03
申请号：US10055260
申请日：2001-10-26
申请人： Kwang-jin Moon , Hee-sook Park , Myoung-bum Lee
发明人： Kwang-jin Moon , Hee-sook Park , Myoung-bum Lee
IPC分类号： H01L21331
CPC分类号： H01L21/76829 , H01L21/32051
摘要： A semiconductor device having a contact using a crack-protecting layer and a method of forming the same are provided. The crack-protecting layer formed of a dielectric material is formed on an interlayer dielectric layer. The crack-protecting layer relieves or absorbs residual stress generated on a conductive layer used in forming a contact plug. Thus, a contact can be formed without damage to the interlayer dielectric layer due to residual stress.
摘要翻译：提供具有使用裂纹保护层的接触的半导体器件及其形成方法。由介电材料形成的裂纹保护层形成在层间电介质层上。裂纹保护层减轻或吸收在用于形成接触插塞的导电层上产生的残余应力。因此，可以形成接触，而不会由于残余应力而损坏层间电介质层。

26. 发明授权

US06777322B2 Method for fabricating a multi-layered dielectric layer including insulating layer having Si-CH3 bond therein 有权
标题翻译：用于制造包含其中具有Si-CH 3键的绝缘层的多层电介质层的方法
公开(公告)号：US06777322B2
公开(公告)日：2004-08-17
申请号：US10255639
申请日：2002-09-27
申请人： Hyun-dam Jeong , Hee-sook Park , Hong-jae Shin , Byeong-jun Kim
发明人： Hyun-dam Jeong , Hee-sook Park , Hong-jae Shin , Byeong-jun Kim
IPC分类号： H01L214763
CPC分类号： H01L23/53295 , C04B35/5603 , C04B35/565 , H01L21/02137 , H01L21/0214 , H01L21/02282 , H01L21/02332 , H01L21/0234 , H01L21/02362 , H01L21/3122 , H01L21/76801 , H01L21/76826 , H01L21/76829 , H01L21/76835 , H01L23/5222 , H01L23/5226 , H01L23/5329 , H01L2924/0002 , Y10T428/24843 , Y10T428/24926 , Y10T428/263 , Y10T428/31663 , H01L2924/00
摘要： A multi-layered dielectric layer wherein the adhesion characteristic of an insulating layer including a Si—CH3 bond is improved, and a method of forming the same are provided. The multi-layered dielectric layer is formed on conductive patterns and includes a first insulating layer formed of a layer having a low dielectric constant including the Si—CH3 bond. In order to improve the adhesion characteristic of the first insulating layer, an adhesion surface is formed on the surface of the first insulating layer by treating the first insulating layer with plasma. In an alternative, the adhesion characteristics of the first insulating layer is improved by forming a buffer layer on the first insulating layer so that dipole—dipole interaction occurs between the first insulating layer and the buffer layer.
摘要翻译：提供了包括Si-CH 3键的绝缘层的粘合特性的多层电介质层，并且提供了其形成方法。多层电介质层形成在导电图案上，并且包括由具有包含Si-CH3键的低介电常数的层形成的第一绝缘层。为了改善第一绝缘层的附着特性，通过用等离子体处理第一绝缘层，在第一绝缘层的表面上形成粘合表面。或者，通过在第一绝缘层上形成缓冲层，在第一绝缘层和缓冲层之间产生偶极 - 偶极相互作用，来提高第一绝缘层的粘合特性。

27. 发明授权

US07879707B2 Semiconductor integrated circuit device and related method 有权
标题翻译：半导体集成电路器件及相关方法
公开(公告)号：US07879707B2
公开(公告)日：2011-02-01
申请号：US12754766
申请日：2010-04-06
申请人： Hee-sook Park
发明人： Hee-sook Park
IPC分类号： H01L21/00
CPC分类号： H01L27/105 , H01L27/1052 , H01L29/66628
摘要： Embodiments of the invention provide a semiconductor integrated circuit device and a method for fabricating the device. In one embodiment, the method comprises forming a plurality of preliminary gate electrode structures in a cell array region and a peripheral circuit region of a semiconductor substrate; forming selective epitaxial films on the semiconductor substrate in the cell array region and the peripheral region; implanting impurities into at least some of the selective epitaxial films to form elevated source/drain regions in the cell array region and the peripheral circuit region; forming a first interlayer insulating film; and patterning the first interlayer insulating film to form a plurality of first openings exposing the elevated source/drain regions. The method further comprises forming a first ohmic film, a first barrier film, and a metal film; and removing portions of each of the metal film, the first barrier film, and the first ohmic film.
摘要翻译：本发明的实施例提供一种半导体集成电路器件及其制造方法。在一个实施例中，该方法包括在半导体衬底的单元阵列区域和外围电路区域中形成多个预选栅电极结构; 在电池阵列区域和外围区域中的半导体衬底上形成选择性外延膜; 将杂质注入到至少一些选择性外延膜中以在电池阵列区域和外围电路区域中形成升高的源极/漏极区域; 形成第一层间绝缘膜; 以及图案化所述第一层间绝缘膜以形成暴露所述升高的源极/漏极区域的多个第一开口。该方法还包括形成第一欧姆膜，第一阻挡膜和金属膜; 以及去除金属膜，第一阻挡膜和第一欧姆膜中的每一个的部分。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式