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21. 发明授权

US07742118B2 Thin film transistor array panel and manufacturing method thereof 有权
标题翻译：薄膜晶体管阵列面板及其制造方法
公开(公告)号：US07742118B2
公开(公告)日：2010-06-22
申请号：US11690563
申请日：2007-03-23
申请人： Jun-Hyung Souk , Jeong-Young Lee , Jong-Soo Yoon , Kwon-Young Choi , Bum-Ki Baek
发明人： Jun-Hyung Souk , Jeong-Young Lee , Jong-Soo Yoon , Kwon-Young Choi , Bum-Ki Baek
IPC分类号： G02F1/136
CPC分类号： G02F1/13458 , G02F1/136227 , G02F1/136286 , H01L27/12 , H01L27/124 , H01L27/1288
摘要： A method of manufacturing a thin film transistor array panel is provided, the method includes: forming a gate line on an insulating substrate; forming a gate insulating layer; forming a semiconductor layer; forming a data conductive layer including a data line and a drain electrode; depositing a passivation layer; forming a photoresist including a first portion located on an end portion of the gate line, a second portion thicker than the first portion and located on the drain electrode, and a third portion thicker than the second portion; exposing a portion of the passivation layer under the second portion of the photoresist and a portion of the gate insulating layer under the first portion of the photoresist by etching using the photoresist as an etch mask; forming first and second contact holes exposing the drain electrode and the end portions of the gate line, respectively; and forming a pixel electrode connected to the drain electrode through the first contact hole.
摘要翻译：提供一种制造薄膜晶体管阵列面板的方法，该方法包括：在绝缘基板上形成栅极线; 形成栅极绝缘层; 形成半导体层; 形成包括数据线和漏电极的数据导电层; 沉积钝化层; 形成包括位于所述栅极线的端部的第一部分的光致抗蚀剂，比所述第一部分更厚且位于所述漏极上的第二部分，以及比所述第二部分更厚的第三部分; 通过使用光致抗蚀剂作为蚀刻掩模，将光致抗蚀剂的第二部分下的钝化层的一部分暴露在光致抗蚀剂的第一部分下方的栅绝缘层的一部分; 形成分别露出所述漏电极和所述栅极线的端部的第一和第二接触孔; 以及通过所述第一接触孔形成连接到所述漏电极的像素电极。

22. 发明申请

US20100096176A1 CONTACT STRUCTURE OF A WIRES AND METHOD MANUFACTURING THE SAME, AND THIN FILM TRANSISTOR SUBSTRATE INCLUDING THE CONTACT STRUCTURE AND METHOD MANUFACTURING THE SAME 审中-公开
标题翻译：一种线的接触结构及其制造方法，以及包括接触结构的薄膜晶体管基板及其制造方法
公开(公告)号：US20100096176A1
公开(公告)日：2010-04-22
申请号：US12645458
申请日：2009-12-22
申请人： Seung-Taek LIM , Mun-Pyo Hong , Nam-Seok Roh , Young-Joo Song , Sang-Ki Kwak , Kwon-Young Choi , Keun-Kyu Song
发明人： Seung-Taek LIM , Mun-Pyo Hong , Nam-Seok Roh , Young-Joo Song , Sang-Ki Kwak , Kwon-Young Choi , Keun-Kyu Song
IPC分类号： H05K1/11
CPC分类号： G02F1/13458 , G02F1/136227 , G02F1/136286 , G02F2001/13629 , H01L21/76805 , H01L21/76816 , H01L23/53223 , H01L27/124 , H01L2924/0002 , H01L2924/00
摘要： In a method of fabricating a thin film transistor array substrate for a liquid crystal display, a gate line assembly is formed on a substrate with a chrome-based under-layer and an aluminum alloy-based over-layer while proceeding in the horizontal direction. The gate line assembly has gate lines, and gate electrodes, and gate pads. A gate insulating layer is deposited onto the insulating substrate such that the gate insulating layer covers the gate line assembly. A semiconductor layer and an ohmic contact layer are sequentially formed on the gate insulating layer. A data line assembly is formed on the ohmic contact layer with a chrome-based under-layer and an aluminum alloy-based over-layer. The data line assembly has data lines crossing over the gate lines, source electrodes, drain electrodes, and data pads. A protective layer is deposited onto the substrate, and patterned to thereby form contact holes exposing the drain electrodes, the gate pads, and the data pads. The sidewall of the under-layers for the gate line assembly and the data line assembly is exposed through the contact holes. An IZO-based layer is deposited onto the substrate, and patterned to thereby form pixel electrodes, subsidiary gate pads, and subsidiary data pads. The pixel electrodes are connected to the sidewall of the drain electrodes, and the subsidiary gate and data pads are connected to the sidewall of the gate and the data pads.
摘要翻译：在制造用于液晶显示器的薄膜晶体管阵列基板的方法中，栅极线组件在沿水平方向前进的基底上形成有铬基底层和基于铝合金的超层。栅极线组件具有栅极线，栅电极和栅极焊盘。栅极绝缘层沉积在绝缘基板上，使得栅极绝缘层覆盖栅极线组件。在栅极绝缘层上依次形成半导体层和欧姆接触层。数据线组件在欧姆接触层上形成有铬基底层和基于铝合金的超层。数据线组件具有跨越栅极线，源电极，漏电极和数据焊盘的数据线。保护层沉积到衬底上，并被图案化，从而形成露出漏电极，栅极焊盘和数据焊盘的接触孔。用于栅极线组件和数据线组件的下层的侧壁通过接触孔暴露。将基于IZO的层沉积到衬底上并构图，从而形成像素电极，辅助栅极焊盘和辅助数据焊盘。像素电极连接到漏电极的侧壁，辅助栅极和数据焊盘连接到栅极和数据焊盘的侧壁。

23. 发明申请

US20090096105A1 CONTACT STRUCTURE OF A WIRES AND METHOD MANUFACTURING THE SAME, AND THIN FILM TRANSISTOR SUBSTRATE INCLUDING THE CONTACT STRUCTURE AND METHOD MANUFACTURING THE SAME 有权
标题翻译：一种线的接触结构及其制造方法，以及包括接触结构的薄膜晶体管基板及其制造方法
公开(公告)号：US20090096105A1
公开(公告)日：2009-04-16
申请号：US12333973
申请日：2008-12-12
申请人： Seung-Taek LIM , Mun-Pyo Hong , Nam-Seok Roh , Young-Joo Song , Sang-Ki Kwak , Kwon-Young Choi , Keun-Kyu Song
发明人： Seung-Taek LIM , Mun-Pyo Hong , Nam-Seok Roh , Young-Joo Song , Sang-Ki Kwak , Kwon-Young Choi , Keun-Kyu Song
IPC分类号： H01L23/48 , H01L23/52
CPC分类号： G02F1/13458 , G02F1/136227 , G02F1/136286 , G02F2001/13629 , H01L21/76805 , H01L21/76816 , H01L23/53223 , H01L27/124 , H01L2924/0002 , H01L2924/00
摘要： In a method of fabricating a thin film transistor array substrate for a liquid crystal display, a gate line assembly is formed on a substrate with a chrome-based under-layer and an aluminum alloy-based over-layer while proceeding in the horizontal direction. The gate line assembly has gate lines, and gate electrodes, and gate pads. A gate insulating layer is deposited onto the insulating substrate such that the gate insulating layer covers the gate line assembly. A semiconductor layer and an ohmic contact layer are sequentially formed on the gate insulating layer. A data line assembly is formed on the ohmic contact layer with a chrome-based under-layer and an aluminum alloy-based over-layer. The data line assembly has data lines crossing over the gate lines, source electrodes, drain electrodes, and data pads. A protective layer is deposited onto the substrate, and patterned to thereby form contact holes exposing the drain electrodes, the gate pads, and the data pads. The sidewall of the under-layers for the gate line assembly and the data line assembly is exposed through the contact holes. An IZO-based layer is deposited onto the substrate, and patterned to thereby form pixel electrodes, subsidiary gate pads, and subsidiary data pads. The pixel electrodes are connected to the sidewall of the drain electrodes, and the subsidiary gate and data pads are connected to the sidewall of the gate and the data pads.
摘要翻译：在制造用于液晶显示器的薄膜晶体管阵列基板的方法中，栅极线组件在沿水平方向前进的基底上形成有铬基底层和基于铝合金的超层。栅极线组件具有栅极线，栅电极和栅极焊盘。栅极绝缘层沉积在绝缘基板上，使得栅极绝缘层覆盖栅极线组件。在栅极绝缘层上依次形成半导体层和欧姆接触层。数据线组件在欧姆接触层上形成有铬基底层和基于铝合金的超层。数据线组件具有跨越栅极线，源电极，漏电极和数据焊盘的数据线。保护层沉积到衬底上，并被图案化，从而形成露出漏电极，栅极焊盘和数据焊盘的接触孔。用于栅极线组件和数据线组件的下层的侧壁通过接触孔暴露。将基于IZO的层沉积到衬底上并构图，从而形成像素电极，辅助栅极焊盘和辅助数据焊盘。像素电极连接到漏电极的侧壁，辅助栅极和数据焊盘连接到栅极和数据焊盘的侧壁。

24. 发明申请

US20080252806A1 THIN FILM TRANSISTOR ARRAY PANEL AND MANUFACTURING METHOD THEREOF 有权
标题翻译：薄膜晶体管阵列及其制造方法
公开(公告)号：US20080252806A1
公开(公告)日：2008-10-16
申请号：US12141623
申请日：2008-06-18
申请人： Jun-Hyung SOUK , Jeong-Young Lee , Jong-Soo Yoon , Kwon-Young Choi , Bum-Ki Baek
发明人： Jun-Hyung SOUK , Jeong-Young Lee , Jong-Soo Yoon , Kwon-Young Choi , Bum-Ki Baek
IPC分类号： G02F1/136
CPC分类号： G02F1/13458 , G02F1/136227 , G02F1/136286 , H01L27/12 , H01L27/124 , H01L27/1288
摘要： A method of manufacturing a thin film transistor array panel is provided, the method includes: forming a gate line on an insulating substrate; forming a gate insulating layer; forming a semiconductor layer; forming a data conductive layer including a data line and a drain electrode; depositing a passivation layer; forming a photoresist including a first portion located on an end portion of the gate line, a second portion thicker than the first portion and located on the drain electrode, and a third portion thicker than the second portion; exposing a portion of the passivation layer under the second portion of the photoresist and a portion of the gate insulating layer under the first portion of the photoresist by etching using the photoresist as an etch mask; forming first and second contact holes exposing the drain electrode and the end portions of the gate line, respectively; and forming a pixel electrode connected to the drain electrode through the first contact hole.
摘要翻译：提供一种制造薄膜晶体管阵列面板的方法，该方法包括：在绝缘基板上形成栅极线; 形成栅极绝缘层; 形成半导体层; 形成包括数据线和漏电极的数据导电层; 沉积钝化层; 形成包括位于所述栅极线的端部的第一部分的光致抗蚀剂，比所述第一部分更厚且位于所述漏极上的第二部分，以及比所述第二部分更厚的第三部分; 通过使用光致抗蚀剂作为蚀刻掩模，将光致抗蚀剂的第二部分下的钝化层的一部分暴露在光致抗蚀剂的第一部分下方的栅绝缘层的一部分; 形成分别露出所述漏电极和所述栅极线的端部的第一和第二接触孔; 以及通过所述第一接触孔形成连接到所述漏电极的像素电极。

25. 发明授权

US07403240B2 Thin film transistor array panel and manufacturing method thereof 有权
标题翻译：薄膜晶体管阵列面板及其制造方法
公开(公告)号：US07403240B2
公开(公告)日：2008-07-22
申请号：US11741470
申请日：2007-04-27
申请人： Jun-Hyung Souk , Jeong-Young Lee , Jong-Soo Yoon , Kwon-Young Choi , Bum-Ki Baek
发明人： Jun-Hyung Souk , Jeong-Young Lee , Jong-Soo Yoon , Kwon-Young Choi , Bum-Ki Baek
IPC分类号： G02F1/136 , G02F1/1335
CPC分类号： G02F1/13458 , G02F1/136227 , G02F1/136286 , H01L27/12 , H01L27/124 , H01L27/1288
摘要： A method of manufacturing a thin film transistor array panel is provided, the method includes: forming a gate line on an insulating substrate; forming a gate insulating layer; forming a semiconductor layer; forming a data conductive layer including a data line and a drain electrode; depositing a passivation layer; forming a photoresist including a first portion located on an end portion of the gate line, a second portion thicker than the first portion and located on the drain electrode, and a third portion thicker than the second portion; exposing a portion of the passivation layer under the second portion of the photoresist and a portion of the gate insulating layer under the first portion of the photoresist by etching using the photoresist as an etch mask; forming first and second contact holes exposing the drain electrode and the end portions of the gate line, respectively; and forming a pixel electrode connected to the drain electrode through the first contact hole.
摘要翻译：提供一种制造薄膜晶体管阵列面板的方法，该方法包括：在绝缘基板上形成栅极线; 形成栅极绝缘层; 形成半导体层; 形成包括数据线和漏电极的数据导电层; 沉积钝化层; 形成包括位于所述栅极线的端部的第一部分的光致抗蚀剂，比所述第一部分更厚且位于所述漏极上的第二部分，以及比所述第二部分更厚的第三部分; 通过使用光致抗蚀剂作为蚀刻掩模，将光致抗蚀剂的第二部分下的钝化层的一部分暴露在光致抗蚀剂的第一部分下方的栅绝缘层的一部分; 形成分别露出所述漏电极和所述栅极线的端部的第一和第二接触孔; 以及通过所述第一接触孔形成连接到所述漏电极的像素电极。

26. 发明授权

US07294855B2 Contact structure of semiconductor device, manufacturing method thereof, thin film transistor array panel including contact structure, and manufacturing method thereof 失效
标题翻译：半导体器件的接触结构，其制造方法，包括接触结构的薄膜晶体管阵列面板及其制造方法
公开(公告)号：US07294855B2
公开(公告)日：2007-11-13
申请号：US10653556
申请日：2003-09-02
申请人： Bum-Gee Baek , Kwon-Young Choi , Young-Joon Rhee , Bong-Joo Kang , Seung-Taek Lim , Hyang-Shik Kong , Won-Joo Kim
发明人： Bum-Gee Baek , Kwon-Young Choi , Young-Joon Rhee , Bong-Joo Kang , Seung-Taek Lim , Hyang-Shik Kong , Won-Joo Kim
IPC分类号： H01L29/04
CPC分类号： G02F1/13458 , G02F1/13439 , G02F1/136227 , G02F1/136286 , G02F2001/136236 , G02F2001/13629 , H01L27/12 , H01L27/124 , H01L27/1288 , H01L29/41733 , H01L29/42384 , H01L29/4908
摘要： Gate lines are formed on a substrate. A gate insulating layer, an intrinsic a-Si layer, an extrinsic a-Si layer, a lower film of Cr and an upper film of Al containing metal are sequentially deposited. A photoresist having thicker first portions on wire areas and thinner second portions on channel areas is formed on the upper film. The upper film on remaining areas are wet-etched, and the lower film and the a-Si layers on the remaining areas are dry-etched along with the second portions of the photoresist. The upper film, the lower film, and the extrinsic a-Si layer on the channel areas are removed. The removal of the upper film and the lower film on the channel areas are performed by wet etching, and the first portions of the photoresist are removed after the removal of the upper film on the channel areas.
摘要翻译：栅极线形成在基板上。依次沉积栅极绝缘层，本征a-Si层，外部a-Si层，下部Cr膜和含Al金属的上部膜。在上部膜上形成具有较粗的第一部分在导线区域上的光刻胶和在沟道区域上较薄的第二部分的光致抗蚀剂。在其余区域上的上部膜被湿式蚀刻，并且其余区域上的下部膜和a-Si层与光致抗蚀剂的第二部分一起被干蚀刻。除去沟道区上的上膜，下膜和非本征a-Si层。通过湿蚀刻来进行通道区域上的上膜和下膜的去除，并且在去除沟道区上的上膜之后去除光致抗蚀剂的第一部分。

27. 发明申请

US20070200981A1 Thin Film Transistor Array Panel and Manufacturing Method Thereof 有权
标题翻译：薄膜晶体管阵列面板及其制造方法
公开(公告)号：US20070200981A1
公开(公告)日：2007-08-30
申请号：US11741470
申请日：2007-04-27
申请人： Jun-Hyung SOUK , Jeong-Young Lee , Jong-Soo Yoon , Kwon-Young Choi , Bum-Ki Baek
发明人： Jun-Hyung SOUK , Jeong-Young Lee , Jong-Soo Yoon , Kwon-Young Choi , Bum-Ki Baek
IPC分类号： G02F1/1335 , G02F1/136
CPC分类号： G02F1/13458 , G02F1/136227 , G02F1/136286 , H01L27/12 , H01L27/124 , H01L27/1288
摘要： A method of manufacturing a thin film transistor array panel is provided, the method includes: forming a gate line on an insulating substrate; forming a gate insulating layer; forming a semiconductor layer; forming a data conductive layer including a data line and a drain electrode; depositing a passivation layer; forming a photoresist including a first portion located on an end portion of the gate line, a second portion thicker than the first portion and located on the drain electrode, and a third portion thicker than the second portion; exposing a portion of the passivation layer under the second portion of the photoresist and a portion of the gate insulating layer under the first portion of the photoresist by etching using the photoresist as an etch mask; forming first and second contact holes exposing the drain electrode and the end portions of the gate line, respectively; and forming a pixel electrode connected to the drain electrode through the first contact hole.
摘要翻译：提供一种制造薄膜晶体管阵列面板的方法，该方法包括：在绝缘基板上形成栅极线; 形成栅极绝缘层; 形成半导体层; 形成包括数据线和漏电极的数据导电层; 沉积钝化层; 形成包括位于所述栅极线的端部的第一部分的光致抗蚀剂，比所述第一部分更厚且位于所述漏极上的第二部分，以及比所述第二部分更厚的第三部分; 通过使用光致抗蚀剂作为蚀刻掩模，将光致抗蚀剂的第二部分下的钝化层的一部分暴露在光致抗蚀剂的第一部分下方的栅绝缘层的一部分; 形成分别露出所述漏电极和所述栅极线的端部的第一和第二接触孔; 以及通过所述第一接触孔形成连接到所述漏电极的像素电极。

28. 发明申请

US20070190706A1 Thin Film Transistor Array Panel And Manufacturing Method Thereof 有权
标题翻译：薄膜晶体管阵列面板及其制造方法
公开(公告)号：US20070190706A1
公开(公告)日：2007-08-16
申请号：US11690563
申请日：2007-03-23
申请人： Jun-Hyung Souk , Jeong-Young Lee , Jong-Soo Yoon , Kwon-Young Choi , Bum-Ki Baek
发明人： Jun-Hyung Souk , Jeong-Young Lee , Jong-Soo Yoon , Kwon-Young Choi , Bum-Ki Baek
IPC分类号： H01L21/84
CPC分类号： G02F1/13458 , G02F1/136227 , G02F1/136286 , H01L27/12 , H01L27/124 , H01L27/1288
摘要： A method of manufacturing a thin film transistor array panel is provided, the method includes: forming a gate line on an insulating substrate; forming a gate insulating layer; forming a semiconductor layer; forming a data conductive layer including a data line and a drain electrode; depositing a passivation layer; forming a photoresist including a first portion located on an end portion of the gate line, a second portion thicker than the first portion and located on the drain electrode, and a third portion thicker than the second portion; exposing a portion of the passivation layer under the second portion of the photoresist and a portion of the gate insulating layer under the first portion of the photoresist by etching using the photoresist as an etch mask; forming first and second contact holes exposing the drain electrode and the end portions of the gate line, respectively; and forming a pixel electrode connected to the drain electrode through the first contact hole.
摘要翻译：提供一种制造薄膜晶体管阵列面板的方法，该方法包括：在绝缘基板上形成栅极线; 形成栅极绝缘层; 形成半导体层; 形成包括数据线和漏电极的数据导电层; 沉积钝化层; 形成包括位于所述栅极线的端部的第一部分的光致抗蚀剂，比所述第一部分更厚且位于所述漏极上的第二部分，以及比所述第二部分更厚的第三部分; 通过使用光致抗蚀剂作为蚀刻掩模，将光致抗蚀剂的第二部分下的钝化层的一部分暴露在光致抗蚀剂的第一部分下方的栅绝缘层的一部分; 形成分别露出所述漏电极和所述栅极线的端部的第一和第二接触孔; 以及通过所述第一接触孔形成连接到所述漏电极的像素电极。

29. 发明授权

US07142279B2 Divisionally exposing an active area in LCD with a plurality of shots 有权
标题翻译：在LCD中分开曝光多个镜头
公开(公告)号：US07142279B2
公开(公告)日：2006-11-28
申请号：US10469197
申请日：2002-09-18
申请人： Young-Mi Tak , Woon-Yong Park , Kwon-Young Choi , Myung-Jae Park
发明人： Young-Mi Tak , Woon-Yong Park , Kwon-Young Choi , Myung-Jae Park
IPC分类号： G02F1/13
CPC分类号： G02F1/1362 , G02F2001/13625
摘要： In a method of manufacturing a liquid crystal display using a divisional exposure for a substrate, an overlapping area at the boundary between adjacent shots is provided and the shots left and right to the boundary are exposed in a way that the areas of the shots gradually decreases and gradually increases, respectively, to reduce the brightness difference due to stitch errors between the two shots. For example, the number of unit stitch areas assigned to the left gradually decreases and the number of unit stitch areas assigned to the right shot gradually increases as it goes to the right along the transverse direction in the stitch area. A unit stitch includes an area obtained by dividing a pixel into at least two parts.
摘要翻译：在使用基板的分割曝光来制造液晶显示器的方法中，提供相邻镜头之间的边界处的重叠区域，并且以边界的区域逐渐减小到边界的左右的镜头并分别逐渐增加，以减少由于两次拍摄之间的针迹误差引起的亮度差异。例如，分配给左侧的单位针迹区域的数量逐渐减少，并且分配给右侧拍摄的单位针迹区域的数量随着在针迹区域中的横向方向上的向右逐渐增加。单位线圈包括通过将像素划分为至少两部分而获得的区域。

30. 发明授权

US07119368B2 Thin film transistor array panel and manufacturing method thereof 有权
公开(公告)号：US07119368B2
公开(公告)日：2006-10-10
申请号：US10926719
申请日：2004-08-26
申请人： Min-Wook Park , Sang-Jin Jeon , Jung-Joon Park , Jeong-Young Lee , Bum-Ki Baek , Se-Hwan Yu , Sang-Ki Kwak , Han-Ju Lee , Kwon-Young Choi
发明人： Min-Wook Park , Sang-Jin Jeon , Jung-Joon Park , Jeong-Young Lee , Bum-Ki Baek , Se-Hwan Yu , Sang-Ki Kwak , Han-Ju Lee , Kwon-Young Choi
IPC分类号： H01L31/0376
CPC分类号： G02F1/1368 , G02F1/1339
摘要： A method of manufacturing a thin film transistor array panel is provided, which includes: forming a gate line on a substrate; depositing a gate insulating layer and a semiconductor layer in sequence on the gate line; depositing a lower conductive film and an upper conductive film on the semiconductor layer; photo-etching the upper conductive film, the lower conductive film, and the semiconductor layer; depositing a passivation layer; photo-etching the passivation layer to expose first and second portions of the upper conductive film; removing the first and the second portions of the upper conductive film to expose first and second portions of the lower conductive film; forming a pixel electrode and a pair of redundant electrodes on the first and the second portions of the lower conductive film, respectively, the redundant electrodes exposing a part of the second portion of the lower conductive film; removing the exposed part of the second portion of the lower conductive film to expose a portion of the semiconductor layer; and forming a columnar spacer on the exposed portion of the semiconductor layer.

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