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21. 发明授权

US08190851B2 Resistance variable memory device 有权
标题翻译：电阻变量存储器件
公开(公告)号：US08190851B2
公开(公告)日：2012-05-29
申请号：US12617758
申请日：2009-11-13
申请人： Kwang-jin Lee , Young-kug Moon , Kwang-ho Kim
发明人： Kwang-jin Lee , Young-kug Moon , Kwang-ho Kim
IPC分类号： G06F12/00
CPC分类号： G06F12/0215 , G06F12/0238 , G06F2212/7203 , G11C7/103 , G11C13/0004 , G11C13/004 , Y02D10/13
摘要： A resistance variable memory device includes a resistance variable memory cell array, a data register that prefetches read data of the resistance variable memory cell array, a data output unit that receives the prefetched read data from the data register and outputs the received data, and a page mode setting unit that sets one of a first page mode and a second page mode as a page mode. In the first page mode, the data output unit sequentially reads the read data prefetched in the data register as page addresses are sequentially received, and in the second page mode, the data output unit sequentially reads the read data prefetched in the data register after a start page address among a plurality of page addresses has been received.
摘要翻译：电阻可变存储器件包括电阻可变存储单元阵列，预取电阻可变存储单元阵列的读取数据的数据寄存器，从数据寄存器接收预取的读取数据并输出接收的数据的数据输出单元，以及页面模式设置单元，其将第一页面模式和第二页面模式之一设置为页面模式。在第一页面模式中，数据输出单元顺序地读取在数据寄存器中预取的读取数据，因为顺序地接收页面地址，而在第二页面模式中，数据输出单元顺序地读取在数据寄存器中预读取的读取数据已经接收到多个页地址中的起始页地址。

22. 发明授权

US07974116B2 Variable resistance memory device 有权
标题翻译：可变电阻存储器件
公开(公告)号：US07974116B2
公开(公告)日：2011-07-05
申请号：US12314965
申请日：2008-12-19
申请人： Byung-gil Choi , Kwang-ho Kim
发明人： Byung-gil Choi , Kwang-ho Kim
IPC分类号： G11C11/00
CPC分类号： G11C13/0023 , G11C8/08 , G11C8/14 , G11C13/0004 , G11C13/0028 , G11C13/0038 , G11C2213/72
摘要： A variable resistance memory device includes a variable resistance memory cell array including a plurality of variable resistance memory cells; a plurality of global word lines configured to drive the variable resistance memory cell array; and a plurality of local word line decoders. Each of the plurality of local word line decoders includes a first transistor having a gate connected to the global word line. A voltage greater than an operation voltage of one or more of the plurality of local word line decoders is applied to a selected one of the plurality of global word lines.
摘要翻译：可变电阻存储器件包括：包括多个可变电阻存储单元的可变电阻存储单元阵列; 配置成驱动可变电阻存储单元阵列的多个全局字线; 和多个本地字线解码器。多个本地字线解码器中的每一个包括具有连接到全局字线的栅极的第一晶体管。大于多个本地字线解码器中的一个或多个的操作电压的电压被施加到多个全局字线中的所选择的一个。

23. 发明授权

US07741890B2 Method and apparatus for generating multi-phase signals 有权
标题翻译：用于产生多相信号的方法和装置
公开(公告)号：US07741890B2
公开(公告)日：2010-06-22
申请号：US11873752
申请日：2007-10-17
申请人： Jin-hyuk Jeung , Kwang-ho Kim
发明人： Jin-hyuk Jeung , Kwang-ho Kim
IPC分类号： H03L7/06
CPC分类号： H03L7/0814 , H03L7/093
摘要： A method and apparatus for generating multi-phase clock signals. The multi-phase generating method includes: generating L reference clock signal groups having predetermined phase delay intervals from an external clock signal, wherein each reference clock signal group includes M sub reference clock signals; averaging phases of sub reference clock signals for each reference clock signal group, and generating L main reference clock signals from the L×M sub reference clock signals; and sequentially delaying the L main reference clock signals, and generating the N multi-phase clock signals having the different phases. Because a plurality of clock signals having equal phase delay intervals between each other are generated regardless of the frequency of a received clock signal, the yield of Delay Locked Loop (DLL) circuits is improved using the multi-phase generating apparatus.
摘要翻译：一种用于产生多相时钟信号的方法和装置。多相产生方法包括：从外部时钟信号产生具有预定相位延迟间隔的L个参考时钟信号组，其中每个参考时钟信号组包括M个子参考时钟信号; 对每个参考时钟信号组进行子参考时钟信号的平均相位，并从L×M子参考时钟信号产生L个主参考时钟信号; 并顺序地延迟L个主参考时钟信号，并产生具有不同相位的N个多相时钟信号。由于多个时钟信号彼此之间具有相等的相位延迟间隔而产生，而与收到的时钟信号的频率无关，所以使用多相发生装置来提高延迟锁定环（DLL）电路的产量。

24. 发明申请

US20100124103A1 Resistance-change random access memory device 有权
标题翻译：电阻变化随机存取存储器件
公开(公告)号：US20100124103A1
公开(公告)日：2010-05-20
申请号：US12591238
申请日：2009-11-13
申请人： Hye-jin Kim , Kwang-ho Kim , Young-kug Moon , Byung-gil Choi
发明人： Hye-jin Kim , Kwang-ho Kim , Young-kug Moon , Byung-gil Choi
IPC分类号： G11C11/00 , G11C11/36 , G11C7/00
CPC分类号： G11C13/0023 , G11C7/12 , G11C8/12 , G11C13/00 , G11C13/0004 , G11C13/0026 , G11C13/0028
摘要： A resistance-change random access memory device includes a resistance-change memory cell array having a plurality of resistance-change memory cells, where a plurality of word lines are connected to respective first terminals of the plurality of resistance-change memory cells. A plurality of bit lines are disposed perpendicular to the word lines and connected to respective second terminals of the plurality of resistance-change memory cells. The device also includes a plurality of discharge elements that are capable of connecting or disconnecting respective bit lines from a discharge voltage, where the discharge elements connect the respective bit lines to the discharge voltage before write and read operations.
摘要翻译：电阻变化随机存取存储器件包括具有多个电阻变化存储单元的电阻变化存储单元阵列，其中多个字线连接到多个电阻变化存储单元的相应第一端子。多个位线垂直于字线布置并连接到多个电阻变化存储单元的相应的第二端子。该装置还包括能够将各个位线与放电电压连接或断开的多个放电元件，其中放电元件在写入和读取操作之前将各个位线连接到放电电压。

25. 发明申请

US20100124101A1 PHASE-CHANGE RANDOM ACCESS MEMORY DEVICE 审中-公开
标题翻译：相变随机访问存储器件
公开(公告)号：US20100124101A1
公开(公告)日：2010-05-20
申请号：US12499894
申请日：2009-07-09
申请人： Mu-hui Park , Soo-guil Yang , Kwang-ho Kim
发明人： Mu-hui Park , Soo-guil Yang , Kwang-ho Kim
IPC分类号： G11C11/00 , G11C7/00
CPC分类号： G11C13/004 , G11C7/08 , G11C13/00 , G11C13/0004 , G11C2013/0054
摘要： Provided is a phase-change random access memory device. The phase-change random access memory device includes a phase-change memory cell array having multiple phase-change memory cells, a sensing unit and a discharge unit. The sensing unit detects data, stored in a phase-change memory cell to be sensed of the multiple phase-change memory cells, during a sensing period. The discharge unit discharges at least one node of multiple nodes positioned on a sensing path between the phase-change memory cell array and the sensing unit during a period other than the sensing period.
摘要翻译：提供了相变随机存取存储器件。相变随机存取存储装置包括具有多个相变存储单元的相变存储单元阵列，感测单元和放电单元。感测单元在感测周期期间检测存储在要被感测的多个相变存储器单元的相变存储单元中的数据。放电单元在除了感测周期之外的时段期间放电位于相变存储单元阵列和感测单元之间的感测路径上的多个节点的至少一个节点。

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