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21. 发明申请

US20070049032A1 Protective coating for planarization 有权
标题翻译：用于平坦化的保护涂层
公开(公告)号：US20070049032A1
公开(公告)日：2007-03-01
申请号：US11219604
申请日：2005-09-01
申请人： Mirzafer Abatchev , David Wells , Baosuo Zhou , Krupakar Subramanian
发明人： Mirzafer Abatchev , David Wells , Baosuo Zhou , Krupakar Subramanian
IPC分类号： H01L21/302
CPC分类号： H01L21/31051 , H01L21/0337 , H01L21/306 , H01L21/30625 , H01L21/31055 , H01L21/31111 , H01L21/31144 , Y10T29/49128 , Y10T29/49146 , Y10T29/49151 , Y10T29/49155 , Y10T29/49171 , Y10T29/49172 , Y10T29/49176 , Y10T29/4922 , Y10T29/49224
摘要： Various pattern transfer and etching steps can be used to create features. Conventional photolithography steps can be used in combination with pitch-reduction techniques to form superimposed, pitch-reduced patterns of crossing elongate features that can be consolidated into a single layer. Planarizing techniques using a filler layer and a protective layer are disclosed. Portions of an integrated circuit having different heights can be etched to a common plane.
摘要翻译：可以使用各种图案转移和蚀刻步骤来产生特征。传统的光刻步骤可以与俯仰减小技术结合使用，以形成可以被整合成单一层的交叉细长特征的叠加的俯仰减小图案。公开了使用填充层和保护层的平面化技术。具有不同高度的集成电路的部分可以被蚀刻到公共平面。

22. 发明授权

US08324107B2 Method for forming high density patterns 有权
标题翻译：形成高密度图案的方法
公开(公告)号：US08324107B2
公开(公告)日：2012-12-04
申请号：US12686602
申请日：2010-01-13
申请人： Baosuo Zhou , Gurtej S. Sandhu , Ardavan Niroomand
发明人： Baosuo Zhou , Gurtej S. Sandhu , Ardavan Niroomand
IPC分类号： H01L21/311
CPC分类号： H01L21/76885 , H01L21/0337 , H01L21/0338 , H01L21/76816
摘要： Methods are disclosed, such as those involving increasing the density of isolated features in an integrated circuit. In one or more embodiments, a method is provided for forming an integrated circuit with a pattern of isolated features having a final density of isolated features that is greater than a starting density of isolated features in the integrated circuit by a multiple of two or more. The method can include forming a pattern of pillars having a density X, and forming a pattern of holes amongst the pillars, the holes having a density at least X. The pillars can be selectively removed to form a pattern of holes having a density at least 2X. In some embodiments, plugs can be formed in the pattern of holes, such as by epitaxial deposition on the substrate, in order to provide a pattern of pillars having a density 2X. In other embodiments, the pattern of holes can be transferred to the substrate by etching.
摘要翻译：公开了诸如涉及增加集成电路中的隔离特征的密度的方法。在一个或多个实施例中，提供了一种用于形成具有孤立特征图案的集成电路的方法，其具有比集成电路中的隔离特征的起始密度大2倍或更多倍的隔离特征的最终密度。该方法可以包括形成具有密度X的柱状图案，并且在柱之间形成孔的图案，孔的密度至少为X.可以选择性地去除柱，以形成至少具有密度的孔的图案 2X。在一些实施例中，插塞可以以空穴的图案形成，例如通过外延沉积在基板上，以便提供具有密度2X的柱状图案。在其他实施例中，孔的图案可以通过蚀刻转移到衬底。

23. 发明授权

US08216939B2 Methods of forming openings 有权
标题翻译：形成开口的方法
公开(公告)号：US08216939B2
公开(公告)日：2012-07-10
申请号：US12860765
申请日：2010-08-20
申请人： Vishal Sipani , Baosuo Zhou , Ming-Chuan Yang
发明人： Vishal Sipani , Baosuo Zhou , Ming-Chuan Yang
IPC分类号： H01L21/44
CPC分类号： H01L21/31144 , H01L21/0337 , H01L21/0338 , H01L21/76816 , H01L23/5226 , H01L23/528 , H01L2924/0002 , H01L2924/00
摘要： Some embodiments include methods of forming openings. For instance, a construction may have a material over a plurality of electrically conductive lines. A plurality of annular features may be formed over the material, with the annular features crossing the lines. A patterned mask may be formed over the annular features, with the patterned mask leaving segments of the annular features exposed through a window in the patterned mask. The exposed segments of the annular features may define a plurality of openings, and such openings may be transferred into the material to form openings extending to the electrically conductive lines.
摘要翻译：一些实施例包括形成开口的方法。例如，结构可以具有多条导电线上的材料。可以在材料上方形成多个环形特征，其中环形特征与线交叉。图案化掩模可以形成在环形特征上，其中图案化掩模留下通过图案化掩模中的窗口暴露的环形特征的段。环形特征的暴露部分可以限定多个开口，并且这样的开口可以被转移到材料中以形成延伸到导电线的开口。

24. 发明申请

US20110316114A1 SIMPLIFIED PITCH DOUBLING PROCESS FLOW 有权
标题翻译：简化的PITCH DOUBLING PROCESS FLOW
公开(公告)号：US20110316114A1
公开(公告)日：2011-12-29
申请号：US13229898
申请日：2011-09-12
申请人： Ardavan Niroomand , Baosuo Zhou , Ramakanth Alapati
发明人： Ardavan Niroomand , Baosuo Zhou , Ramakanth Alapati
IPC分类号： H01L27/06
CPC分类号： H01L27/04 , H01L21/0338 , H01L21/3088 , H01L2924/0002 , H01L2924/00
摘要： A method for fabricating a semiconductor device comprises patterning a layer of photoresist material to form a plurality of mandrels. The method further comprises depositing an oxide material over the plurality of mandrels by an atomic layer deposition (ALD) process. The method further comprises anisotropically etching the oxide material from exposed horizontal surfaces. The method further comprises selectively etching photoresist material.
摘要翻译：一种用于制造半导体器件的方法包括对一层光致抗蚀剂材料进行构图以形成多个心轴。该方法还包括通过原子层沉积（ALD）工艺在多个心轴上沉积氧化物材料。该方法还包括从暴露的水平表面各向异性地蚀刻氧化物材料。该方法还包括选择性地蚀刻光刻胶材料。

25. 发明授权

US07807575B2 Methods to reduce the critical dimension of semiconductor devices 有权
标题翻译：降低半导体器件临界尺寸的方法
公开(公告)号：US07807575B2
公开(公告)日：2010-10-05
申请号：US11606613
申请日：2006-11-29
申请人： Baosuo Zhou
发明人： Baosuo Zhou
IPC分类号： H01L23/544 , H01L21/311
CPC分类号： H01L21/0338 , H01L21/3088
摘要： A method of forming features on a target layer. The features have a critical dimension that is triple- or quadruple-reduced compared to the critical dimension of portions of a resist layer used as a mask. An intermediate layer is deposited over a target layer and the resist layer is formed over the intermediate layer. After patterning the resist layer, first spacers are formed on sidewalls of remaining portions of the resist layer, masking portions of the intermediate layer. Second spacers are formed on sidewalls of the portions of the intermediate layer. After removing the portions of the intermediate layer, the second spacers are used as a mask to form the features on the target layer. A partially fabricated integrated circuit device is also disclosed.
摘要翻译：在目标层上形成特征的方法。与用作掩模的抗蚀剂层的部分的临界尺寸相比，这些特征具有三倍或四倍的临界尺寸。在目标层上沉积中间层，并且在中间层上形成抗蚀剂层。在图案化抗蚀剂层之后，第一间隔物形成在抗蚀剂层的剩余部分的侧壁上，中间层的掩蔽部分。第二间隔件形成在中间层的部分的侧壁上。在去除中间层的部分之后，将第二间隔物用作掩模以在目标层上形成特征。还公开了部分制造的集成电路器件。

26. 发明授权

US07662718B2 Trim process for critical dimension control for integrated circuits 失效
标题翻译：用于集成电路的关键尺寸控制的修整过程
公开(公告)号：US07662718B2
公开(公告)日：2010-02-16
申请号：US11372825
申请日：2006-03-09
申请人： Mirzafer K. Abatchev , Krupakar Murali Subramanian , Baosuo Zhou
发明人： Mirzafer K. Abatchev , Krupakar Murali Subramanian , Baosuo Zhou
IPC分类号： H01L21/302
CPC分类号： H01L21/0337 , H01L21/0338 , H01L21/3086 , H01L21/3088 , H01L21/31144 , H01L21/32139
摘要： Methods of etching substrates employing a trim process for critical dimension control for integrated circuits are disclosed. In one embodiment, the method of etching includes providing a first hard mask layer over a target layer; providing a second hard mask layer over the first hard mask layer; providing a photoresist layer over the second hard mask layer; forming a pattern in the photoresist layer; transferring the pattern into the second hard mask layer; and trimming the second hard mask layer with the photoresist layer on top of the second hard mask layer. The top surface of the second hard mask layer is protected by the photoresist and the substrate is protected by the overlying first hard mask layer during the trim etch, which can therefore be aggressive.
摘要翻译：公开了采用用于集成电路的关键尺寸控制的修整工艺的衬底的蚀刻方法。在一个实施例中，蚀刻方法包括在目标层上提供第一硬掩模层; 在第一硬掩模层上提供第二硬掩模层; 在所述第二硬掩模层上提供光致抗蚀剂层; 在光致抗蚀剂层中形成图案; 将图案转移到第二硬掩模层中; 以及在所述第二硬掩模层的顶部上用所述光致抗蚀剂层修剪所述第二硬掩模层。第二硬掩模层的顶表面由光致抗蚀剂保护，并且衬底在修整蚀刻期间被上覆的第一硬掩模层保护，因此可以是侵蚀性的。

27. 发明申请

US20090149026A1 METHOD FOR FORMING HIGH DENSITY PATTERNS 有权
标题翻译：形成高密度图案的方法
公开(公告)号：US20090149026A1
公开(公告)日：2009-06-11
申请号：US11952017
申请日：2007-12-06
申请人： Baosuo Zhou , Gurtej S. Sandhu , Ardavan Niroomand
发明人： Baosuo Zhou , Gurtej S. Sandhu , Ardavan Niroomand
IPC分类号： H01L21/311
CPC分类号： H01L21/76885 , H01L21/0337 , H01L21/0338 , H01L21/76816
摘要： Methods are disclosed, such as those involving increasing the density of isolated features in an integrated circuit. In one or more embodiments, a method is provided for forming an integrated circuit with a pattern of isolated features having a final density of isolated features that is greater than a starting density of isolated features in the integrated circuit by a multiple of two or more. The method can include forming a pattern of pillars having a density X, and forming a pattern of holes amongst the pillars, the holes having a density at least X. The pillars can be selectively removed to form a pattern of holes having a density at least 2X. In some embodiments, plugs can be formed in the pattern of holes, such as by epitaxial deposition on the substrate, in order to provide a pattern of pillars having a density 2X. In other embodiments, the pattern of holes can be transferred to the substrate by etching.
摘要翻译：公开了诸如涉及增加集成电路中的隔离特征的密度的方法。在一个或多个实施例中，提供了一种用于形成具有孤立特征图案的集成电路的方法，其具有比集成电路中的隔离特征的起始密度大2倍或更多倍的隔离特征的最终密度。该方法可以包括形成具有密度X的柱状图案，并且在柱之间形成孔的图案，孔的密度至少为X.可以选择性地去除柱，以形成至少具有密度的孔的图案 2X。在一些实施例中，插塞可以以空穴的图案形成，例如通过外延沉积在基板上，以便提供具有密度2X的柱状图案。在其他实施例中，孔的图案可以通过蚀刻转移到衬底。

28. 发明申请

US20070238308A1 Simplified pitch doubling process flow 有权
标题翻译：简化俯仰加倍流程
公开(公告)号：US20070238308A1
公开(公告)日：2007-10-11
申请号：US11400603
申请日：2006-04-07
申请人： Ardavan Niroomand , Baosuo Zhou , Ramakanth Alapati
发明人： Ardavan Niroomand , Baosuo Zhou , Ramakanth Alapati
IPC分类号： H01L21/302
CPC分类号： H01L27/04 , H01L21/0338 , H01L21/3088 , H01L2924/0002 , H01L2924/00
摘要： A method for fabricating a semiconductor device comprises patterning a layer of photoresist material to form a plurality of mandrels in a device array region. The method further comprises depositing an oxide material over the plurality of mandrels and over a device peripheral region. The method further comprises forming a pattern of photoresist material over the oxide material in the device peripheral region. The method further comprises anisotropically etching the oxide material from exposed horizontal surfaces in the device array region. The method further comprises selectively etching photoresist material from the device array region and from the device peripheral region.
摘要翻译：一种用于制造半导体器件的方法包括将光致抗蚀剂材料层图案化以在器件阵列区域中形成多个心轴。该方法还包括在多个心轴上并在器件外围区域上沉积氧化物材料。该方法还包括在器件外围区域中的氧化物材料上形成光致抗蚀剂材料的图案。该方法还包括从器件阵列区域中暴露的水平表面各向异性地蚀刻氧化物材料。该方法还包括从器件阵列区域和器件外围区域选择性地蚀刻光致抗蚀剂材料。

29. 发明申请

US20070238299A1 SIMPLIFIED PITCH DOUBLING PROCESS FLOW 有权
标题翻译：简化的PITCH DOUBLING PROCESS FLOW
公开(公告)号：US20070238299A1
公开(公告)日：2007-10-11
申请号：US11744074
申请日：2007-05-03
申请人： Ardavan Niroomand , Baosuo Zhou , Ramakanth Alapati
发明人： Ardavan Niroomand , Baosuo Zhou , Ramakanth Alapati
IPC分类号： H01L21/02
CPC分类号： H01L27/04 , H01L21/0338 , H01L21/3088 , H01L2924/0002 , H01L2924/00
摘要： A method for fabricating a semiconductor device comprises patterning a layer of photoresist material to form a plurality of mandrels. The method further comprises depositing an oxide material over the plurality of mandrels by an atomic layer deposition (ALD) process. The method further comprises anisotropically etching the oxide material from exposed horizontal surfaces. The method further comprises selectively etching photoresist material.
摘要翻译：一种用于制造半导体器件的方法包括对一层光致抗蚀剂材料进行构图以形成多个心轴。该方法还包括通过原子层沉积（ALD）工艺在多个心轴上沉积氧化物材料。该方法还包括从暴露的水平表面各向异性地蚀刻氧化物材料。该方法还包括选择性地蚀刻光刻胶材料。

30. 发明授权

US08836083B2 Methods to reduce the critical dimension of semiconductor devices and related semiconductor devices 有权
标题翻译：减少半导体器件和相关半导体器件临界尺寸的方法
公开(公告)号：US08836083B2
公开(公告)日：2014-09-16
申请号：US13619905
申请日：2012-09-14
申请人： Baosuo Zhou
发明人： Baosuo Zhou
IPC分类号： H01L29/06 , H01L21/311 , H01L21/308 , H01L21/033
CPC分类号： H01L21/0338 , H01L21/3088
摘要： A method of forming features on a target layer. The features have a critical dimension that is triple- or quadruple-reduced compared to the critical dimension of portions of a resist layer used as a mask. An intermediate layer is deposited over a target layer and the resist layer is formed over the intermediate layer. After patterning the resist layer, first spacers are formed on sidewalls of remaining portions of the resist layer, masking portions of the intermediate layer. Second spacers are formed on sidewalls of the portions of the intermediate layer. After removing the portions of the intermediate layer, the second spacers are used as a mask to form the features on the target layer. Integrated circuit devices are also disclosed.
摘要翻译：在目标层上形成特征的方法。与用作掩模的抗蚀剂层的部分的临界尺寸相比，这些特征具有三倍或四倍的临界尺寸。在目标层上沉积中间层，并且在中间层上形成抗蚀剂层。在图案化抗蚀剂层之后，第一间隔物形成在抗蚀剂层的剩余部分的侧壁上，中间层的掩蔽部分。第二间隔件形成在中间层的部分的侧壁上。在去除中间层的部分之后，将第二间隔物用作掩模以在目标层上形成特征。还公开了集成电路器件。

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