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21. 发明申请

US20070001265A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20070001265A1
公开(公告)日：2007-01-04
申请号：US11276668
申请日：2006-03-09
申请人： Atsushi Narazaki
发明人： Atsushi Narazaki
IPC分类号： H01L27/082 , H01L29/70 , H01L27/102 , H01L31/11
CPC分类号： H01L23/482 , H01L23/4824 , H01L23/49562 , H01L24/34 , H01L24/37 , H01L24/73 , H01L2224/37147 , H01L2224/37599 , H01L2224/45124 , H01L2224/48463 , H01L2224/73221 , H01L2224/73265 , H01L2224/83801 , H01L2224/84801 , H01L2924/1305 , H01L2924/13055 , H01L2924/1306 , H01L2924/13091 , H01L2924/181 , H01L2924/351 , H01L2924/00 , H01L2924/00012 , H01L2924/00014
摘要： A semiconductor device has a structure capable of connecting a lead terminal directly to an electrode on a front surface thereof. The semiconductor device includes a first main electrode provided on the front surface, a second main electrode provided on a back surface, and a metal film provided so as to cover at least a portion of a surface of the first main electrode and for soldering the lead terminal thereto. Here, the metal film includes a plurality of opening portions through which the surface of the first main electrode is exposed.
摘要翻译：半导体器件具有能够将引线端子直接连接到其表面上的电极的结构。半导体器件包括设置在前表面的第一主电极，设置在背面上的第二主电极和设置成覆盖第一主电极表面的至少一部分并用于焊接引线的金属膜终端。这里，金属膜包括第一主电极的表面露出的多个开口部。

22. 发明授权

US07045831B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07045831B2
公开(公告)日：2006-05-16
申请号：US10918355
申请日：2004-08-16
申请人： Atsushi Narazaki
发明人： Atsushi Narazaki
IPC分类号： H01L29/73 , H01L29/74 , H01L31/111 , H01L27/082 , H01L27/102
CPC分类号： H01L24/05 , H01L23/4827 , H01L24/06 , H01L24/29 , H01L24/45 , H01L24/48 , H01L2224/04026 , H01L2224/04042 , H01L2224/05 , H01L2224/05644 , H01L2224/05655 , H01L2224/32245 , H01L2224/45124 , H01L2224/4847 , H01L2224/48491 , H01L2224/48699 , H01L2224/73265 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01022 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01042 , H01L2924/0105 , H01L2924/01068 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/1301 , H01L2924/1305 , H01L2924/13055 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/19043 , H01L2924/00014 , H01L2924/00
摘要： A semiconductor device of the present invention comprises a semiconductor chip, metal layers formed on a first main surface of the semiconductor chip, a first conductive layer layered on a second main surface of the semiconductor chip, consisting of a plurality of conductive films, a second conductive layer layered on the metal layer, having a layered structure consisting of a plurality of conductive films formed in the same order as in the first conductive layer as viewed from the semiconductor chip and a third conductive layer layered on the metal layer, having a layered structure consisting of a plurality of conductive films formed in the same order as in the first conductive layer as viewed from the semiconductor chip. The plurality of conductive films comprise a nickel film and a low contact resistance conductive film having contact resistance with the semiconductor chip which is lower than that of the nickel film. The low contact resistance conductive film and the nickel film are formed in this order from the semiconductor chip. With such a structure, a semiconductor device ensuring simplification of its manufacturing process can be provided.
摘要翻译：本发明的半导体器件包括半导体芯片，形成在半导体芯片的第一主表面上的金属层，层叠在半导体芯片的第二主表面上的第一导电层，由多个导电膜构成，第二导电层导电层，层叠在金属层上，具有由从半导体芯片观察的与第一导电层相同的数量形成的多个导电膜和层叠在金属层上的第三导电层构成的层叠结构，由从半导体芯片观察的与第一导电层中的顺序相同的多个导电膜构成的结构。多个导电膜包括与半导体芯片的接触电阻低于镍膜的接触电阻的镍膜和低接触电阻导电膜。低接触电阻导电膜和镍膜从半导体芯片依次形成。通过这样的结构，可以提供确保简化其制造工艺的半导体器件。

23. 发明授权

US06933576B2 Semiconductor device including a predetermined film formed at a border between dielectric films 失效
标题翻译：半导体器件包括在电介质膜之间的边界处形成的预定膜
公开(公告)号：US06933576B2
公开(公告)日：2005-08-23
申请号：US10681303
申请日：2003-10-09
申请人： Katsumi Uryuu , Atsushi Narazaki
发明人： Katsumi Uryuu , Atsushi Narazaki
IPC分类号： H01L29/78 , H01L21/335 , H01L29/423 , H01L21/8238 , H01L29/788
CPC分类号： H01L29/42368 , H01L29/7802
摘要： A semiconductor device includes a silicon oxide film (2) formed in a predetermined region on a single crystalline silicon substrate (1) and a gate dielectric film (3) as a thermal oxide film formed by performing thermal oxidation on the surface of the substrate (1) in a region adjacent to the silicon oxide film (2). A polycrystalline silicon (5) (or amorphous silicon) having an oxidized surface is formed on the border between the silicon oxide film (2) and gate dielectric film (3).
摘要翻译：半导体器件包括形成在单晶硅衬底（1）上的预定区域中的氧化硅膜（2）和作为通过在衬底的表面上进行热氧化形成的热氧化膜的栅极电介质膜（3） 1）在与氧化硅膜（2）相邻的区域中。在氧化硅膜（2）和栅极电介质膜（3）之间的边界上形成具有氧化表面的多晶硅（5）（或非晶硅）。

24. 发明授权

US09431479B2 High breakdown voltage semiconductor device having a resurf layer 有权
标题翻译：具有复层的高耐压电压半导体器件
公开(公告)号：US09431479B2
公开(公告)日：2016-08-30
申请号：US12845176
申请日：2010-07-28
申请人： Shigeto Honda , Atsushi Narazaki , Kaoru Motonami
发明人： Shigeto Honda , Atsushi Narazaki , Kaoru Motonami
IPC分类号： H01L29/06 , H01L29/40 , H01L29/66 , H01L29/861 , H01L29/16 , H01L29/20 , H01L29/78
CPC分类号： H01L29/0615 , H01L29/063 , H01L29/0638 , H01L29/0657 , H01L29/0661 , H01L29/1608 , H01L29/2003 , H01L29/402 , H01L29/66128 , H01L29/7811 , H01L29/8611
摘要： In a semiconductor device according to the present invention, an electrode layer and a recessed part are formed on a surface of a semiconductor substrate. Further, in the semiconductor substrate, a RESURF layer that is in contact with a bottom surface of the recessed part and the electrode layer is formed. In addition, an insulating film is formed on an upper surface of the semiconductor substrate so as to fill the recessed part. Moreover, a field plate electrode is formed on the insulating film above the recessed part.
摘要翻译：在根据本发明的半导体器件中，在半导体衬底的表面上形成电极层和凹部。此外，在半导体基板中，形成与凹部的底面接触的RESURF层和电极层。此外，在半导体衬底的上表面上形成绝缘膜以便填充凹部。此外，在凹部上方的绝缘膜上形成场板电极。

25. 发明授权

US08742474B2 Power semiconductor device having an active region and an electric field reduction region 有权
标题翻译：功率半导体器件具有有源区和电场减少区
公开(公告)号：US08742474B2
公开(公告)日：2014-06-03
申请号：US11937725
申请日：2007-11-09
申请人： Yoshiaki Hisamoto , Atsushi Narazaki , Hitoshi Uemura
发明人： Yoshiaki Hisamoto , Atsushi Narazaki , Hitoshi Uemura
IPC分类号： H01L29/66
CPC分类号： H01L29/7395 , H01L29/0619 , H01L29/0638 , H01L29/0834 , H01L29/402
摘要： A power semiconductor device of the present invention has an active region and an electric field reduction region and includes: an emitter region of a first conductivity type; a base region of a second conductivity type in contact with the emitter region; an electrical strength providing region of the first conductivity type in contact with the base region; a collector region of the second conductivity type in contact with the electrical strength providing region; and a collector electrode in contact with the collector region; wherein the collector region is disposed on both a active region and a electric field reduction region each containing a dopant of the second conductivity type, and the collector region disposed on the electric field reduction region includes a region having a lower density of carriers of the second conductivity type than the collector region disposed on the active region.
摘要翻译：本发明的功率半导体器件具有有源区和电场还原区，包括：第一导电型的发射极区; 与发射极区域接触的第二导电类型的基极区域; 所述第一导电类型的电强度提供区域与所述基极区域接触; 与所述电强度提供区域接触的所述第二导电类型的集电极区域; 以及与集电极区域接触的集电极; 其特征在于，所述集电极区域配置在各自含有所述第二导电型掺杂剂的有源区域和电场还原区域上，并且设置在所述电场还原区域上的所述集电极区域包括具有较低密度的载流子的区域，导电类型比设置在有源区上的集电极区域。

26. 发明授权

US08552468B2 Power semiconductor device 有权
标题翻译：功率半导体器件
公开(公告)号：US08552468B2
公开(公告)日：2013-10-08
申请号：US12724987
申请日：2010-03-16
申请人： Atsushi Narazaki
发明人： Atsushi Narazaki
IPC分类号： H01L29/74
CPC分类号： H01L29/7397 , H01L29/0696 , H01L29/0843 , H01L29/1095 , H01L29/4236 , H01L29/4238
摘要： A semiconductor layer has a first layer of first conductive type, a second layer of second conductive type, and a third layer. The third layer has a first region of first conductive type, and a second region of second conductive type. A second electrode is in contact with each of the first and second regions. A trench is formed on the semiconductor layer at a surface opposite to its surface facing a first electrode. A gate electrode is embedded in the trench with a gate insulating film interposed therebetween. The gate electrode includes a first portion projecting into the first layer through the first region and the second layer, a second portion projecting into the first layer through the second region and the second layer. The second portion projects into the first layer deeper than a depth in which the first portion projects into the first layer.
摘要翻译：半导体层具有第一导电类型的第一层，第二导电类型的第二层和第三层。第三层具有第一导电类型的第一区域和第二导电类型的第二区域。第二电极与第一和第二区域中的每一个接触。在半导体层的与面对第一电极的表面相对的表面上形成沟槽。栅电极嵌入在沟槽中，其间插入有栅极绝缘膜。栅电极包括通过第一区和第二层伸入第一层的第一部分，通过第二区和第二层突出到第一层的第二部分。第二部分比第一部分伸入第一层的深度深入第一层。

27. 发明授权

US08530966B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08530966B2
公开(公告)日：2013-09-10
申请号：US13205085
申请日：2011-08-08
申请人： Atsushi Narazaki , Hisaaki Yoshida , Kazuaki Higashi
发明人： Atsushi Narazaki , Hisaaki Yoshida , Kazuaki Higashi
IPC分类号： H01L29/76 , H01L21/336
CPC分类号： H01L29/7813 , H01L29/4236 , H01L29/4238 , H01L29/7811
摘要： A semiconductor device includes a trench extending from a surface of a P-base layer to a surface of a P-well layer. The trench has a trench end portion defined in the surface of the P-well layer and in a direction in which the trench extends. The trench has first and second regions. The first region extends from the trench end portion to get into the surface of the P-base layer near a boundary between the P-base layer and the P-well layer. The second region extends in the surface of the P-base layer from an end portion of the first region. A trench width is greater in the first region than in the second region.
摘要翻译：半导体器件包括从P基层的表面延伸到P阱层的表面的沟槽。沟槽具有限定在P阱层的表面中并且在沟槽延伸的方向上的沟槽端部。沟渠有第一和第二区域。第一区域从沟槽末端部延伸到P基层与P阱层之间的边界附近的P基层的表面。第二区域从第一区域的端部在P基层的表面延伸。沟道宽度在第一区域比在第二区域中大。

28. 发明授权

US08178365B2 Method of manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US08178365B2
公开(公告)日：2012-05-15
申请号：US13011263
申请日：2011-01-21
申请人： Atsushi Narazaki , Yukio Matsushita , Masashi Osaka , Shunsuke Sakamoto
发明人： Atsushi Narazaki , Yukio Matsushita , Masashi Osaka , Shunsuke Sakamoto
IPC分类号： G01R31/26
CPC分类号： H01L22/20 , H01L22/14 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor wafer having IGBT elements and transistors formed on a surface thereof is prepared. Electron beams are emitted all over the surface of the semiconductor wafer. Recombination centers are formed in the IGBT elements and the transistors. ON voltages of the transistors are measured by a measurement device, and lifetimes defined in the IGBT elements and the transistors are recovered by a prescribed annealing treatment. When the lifetimes are recovered, a control device controls an annealing treatment amount in the annealing treatment based on the measured ON voltages of the transistors such that ON voltages of the IGBT elements are each equal to a desired ON voltage. Variations in the ON voltages of a plurality of IGBT elements obtained from the semiconductor wafer are reduced.
摘要翻译：准备了在其表面上形成有IGBT元件和晶体管的半导体晶片。电子束在半导体晶片的整个表面上发射。在IGBT元件和晶体管中形成复合中心。通过测量装置测量晶体管的导通电压，并且通过规定的退火处理来恢复在IGBT元件和晶体管中限定的寿命。当寿命恢复时，控制装置基于所测量的晶体管的导通电压来控制退火处理中的退火处理量，使得IGBT元件的导通电压各自等于期望的导通电压。从半导体晶片获得的多个IGBT元件的导通电压的变化减小。

29. 发明授权

US08124533B2 Method of manufacturing power semiconductor device 有权
标题翻译：功率半导体器件制造方法
公开(公告)号：US08124533B2
公开(公告)日：2012-02-28
申请号：US12558999
申请日：2009-09-14
申请人： Atsushi Narazaki
发明人： Atsushi Narazaki
IPC分类号： H01L21/311
CPC分类号： H01L29/7813 , H01L29/1095 , H01L29/66348 , H01L29/66719 , H01L29/66734 , H01L29/7397
摘要： A mask layer having a plurality of openings is formed on the first layer. A second layer having a second conductivity type different from the first conductivity type is formed on the first layer by introducing impurities using the mask layer. A third layer having the first conductivity type is formed on the second layer by introducing impurities using the mask layer. A trench extending through the second layer and the third layer to the first layer is formed by carrying out etching using an etching mask including at least the mask layer. A gate insulation film covering a sidewall of the trench is formed. A trench gate filling the trench is formed on the gate insulation film.
摘要翻译：在第一层上形成具有多个开口的掩模层。通过使用掩模层引入杂质，在第一层上形成具有不同于第一导电类型的第二导电类型的第二层。通过使用掩模层引入杂质，在第二层上形成具有第一导电类型的第三层。通过使用至少包括掩模层的蚀刻掩模进行蚀刻来形成延伸穿过第二层和第三层到第一层的沟槽。形成覆盖沟槽侧壁的栅极绝缘膜。填充沟槽的沟槽栅极形成在栅极绝缘膜上。

30. 发明申请

US20110244604A1 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20110244604A1
公开(公告)日：2011-10-06
申请号：US13011263
申请日：2011-01-21
申请人： Atsushi Narazaki , Yukio Matsushita , Masashi Osaka , Shunsuke Sakamoto
发明人： Atsushi Narazaki , Yukio Matsushita , Masashi Osaka , Shunsuke Sakamoto
IPC分类号： H01L21/66
CPC分类号： H01L22/20 , H01L22/14 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor wafer having IGBT elements and transistors formed on a surface thereof is prepared. Electron beams are emitted all over the surface of the semiconductor wafer. Recombination centers are formed in the IGBT elements and the transistors. ON voltages of the transistors are measured by a measurement device, and lifetimes defined in the IGBT elements and the transistors are recovered by a prescribed annealing treatment. When the lifetimes are recovered, a control device controls an annealing treatment amount in the annealing treatment based on the measured ON voltages of the transistors such that ON voltages of the IGBT elements are each equal to a desired ON voltage. Variations in the ON voltages of a plurality of IGBT elements obtained from the semiconductor wafer are reduced.
摘要翻译：准备了在其表面上形成有IGBT元件和晶体管的半导体晶片。电子束在半导体晶片的整个表面上发射。在IGBT元件和晶体管中形成复合中心。通过测量装置测量晶体管的导通电压，并且通过规定的退火处理来恢复在IGBT元件和晶体管中限定的寿命。当寿命恢复时，控制装置基于所测量的晶体管的导通电压来控制退火处理中的退火处理量，使得IGBT元件的导通电压各自等于期望的导通电压。从半导体晶片获得的多个IGBT元件的导通电压的变化减小。

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