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21. 发明授权

US07075179B1 System for implementing a configurable integrated circuit 有权
公开(公告)号：US07075179B1
公开(公告)日：2006-07-11
申请号：US11016014
申请日：2004-12-17
申请人： Anwar Ali , Julie L. Beatty , Kalyan Doddapaneni
发明人： Anwar Ali , Julie L. Beatty , Kalyan Doddapaneni
IPC分类号： H01L23/48 , H01L23/485 , H01L23/50 , H01L23/552
CPC分类号： H01L24/06 , H01L23/49838 , H01L23/50 , H01L24/45 , H01L24/48 , H01L24/49 , H01L2224/0401 , H01L2224/05554 , H01L2224/451 , H01L2224/48227 , H01L2224/48233 , H01L2224/49171 , H01L2224/4943 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01027 , H01L2924/01033 , H01L2924/01075 , H01L2924/01076 , H01L2924/14 , H01L2924/1433 , H01L2924/00 , H01L2924/00015 , H01L2224/05599
摘要： The present invention provides a system for implementing a configurable integrated circuit (IC). Aspects of the invention include an IC die; a plurality of input/outputs (I/Os) coupled to the IC die; and a plurality power planes coupled to the IC die for providing power to the plurality of I/Os at different voltages. The plurality of power planes are configured concentrically around the IC die so that any one or more of the I/Os at any location on the IC die can be individually configured to connect to any of the power planes. As a result, any number of I/Os available on the IC die can operate at a given voltage.

22. 发明申请

US20070164451A1 Power configuration method for structured ASICs 有权
标题翻译：结构化ASIC的电源配置方法
公开(公告)号：US20070164451A1
公开(公告)日：2007-07-19
申请号：US11334870
申请日：2006-01-19
申请人： Anwar Ali , Tauman Lau , Kalyan Doddapaneni
发明人： Anwar Ali , Tauman Lau , Kalyan Doddapaneni
IPC分类号： H01L23/48
CPC分类号： H01L24/06 , H01L24/17 , H01L24/49 , H01L27/11898 , H01L2224/0401 , H01L2224/04073 , H01L2224/05093 , H01L2224/05553 , H01L2224/05554 , H01L2224/16 , H01L2224/49171 , H01L2224/4943 , H01L2924/00014 , H01L2924/14 , H01L2924/1433 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A method for electrically coupling a bond pad of an integrated circuit such as a field programmable device, an application-specific integrated circuit, or a rapid chip with an input/output device is disclosed. The bond pad is provided with a plurality of metal layers configurable for making a connection with the input/output device. The bond pad is then coupled to the input/output device with an interconnect structure. The method for electrically coupling the bond pad to the input/output device allows the customer to configure the power and ground pad counts after the slice is created.
摘要翻译：公开了一种用于将诸如现场可编程设备，专用集成电路或快速芯片的集成电路的接合焊盘电耦合到输入/输出设备的方法。接合焊盘设置有可配置用于与输入/输出设备连接的多个金属层。接合焊盘然后与互连结构耦合到输入/输出设备。将接合焊盘电耦合到输入/输出设备的方法允许客户在切片创建之后配置电源和接地焊盘计数。

23. 发明申请

US20060131725A1 System for implementing a configurable integrated circuit 有权
标题翻译：用于实现可配置集成电路的系统
公开(公告)号：US20060131725A1
公开(公告)日：2006-06-22
申请号：US11016014
申请日：2004-12-17
申请人： Anwar Ali , Julie Beatty , Kalyan Doddapaneni
发明人： Anwar Ali , Julie Beatty , Kalyan Doddapaneni
IPC分类号： H01L23/52
CPC分类号： H01L24/06 , H01L23/49838 , H01L23/50 , H01L24/45 , H01L24/48 , H01L24/49 , H01L2224/0401 , H01L2224/05554 , H01L2224/451 , H01L2224/48227 , H01L2224/48233 , H01L2224/49171 , H01L2224/4943 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01027 , H01L2924/01033 , H01L2924/01075 , H01L2924/01076 , H01L2924/14 , H01L2924/1433 , H01L2924/00 , H01L2924/00015 , H01L2224/05599
摘要： The present invention provides a system for implementing a configurable integrated circuit (IC). Aspects of the invention include an IC die; a plurality of input/outputs (I/Os) coupled to the IC die; and a plurality power planes coupled to the IC die for providing power to the plurality of I/Os at different voltages. The plurality of power planes are configured concentrically around the IC die so that any one or more of the I/Os at any location on the IC die can be individually configured to connect to any of the power planes. As a result, any number of I/Os available on the IC die can operate at a given voltage.
摘要翻译：本发明提供一种用于实现可配置集成电路（IC）的系统。本发明的方面包括IC芯片; 耦合到IC管芯的多个输入/输出（I / O）; 以及耦合到IC管芯的多个电源层，用于以不同的电压向多个I / O供电。多个电源平面被配置成围绕IC芯片同心地配置，使得IC芯片上的任何位置处的I / O中的任何一个或多个可被单独配置成连接到任何电源层。因此，IC芯片上可用的任何数量的I / O可以在给定电压下工作。

24. 发明授权

US06781228B2 Donut power mesh scheme for flip chip package 有权
公开(公告)号：US06781228B2
公开(公告)日：2004-08-24
申请号：US10339844
申请日：2003-01-10
申请人： Hiroshi Ishikawa , Thomas Antisseril , Radoslav Ratchkov , Bo Shen , Prasad Subbarao , Maad Al-Dabagh , Anwar Ali , Benjamin Mbouombouo
发明人： Hiroshi Ishikawa , Thomas Antisseril , Radoslav Ratchkov , Bo Shen , Prasad Subbarao , Maad Al-Dabagh , Anwar Ali , Benjamin Mbouombouo
IPC分类号： H01L2352
CPC分类号： H01L23/5286 , H01L24/81 , H01L2224/81801
摘要： A multiple layer mesh design which includes a layer which provides a vertical mesh and an adjacent layer which provides a horizontal mesh which includes an open area or hole. The layer which provides the horizontal mesh (with hole) may either be above or below the vertical mesh layer, depending on the design. The vertical mesh may be full or may surround an open area or hole where the design includes both a horizontal donut mesh and a vertical donut mesh.

25. 发明授权

US06671865B1 High density input output 失效
标题翻译：高密度输入输出
公开(公告)号：US06671865B1
公开(公告)日：2003-12-30
申请号：US09994567
申请日：2001-11-27
申请人： Anwar Ali , Farshad Ghahghahi , Edwin M. Fulcher
发明人： Anwar Ali , Farshad Ghahghahi , Edwin M. Fulcher
IPC分类号： G06F1750
CPC分类号： H01L23/49838 , G06F17/5068 , G06F2217/40 , H01L2924/0002 , H01L2924/00
摘要： An input/output array of an integrated circuit comprises concentric rings of input/output tiles. The peripheral input/output tiles are adjacently arranged along the periphery of the integrated circuit to form a peripheral ring. Each of the peripheral input/output tiles is associated with a corresponding peripheral input/output device group having x1 number of input/output devices. Each peripheral input/output tile includes x1 number of signal contacts for coupling signals to corresponding ones of the x1 number of input/output devices, y1 number of input/output driver voltage contacts for coupling a source voltage to drivers of the x1 number of input/output devices, and z1 number of ground contacts. The interior input/output tiles are adjacently arranged within the interior of the integrated circuit to form n number of substantially concentric interior rings, where n is greater than or equal to one.
摘要翻译：集成电路的输入/输出阵列包括输入/输出瓦片的同心环。周边输入/输出瓦片沿着集成电路的周边相邻布置以形成外围环。每个外围输入/输出瓦片与具有x1个输入/输出设备的相应的外围输入/输出设备组相关联。每个外围输入/输出瓦片包括x1个信号触点，用于将信号耦合到x1个输入/输出设备中的相应的输入/输出设备，y1个输入/输出驱动器电压触点数量，用于将源电压耦合到X1输入端的驱动器 /输出设备，以及z1个接地点数。内部输入/输出瓦片相邻地布置在集成电路的内部，以形成n个基本上同心的内部环，其中n大于或等于1。

26. 发明授权

US07117467B2 Methods for optimizing package and silicon co-design of integrated circuit 有权
标题翻译：优化集成电路封装和硅协同设计的方法
公开(公告)号：US07117467B2
公开(公告)日：2006-10-03
申请号：US10918933
申请日：2004-08-16
申请人： Anwar Ali , Stan Mihelcic , James G. Monthie
发明人： Anwar Ali , Stan Mihelcic , James G. Monthie
IPC分类号： G06F17/50 , H01L21/44 , H01L21/48 , H01L21/50 , H01L23/488
CPC分类号： G06F17/5068
摘要： The present invention is directed to methods for optimizing package and silicon co-design of an integrated circuit. A composite bump pattern for an integrated circuit is created based on a first library including at least one bump pattern template. PCB and Die constraints of the integrated circuit are then reviewed. A partial package design for the integrated circuit is generated based on a second library including at least one partial package template. A partial silicon design for said integrated circuit is started. A full package design for the integrated circuit is then completed. A full silicon design for the integrated circuit is completed.
摘要翻译：本发明涉及用于优化集成电路的封装和硅协同设计的方法。基于包括至少一个凸块图案模板的第一库创建用于集成电路的复合凸块图案。然后审查集成电路的PCB和晶片约束。基于包括至少一个部分封装模板的第二库生成集成电路的部分封装设计。开始用于所述集成电路的部分硅设计。然后完成集成电路的完整封装设计。集成电路的全硅设计完成。

27. 发明申请

US20060022687A1 Disabling unused IO resources in platform-based integrated circuits 失效
标题翻译：在基于平台的集成电路中禁用未使用的IO资源
公开(公告)号：US20060022687A1
公开(公告)日：2006-02-02
申请号：US10909603
申请日：2004-08-02
申请人： Anwar Ali , Julie Beatty , Kalyan Doddapaneni
发明人： Anwar Ali , Julie Beatty , Kalyan Doddapaneni
IPC分类号： G01R31/02
CPC分类号： G01R31/31712 , G01R31/31704
摘要： The present invention is directed to methods for disabling unused IO resources in a platform-based integrated circuit. A slice is received from a vendor. The slice includes an IO circuit unused by a customer. The IO circuit is disabled. For example, when the IO circuit is desired to be tied to a power source, a primary input/output pin of the IO circuit is shorted to a power bus of the IO circuit. When the IO circuit is desired to be tied to a ground source, a primary input/output pin of the IO circuit is shorted to a ground bus of the IO circuit. When the IO circuit is desired to be left floated, a primary input/output pin of the IO circuit is not connected to any bonding pad cell of the slice. Next, the IO circuit is removed from the customer's logic design netlist. The IO circuit is inserted in the vendor's physical design database.
摘要翻译：本发明涉及用于在基于平台的集成电路中禁用未使用的IO资源的方法。从供应商接收到一个切片。该片包括客户未使用的IO电路。 IO电路被禁止。例如，当IO电路需要连接到电源时，IO电路的主输入/输出引脚与IO电路的电源总线短路。当IO电路需要连接到接地源时，IO电路的主输入/输出引脚短接到IO电路的接地总线。当IO电路需要悬浮时，IO电路的主输入/输出引脚不连接到片的任何焊盘单元。接下来，IO电路从客户的逻辑设计网表中删除。 IO电路插入供应商的物理设计数据库。

28. 发明授权

US06704918B1 Integrated circuit routing 有权
标题翻译：集成电路布线
公开(公告)号：US06704918B1
公开(公告)日：2004-03-09
申请号：US09311981
申请日：1999-05-14
申请人： Anwar Ali , Virendra Patel
发明人： Anwar Ali , Virendra Patel
IPC分类号： G06F1750
CPC分类号： G06F17/5077 , H01L27/0207
摘要： A technique is described for enabling routing of metallisation wires over sensitive cells of an integrated circuit by means of a global router after the cell circuits have been designed. At least one cell includes dedicated route paths (32, 36, 40, 46) as part of the cell design. The paths may include alternative paths (32 and 36), and concurrently usable paths (40 and 46). By including the routes as part of the cell design, the subsequent problems of a global routing tool routing wires over sensitive areas of the cell can be avoided, and the number of wire routes can be controlled. The global router operates by detecting whether dedicated routes are provided and, if so, identifying the entry/exit points for routes to be used.
摘要翻译：描述了一种技术，用于在单元电路被设计之后通过全局路由器实现金属化导线在集成电路的敏感单元上的路由。至少一个单元包括作为单元设计的一部分的专用路径路径（32,36,40,46）。路径可以包括替代路径（32和36）以及可同时使用的路径（40和46）。通过将路由作为单元设计的一部分，可以避免在单元的敏感区域上布线的全局布线工具的后续问题，并且可以控制线路数量。全局路由器通过检测是否提供专用路由器进行操作，如果是，则识别要使用的路由的入口/出口点。

29. 发明授权

US06657870B1 Die power distribution system 有权
标题翻译：模具配电系统
公开(公告)号：US06657870B1
公开(公告)日：2003-12-02
申请号：US09968286
申请日：2001-10-01
申请人： Anwar Ali , Benjamin Mbouombouo , Max Yeung
发明人： Anwar Ali , Benjamin Mbouombouo , Max Yeung
IPC分类号： H05K702
CPC分类号： H01L23/50 , H01L23/49838 , H01L24/06 , H01L2224/05554 , H01L2224/49171 , H01L2924/14 , H01L2924/00
摘要： A power distribution system for distributing external power across a die is disclosed, wherein the die has horizontal and vertical centerlines. The system and method include providing a power mesh that includes a plurality of V-shaped trunks patterned as concentric diagonal trunks extending from the horizontal and vertical centerlines of the die towards the periphery of the die.
摘要翻译：公开了一种用于在模具上分配外部电力的配电系统，其中模具具有水平和垂直的中心线。该系统和方法包括提供功率网格，其包括被图案化为从模具的水平和垂直中心线延伸到模具的周边的同心对角线的多个V形树干。

30. 发明申请

US20130154109A1 METHOD OF LOWERING CAPACITANCES OF CONDUCTIVE APERTURES AND AN INTERPOSER CAPABLE OF BEING REVERSE BIASED TO ACHIEVE REDUCED CAPACITANCE 审中-公开
标题翻译：降低导电性能的方法和可逆向实现降低电容的插入器的方法
公开(公告)号：US20130154109A1
公开(公告)日：2013-06-20
申请号：US13328332
申请日：2011-12-16
申请人： Ramnath Venkatraman , John W. Osenbach , Anwar Ali , Donald E. Hawk , Robert J. Madge
发明人： Ramnath Venkatraman , John W. Osenbach , Anwar Ali , Donald E. Hawk , Robert J. Madge
IPC分类号： H01L23/48 , H01L21/22 , H01L21/02
CPC分类号： H01L23/4926 , H01L23/49827 , H01L23/5384 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2924/15311 , H01L2924/00
摘要： The disclosure provides an interposer with conductive paths, a three-dimensional integrated circuit (3D IC), a method of reducing capacitance associated with conductive paths in an interposer and a method of manufacturing an interposer. In one embodiment the interposer includes: (1) a semiconductor substrate that is doped with a dopant, (2) conductive paths located within said semiconductor substrate and configured to provide electrical routes therethrough and (3) an ohmic contact region located within said semiconductor substrate and configured to receive a back bias voltage.
摘要翻译：本公开提供了具有导电路径的插入器，三维集成电路（3D IC），减小与插入器中的导电路径相关联的电容的方法和制造插值器的方法。在一个实施例中，插入器包括：（1）掺杂有掺杂剂的半导体衬底，（2）位于所述半导体衬底内的导电路径，并且被配置为提供穿过其中的电路径，以及（3）位于所述半导体衬底内的欧姆接触区域并被配置为接收背偏置电压。

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