专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

21. 发明申请

US20060163651A1 Semiconductor device having a dislocation loop located within a boundary created by source/drain regions and a method of manufacture therefor 有权
标题翻译：具有位于由源/漏区产生的边界内的位错环的半导体器件及其制造方法
公开(公告)号：US20060163651A1
公开(公告)日：2006-07-27
申请号：US11042415
申请日：2005-01-25
申请人： Antonio Rotondaro , Kaiping Liu , Jihong Chen , Amitabh Jain
发明人： Antonio Rotondaro , Kaiping Liu , Jihong Chen , Amitabh Jain
IPC分类号： H01L29/06
CPC分类号： H01L29/6659 , H01L21/26506 , H01L21/823814 , H01L21/823871
摘要： The present invention provides a method for manufacturing a transistor device, a method for manufacturing an integrated circuit, and a transistor device. The method for manufacturing the transistor device, among other steps, includes forming a gate structure over a substrate and forming source/drain regions in the substrate proximate the gate structure, the source/drain regions having a boundary that forms an electrical junction with the substrate. The method further includes forming dislocation loops in the substrate, the dislocation loops not extending outside the boundary of the source/drain regions.
摘要翻译：本发明提供了晶体管器件的制造方法，集成电路的制造方法以及晶体管器件。制造晶体管器件的方法以及其它步骤包括在衬底上形成栅极结构，并在栅极结构附近形成衬底中的源极/漏极区域，源极/漏极区域具有与衬底形成电连接的边界。该方法还包括在衬底中形成位错环，位错环不延伸到源/漏区的边界之外。

22. 发明申请

US20060046367A1 Method to selectively recess ETCH regions on a wafer surface using capoly as a mask 有权
标题翻译：使用capoly作为掩模来选择性地在晶片表面上凹入ETCH区域的方法
公开(公告)号：US20060046367A1
公开(公告)日：2006-03-02
申请号：US10931195
申请日：2004-08-31
申请人： Antonio Rotondaro , Seetharaman Sridhar
发明人： Antonio Rotondaro , Seetharaman Sridhar
IPC分类号： H01L21/8238
CPC分类号： H01L29/7842 , H01L21/823807 , H01L21/823814 , H01L29/7843 , H01L29/7848
摘要： The present invention facilitates semiconductor fabrication by providing methods of fabrication that selectively apply strain to channel regions of devices while mitigating masking operations employed. A CAPOLY layer is formed over an NMOS region of a semiconductor device (102). A recess etch is performed on active regions of devices within a PMOS region of the semiconductor device (104) and the CAPOLY layer prevents etching of devices within an NMOS region of the semiconductor device. Subsequently, an epitaxial formation process (106) is performed that forms or deposits epitaxial regions and introduces a first type of strain across the channel regions in the PMOS region. Then, the semiconductor device is annealed (108) to cause the CAPOLY layer to introduce a second type of strain across the channel regions in the NMOS region. After annealing, the CAPOLY layer is removed (110).
摘要翻译：本发明通过提供制造方法来促进半导体制造，该方法选择性地将应变应用于器件的沟道区，同时减轻所采用的掩模操作。在半导体器件（102）的NMOS区域上形成CAPOLY层。在半导体器件（104）的PMOS区域内的器件的有源区域上执行凹蚀刻，并且CAPOLY层防止在半导体器件的NMOS区域内的器件的蚀刻。随后，执行形成或沉积外延区域并在PMOS区域中的沟道区域上引入第一类型的应变的外延形成工艺（106）。然后，半导体器件被退火（108）以使CAPOLY层在NMOS区域中的沟道区域上引入第二类型的应变。退火后，去除CAPOLY层（110）。

23. 发明申请

US20050014353A1 Method to reduce transistor gate to source/drain overlap capacitance by incorporaton of carbon 有权
标题翻译：通过碳引入降低晶体管栅极到源极/漏极重叠电容的方法
公开(公告)号：US20050014353A1
公开(公告)日：2005-01-20
申请号：US10620492
申请日：2003-07-16
申请人： Majid Mansoori , Alwin Tsao , Antonio Rotondaro , Brian Smith
发明人： Majid Mansoori , Alwin Tsao , Antonio Rotondaro , Brian Smith
IPC分类号： H01L21/265 , H01L21/28 , H01L21/3213 , H01L29/423 , H01L21/3205
CPC分类号： H01L21/28044 , H01L21/26506 , H01L21/28114 , H01L21/32137 , H01L29/42376
摘要： The present invention pertains to formation of a transistor in a manner that mitigates overlap capacitances, thereby facilitating, among other things, enhanced switching speeds. More particularly, a gate stack of the transistor is formed to include an optional layer of poly-SiGe and a layer of poly-Si, where at least one or the layers comprises carbon. The stack may also include a polysilicon seed layer that can also comprise carbon. The carbon changes the components of sidewall passivation materials and affects etch rates during an etching process, thereby facilitating isotropic etching. The changed passivation materials coupled with an enhanced sensitivity of the poly-SiGe and carbon-doped poly-SiGe layer to an etchant utilized in the etching process causes the stack to have a notched appearance. The tapered configuration of the gate stack provides little, if any, area for dopants that may migrate under the gate structure to overlap the conductive layers in the stack, and thus mitigates the opportunity for overlap capacitances to arise.
摘要翻译：本发明涉及以减轻重叠电容的方式形成晶体管，从而有利于提高切换速度。更具体地，晶体管的栅极堆叠形成为包括任选的多晶硅层和多晶硅层，其中至少一个或多个层包含碳。堆叠还可以包括也可以包含碳的多晶硅种子层。碳改变侧壁钝化材料的组分并影响蚀刻过程中的蚀刻速率，从而促进各向同性蚀刻。与蚀刻过程中使用的蚀刻剂相比，改变的钝化材料与多晶硅和掺杂碳的多晶硅层的增强灵敏度相结合，使堆叠具有缺口外观。栅极堆叠的锥形配置对于可能在栅极结构下迁移以与堆叠中的导电层重叠的掺杂剂提供很小的（如果有的话）区域，并且因此减轻了重叠电容出现的机会。

24. 发明申请

US20070249168A1 CRYSTALLOGRAPHIC PREFERENTIAL ETCH TO DEFINE A RECESSED-REGION FOR EPITAXIAL GROWTH 有权
标题翻译：确定外来生长发育区域的晶体优选蚀刻
公开(公告)号：US20070249168A1
公开(公告)日：2007-10-25
申请号：US11379408
申请日：2006-04-20
申请人： Antonio Rotondaro , Trace Hurd , Elisabeth Koontz
发明人： Antonio Rotondaro , Trace Hurd , Elisabeth Koontz
IPC分类号： H01L21/311
CPC分类号： H01L21/30608 , H01L21/823807 , H01L21/823814 , H01L29/165 , H01L29/665 , H01L29/6656 , H01L29/66636 , H01L29/7848
摘要： A semiconductor device 100 comprising a gate structure 105 on a semiconductor substrate 110 and a recessed-region 115 in the semiconductor substrate. The recessed-region has a widest lateral opening 120 that is near a top surface 122 of the semiconductor substrate. The widest lateral opening undercuts the gate structure.
摘要翻译：半导体器件100包括在半导体衬底110上的栅极结构105和半导体衬底中的凹陷区域115。凹陷区域具有最接近半导体衬底的顶表面122的侧向开口120。最宽的侧向开口会削弱门结构。

25. 发明申请

US20050263834A1 Encapsulated spacer with low dielectric constant material to reduce the parasitic capacitance between gate and drain in CMOS technology 审中-公开
标题翻译：具有低介电常数材料的封装间隔物，以减少CMOS技术中栅极和漏极之间的寄生电容
公开(公告)号：US20050263834A1
公开(公告)日：2005-12-01
申请号：US11177142
申请日：2005-07-07
申请人： Yuanning Chen , Antonio Rotondaro , Karen Kirmse
发明人： Yuanning Chen , Antonio Rotondaro , Karen Kirmse
IPC分类号： H01L21/336 , H01L29/49
CPC分类号： H01L29/4983 , H01L29/6656 , H01L29/6659
摘要： The present invention pertains to formation of a transistor in a manner that mitigates parasitic capacitance, thereby facilitating, inter alia, enhanced switching speeds. More particularly, a sidewall spacer formed upon a semiconductor substrate adjacent a conductive gate structure includes a material having a low dielectric constant (low-k) to mitigate parasitic capacitance between the gate structure, the sidewall spacer and a conductive drain formed within the semiconductor substrate. The low-k sidewall spacer is encapsulated within a nitride material which is selective to etchants such that the spacer is not altered during subsequent processing. The spacer thus retains its shape and remains effective to guide dopants into desired locations within the substrate.
摘要翻译：本发明涉及以减轻寄生电容的方式形成晶体管，从而有助于特别地提高切换速度。更具体地，形成在与导电栅极结构相邻的半导体衬底上的侧壁间隔物包括具有低介电常数（低k）的材料，以减轻栅极结构，侧壁间隔物和形成在半导体衬底内的导电漏极之间的寄生电容。低k侧壁间隔物被封装在对蚀刻剂有选择性的氮化物材料内，使得间隔物在随后的处理期间不改变。间隔物因此保持其形状并且仍然有效地将掺杂剂引导到衬底内的期望位置。

26. 发明申请

US20050087775A1 Encapsulated spacer with low dielectric constant material to reduce the parasitic capacitance between gate and drain in CMOS technology 有权
公开(公告)号：US20050087775A1
公开(公告)日：2005-04-28
申请号：US10692388
申请日：2003-10-23
申请人： Yuanning Chen , Antonio Rotondaro , Karen Kirmse
发明人： Yuanning Chen , Antonio Rotondaro , Karen Kirmse
IPC分类号： H01L21/336 , H01L29/49 , H01L29/80
CPC分类号： H01L29/4983 , H01L29/6656 , H01L29/6659
摘要： The present invention pertains to formation of a transistor in a manner that mitigates parasitic capacitance, thereby facilitating, inter alia, enhanced switching speeds. More particularly, a sidewall spacer formed upon a semiconductor substrate adjacent a conductive gate structure includes a material having a low dielectric constant (low-k) to mitigate parasitic capacitance between the gate structure, the sidewall spacer and a conductive drain formed within the semiconductor substrate. The low-k sidewall spacer is encapsulated within a nitride material which is selective to etchants such that the spacer is not altered during subsequent processing. The spacer thus retains its shape and remains effective to guide dopants into desired locations within the substrate.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式