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21. 发明申请

US20070267673A1 Adjustable on-chip sub-capacitor design 有权
标题翻译：可调片上子电容设计
公开(公告)号：US20070267673A1
公开(公告)日：2007-11-22
申请号：US11436249
申请日：2006-05-18
申请人： Jonghae Kim , Moon J. Kim , Jean-Olivier Plouchart , Robert E. Trzcinski
发明人： Jonghae Kim , Moon J. Kim , Jean-Olivier Plouchart , Robert E. Trzcinski
IPC分类号： H01L27/108 , H01L29/94 , H01L29/76 , H01L31/119
CPC分类号： H01L27/0805 , H01L23/5223 , H01L27/0688 , H01L27/0808 , H01L2924/0002 , H01L2924/00
摘要： One or more on-chip VNCAP or MIMCAP capacitors utilize a variable MOS capacitor to improve the uniform capacitance value of the capacitors. This permits the production of silicon semiconductor chips on which are mounted capacitors having capacitive values that are precisely adjusted to be within a range of between about 1% and 5% of their design value. This optimization can be achieved by the use of a back-to-back connection between a pair of the variable MOS capacitors for DC decoupling. It involves the parallelization of on-chip BEOL capacitance of VNCAP and/or MIMCAP capacitors by the insertion in the FEOL of pairs of back-to-back variable MOS capacitors.
摘要翻译：一个或多个片上VNCAP或MIMCAP电容器利用可变MOS电容来改善电容器的均匀电容值。这允许生产硅半导体芯片，其上安装有具有精确调节的电容值的电容器在其设计值的约1％至5％的范围内。该优化可以通过使用一对用于DC去耦的可变MOS电容器之间的背对背连接来实现。它涉及VOCAP和/或MIMCAP电容器的片上BEOL电容的并联，通过在FEOL中插入成对的背对背可变MOS电容器。

22. 发明授权

US08039354B2 Passive components in the back end of integrated circuits 有权
标题翻译：集成电路后端的被动元件
公开(公告)号：US08039354B2
公开(公告)日：2011-10-18
申请号：US12849086
申请日：2010-08-03
申请人： Anil K. Chinthakindi , Douglas D. Coolbaugh , Ebenezer E. Eshun , Zhong-Xiang He , Jeffrey B. Johnson , Jonghae Kim , Jean-Oliver Plouchart , Anthony K. Stamper
发明人： Anil K. Chinthakindi , Douglas D. Coolbaugh , Ebenezer E. Eshun , Zhong-Xiang He , Jeffrey B. Johnson , Jonghae Kim , Jean-Oliver Plouchart , Anthony K. Stamper
IPC分类号： H01L21/02
CPC分类号： H01L23/5228 , H01L23/5227 , H01L28/87 , H01L2924/0002 , H01L2924/00
摘要： Passive components are formed in the back end by using the same deposition process and materials as in the rest of the back end. Resistors are formed by connecting in series individual structures on the nth, (n+1)th, etc levels of the back end. Capacitors are formed by constructing a set of vertical capacitor plates from a plurality of levels in the back end, the plates being formed by connecting electrodes on two or more levels of the back end by vertical connection members.
摘要翻译：通过使用与后端的其余部分相同的沉积工艺和材料在后端形成被动部件。电阻器通过连接在后端的第n（n + 1）等级上的串联单独结构而形成。电容器通过从后端的多个层构造一组垂直电容器板而形成，该板通过垂直连接构件在后端的两层或更多层上连接电极而形成。

23. 发明授权

US07768055B2 Passive components in the back end of integrated circuits 失效
标题翻译：集成电路后端的被动元件
公开(公告)号：US07768055B2
公开(公告)日：2010-08-03
申请号：US11164634
申请日：2005-11-30
申请人： Anil K. Chinthakindi , Douglas D. Coolbaugh , Ebenezer E. Eshun , Zhong-Xiang He , Jeffrey B. Johnson , Jonghae Kim , Jean-Oliver Plouchart , Anthony K. Stamper
发明人： Anil K. Chinthakindi , Douglas D. Coolbaugh , Ebenezer E. Eshun , Zhong-Xiang He , Jeffrey B. Johnson , Jonghae Kim , Jean-Oliver Plouchart , Anthony K. Stamper
IPC分类号： H01L29/94
CPC分类号： H01L23/5228 , H01L23/5227 , H01L28/87 , H01L2924/0002 , H01L2924/00
摘要： Passive components are formed in the back end by using the same deposition process and materials as in the rest of the back end. Resistors are formed by connecting in series individual structures on the nth, (n+1)th, etc levels of the back end. Capacitors are formed by constructing a set of vertical capacitor plates from a plurality of levels in the back end, the plates being formed by connecting electrodes on two or more levels of the back end by vertical connection members.
摘要翻译：通过使用与后端的其余部分相同的沉积工艺和材料在后端形成被动部件。电阻器通过连接在后端的第n（n + 1）等级上的串联单独结构而形成。电容器通过从后端的多个层构造一组垂直电容器板而形成，该板通过垂直连接构件在后端的两层或更多层上连接电极而形成。

24. 发明授权

US09406865B2 Composite piezoelectric laterally vibrating resonator 有权
标题翻译：复合压电横向振动谐振器
公开(公告)号：US09406865B2
公开(公告)日：2016-08-02
申请号：US13587618
申请日：2012-08-16
申请人： Chengjie Zuo , Changhan Hobie Yun , Jonghae Kim
发明人： Chengjie Zuo , Changhan Hobie Yun , Jonghae Kim
IPC分类号： H01L41/09 , H01L41/18 , H03H9/02 , H01L41/277
CPC分类号： H01L41/183 , H01L41/277 , H03H9/02015 , H03H9/02228 , Y10T29/42
摘要： A resonator is described. The resonator includes multiple electrodes. The resonator also includes a composite piezoelectric material. The composite piezoelectric material includes at least one layer of a first piezoelectric material and at least one layer of a second piezoelectric material. At least one electrode is coupled to a bottom of the composite piezoelectric material. At least one electrode is coupled to a top of the composite piezoelectric material.
摘要翻译：描述谐振器。谐振器包括多个电极。谐振器还包括复合压电材料。复合压电材料包括至少一层第一压电材料和至少一层第二压电材料。至少一个电极耦合到复合压电材料的底部。至少一个电极耦合到复合压电材料的顶部。

25. 发明授权

US09245881B2 Selective fabrication of high-capacitance insulator for a metal-oxide-metal capacitor 有权
标题翻译：用于金属氧化物 - 金属电容器的高容量绝缘体的选择性制造
公开(公告)号：US09245881B2
公开(公告)日：2016-01-26
申请号：US12405303
申请日：2009-03-17
申请人： Woo Tag Kang , Jonghae Kim , Jungwon Suh
发明人： Woo Tag Kang , Jonghae Kim , Jungwon Suh
IPC分类号： H01L49/02 , H01L27/08 , G06F17/50
CPC分类号： H01L27/0805 , G06F17/5068 , H01L28/40 , Y10T29/49117
摘要： Methods and devices of a capacitor in a semiconductor device having an increased capacitance are disclosed. In a particular embodiment, a method of forming a capacitor is disclosed. A section of a first insulating material between a first metal contact element and a second metal contact element is removed to form a channel. A second insulating material is deposited in the channel between the first metal contact element and the second metal contact element.
摘要翻译：公开了具有增加的电容的半导体器件中的电容器的方法和装置。在特定实施例中，公开了形成电容器的方法。在第一金属接触元件和第二金属接触元件之间的第一绝缘材料的一部分被去除以形成通道。在第一金属接触元件和第二金属接触元件之间的通道中沉积第二绝缘材料。

26. 发明申请

US20140028543A1 COMPLEX PASSIVE DESIGN WITH SPECIAL VIA IMPLEMENTATION 有权
标题翻译：复杂的被动设计，特别是通过实施
公开(公告)号：US20140028543A1
公开(公告)日：2014-01-30
申请号：US13562168
申请日：2012-07-30
申请人： Chi Shun Lo , Je-Hsiung Jeffrey Lan , Mario Francisco Velez , Robert Paul Mikulka , Chengjie Zuo , Changhan Hobie Yun , Jonghae Kim
发明人： Chi Shun Lo , Je-Hsiung Jeffrey Lan , Mario Francisco Velez , Robert Paul Mikulka , Chengjie Zuo , Changhan Hobie Yun , Jonghae Kim
IPC分类号： H01F5/00 , B05D5/12 , C25D5/02 , G06T1/00 , G06F3/01 , G06F1/16 , B05D3/10
CPC分类号： H01F17/0006 , G02B26/001 , H01F27/2804 , H01L23/5227 , H01L28/10 , H01L2924/00 , H01L2924/0002
摘要： This disclosure provides systems, methods and apparatus for vias in an integrated circuit structure such as a passive device. In one aspect, an integrated passive device includes a first conductive trace and a second conductive trace over the first conductive trace with an interlayer dielectric between a portion of the first conductive trace and the second conductive trace. One or more vias are provided within the interlayer dielectric to provide electrical connection between the first conductive trace and the second conductive trace. A width of the vias is greater than a width of at least one of the conductive traces.
摘要翻译：本公开提供了诸如无源器件的集成电路结构中的通孔的系统，方法和装置。一方面，集成无源器件包括在第一导电迹线上的第一导电迹线和第二导电迹线，在第一导电迹线的一部分和第二导电迹线之间具有层间电介质。在层间电介质中提供一个或多个通孔以提供第一导电迹线和第二导电迹线之间的电连接。通孔的宽度大于至少一个导电迹线的宽度。

27. 发明授权

US08508301B2 Three dimensional inductor, transformer and radio frequency amplifier 有权
标题翻译：三维电感，变压器和射频放大器
公开(公告)号：US08508301B2
公开(公告)日：2013-08-13
申请号：US13294351
申请日：2011-11-11
申请人： Jonghae Kim , Shiqun Gu , Brian Matthew Henderson , Thomas R. Toms , Lew G. Chua-Eoan , Seyfollah S. Bazarjani , Matthew Nowak
发明人： Jonghae Kim , Shiqun Gu , Brian Matthew Henderson , Thomas R. Toms , Lew G. Chua-Eoan , Seyfollah S. Bazarjani , Matthew Nowak
IPC分类号： H03F3/14
CPC分类号： H01L28/10 , H01F17/0013 , H01F19/04 , H01F2017/002 , H01L23/481 , H01L23/5227 , H01L27/0207 , H01L2224/16145 , H01L2924/3011
摘要： A three dimensional on-chip radio frequency amplifier is disclosed that includes first and second transformers and a first transistor. The first transformer includes first and second inductively coupled inductors. The second transformer includes third and fourth inductively coupled inductors. Each inductor includes multiple first segments in a first metal layer; multiple second segments in a second metal layer; first and second inputs, and multiple through vias coupling the first and second segments to form a continuous path between the first and second inputs. The first input of the first inductor is coupled to an amplifier input; the first input of the second inductor is coupled to the first transistor gate; the first input of the third inductor is coupled to the first transistor drain, the first input of the fourth inductor is coupled to an amplifier output. The second inductor inputs and the first transistor source are coupled to ground.
摘要翻译：公开了一种三维片上射频放大器，其包括第一和第二变压器和第一晶体管。第一变压器包括第一和第二电感耦合电感器。第二变压器包括第三和第四电感耦合电感器。每个电感器包括在第一金属层中的多个第一段; 第二金属层中的多个第二段; 第一和第二输入以及耦合第一和第二段的多通孔，以形成第一和第二输入之间的连续路径。第一电感器的第一输入耦合到放大器输入端; 第二电感器的第一输入耦合到第一晶体管栅极; 第三电感器的第一输入耦合到第一晶体管漏极，第四电感器的第一输入耦合到放大器输出端。第二电感器输入和第一晶体管源耦合到地。

28. 发明申请

US20130134838A1 PIEZOELECTRIC MEMS TRANSFORMER 审中-公开
标题翻译：压电MEMS变压器
公开(公告)号：US20130134838A1
公开(公告)日：2013-05-30
申请号：US13305293
申请日：2011-11-28
申请人： Changhan Hobie Yun , Chi Shun Lo , Chengjie Zuo , Jonghae Kim
发明人： Changhan Hobie Yun , Chi Shun Lo , Chengjie Zuo , Jonghae Kim
IPC分类号： H01L41/107 , H01L41/22
CPC分类号： H01L41/107 , H01L41/047 , H03H9/02228 , Y10T29/42
摘要： This disclosure provides implementations of electromechanical systems piezoelectric resonator transformers, devices, apparatus, systems, and related processes. In one aspect, a transformer includes a piezoelectric layer; a first conductive layer arranged over a first surface of the piezoelectric layer including a first set of electrodes and a second set of electrodes interdigitated with the first set. The transformer includes a second conductive layer arranged over a second surface including at least a third set of electrodes. In some implementations, the transformer includes a first port capable of receiving an input signal and to which the first set of electrodes are coupled, and a second port capable of being coupled to a load and of outputting an output signal, the second set of electrodes being coupled to the second port. Generally, a ratio of the number of electrodes of the second set to the first set characterizes a transformation ratio.
摘要翻译：本公开提供了机电系统压电谐振器变压器，装置，装置，系统和相关过程的实现。一方面，变压器包括压电层; 布置在压电层的第一表面上的第一导电层，包括第一组电极和与第一组交叉的第二组电极。变压器包括布置在包括至少第三组电极的第二表面上的第二导电层。在一些实施方式中，变压器包括能够接收输入信号并且第一组电极被耦合的第一端口和能够耦合到负载并输出输出信号的第二端口，第二组电极耦合到第二端口。通常，第二组的电极数与第一组的比例表示变换比。

29. 发明申请

US20130120951A1 STACKED CMOS CHIPSET HAVING AN INSULATING LAYER AND A SECONDARY LAYER AND METHOD OF FORMING SAME 有权
标题翻译：具有绝缘层和二次层的堆叠CMOS芯片及其形成方法
公开(公告)号：US20130120951A1
公开(公告)日：2013-05-16
申请号：US13356717
申请日：2012-01-24
申请人： Chengjie Zuo , Changhan Yun , Sang-June Park , Chi Shun Lo , Mario F. Velez , Jonghae Kim
发明人： Chengjie Zuo , Changhan Yun , Sang-June Park , Chi Shun Lo , Mario F. Velez , Jonghae Kim
IPC分类号： H05K1/03 , H01L21/60 , H05K7/06 , H01L21/58
CPC分类号： H01L27/0688 , H01L2224/18
摘要： A chipset includes a sheet of glass, quartz or sapphire and a first wafer having at least one first circuit layer on a first side of a first substrate layer. The first wafer is connected to the sheet such that the at least one first circuit layer is located between the first substrate layer and the sheet. A second wafer having at least one second circuit layer on a first side of a second substrate layer is connected to the first substrate layer such that the at least one second circuit layer is located between the second substrate layer and the first substrate layer. Also a method of forming a chipset.
摘要翻译：芯片组包括玻璃板，石英或蓝宝石片，以及在第一基底层的第一面上具有至少一个第一电路层的第一晶片。第一晶片连接到片材，使得至少一个第一电路层位于第一基片层和片之间。具有在第二衬底层的第一侧上的至少一个第二电路层的第二晶片连接到第一衬底层，使得至少一个第二电路层位于第二衬底层和第一衬底层之间。还有一种形成芯片组的方法。

30. 发明申请

US20130113076A1 METAL-SEMICONDUCTOR WAFER BONDING FOR HIGH-Q DEVICES 有权
公开(公告)号：US20130113076A1
公开(公告)日：2013-05-09
申请号：US13293075
申请日：2011-11-09
申请人： Changhan YUN , Chengjie Zuo , Chi Shun Lo , Jonghae Kim , Mario F. Velez
发明人： Changhan YUN , Chengjie Zuo , Chi Shun Lo , Jonghae Kim , Mario F. Velez
IPC分类号： H01L21/02 , H01L29/92
CPC分类号： H01L29/66174 , H01G4/1272 , H01G4/33 , H01L28/40 , H01L28/75
摘要： Methods and apparatus for metal semiconductor wafer bonding for high-Q devices are provided. An exemplary capacitor includes a first plate formed on a glass substrate, a second plate, and a dielectric layer. No organic bonding agent is used between the first plate and the glass substrate, and the dielectric layer can be an intrinsic semiconductor. A extrinsic semiconductor layer that is heavily doped contacts the dielectric layer. The dielectric and extrinsic semiconductor layers are sandwiched between the first and second plates. An intermetallic layer is formed between the first plate and the dielectric layer. The intermetallic layer is thermo compression bonded to the first plate and the dielectric layer. The capacitor can be coupled in a circuit as a high-Q capacitor and/or a varactor, and can be integrated with a mobile device.

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