专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

21. 发明授权

US07392415B2 Sleep protection 有权
标题翻译：睡眠保护
公开(公告)号：US07392415B2
公开(公告)日：2008-06-24
申请号：US10185887
申请日：2002-06-26
申请人： David W. Grawrock , David I. Poisner
发明人： David W. Grawrock , David I. Poisner
IPC分类号： G06F1/32
CPC分类号： G06F21/57 , G06F21/79
摘要： Methods, apparatus and machine-readable medium are described that attempt to protect secrets from sleep attacks. In some embodiments, the secrets are encrypted and a security enhanced environment dismantled prior to entering a sleep state. Some embodiments further re-establish a security enhanced environment and decrypt the secrets in response to a wake event.
摘要翻译：描述了尝试保护秘密免于睡眠攻击的方法，装置和机器可读介质。在一些实施例中，秘密被加密，并且在进入睡眠状态之前拆除安全增强的环境。一些实施例进一步重新建立安全增强环境并且响应于唤醒事件来解密秘密。

22. 发明授权

US06920535B1 Accessing multi-ported memory for uncached status and control accesses 失效
标题翻译：访问多端口存储器用于非缓存状态和控制访问
公开(公告)号：US06920535B1
公开(公告)日：2005-07-19
申请号：US09672345
申请日：2000-09-28
申请人： David I. Poisner
发明人： David I. Poisner
IPC分类号： G06F12/08 , G06F13/00
CPC分类号： G06F12/0897 , G06F12/08
摘要： A computer system comprising multi-ported memory electrically coupled to a central processing unit and a peripheral device. The central processing unit and the peripheral device access the multi-ported memory independently.
摘要翻译：一种包括电连接到中央处理单元和外围设备的多端口存储器的计算机系统。中央处理单元和外围设备独立访问多端口存储器。

23. 发明授权

US06738848B2 Decoder-based circuitry for sharing an interrupt between disk drive interfaces 有权
标题翻译：用于在磁盘驱动器接口之间共享中断的基于解码器的电路
公开(公告)号：US06738848B2
公开(公告)日：2004-05-18
申请号：US09751095
申请日：2000-12-29
申请人： David I. Poisner , Louis A. Lippincott
发明人： David I. Poisner , Louis A. Lippincott
IPC分类号： G06F1324
CPC分类号： G06F3/0607 , G06F3/0658 , G06F3/0674 , G06F13/24
摘要： An apparatus for sharing an interrupt between a controller for a parallel storage device interface and a controller for a serial storage device interface includes interrupt conditioning circuitry that masks an interrupt signal coming from the parallel storage device interface if no storage device is coupled to the parallel storage device interface. The masking of the parallel storage device interface interrupt of no storage device is coupled to the parallel storage device interface allows the controller for the serial storage device interface to share the interrupt traditionally assigned to the parallel storage device interface.
摘要翻译：用于在用于并行存储设备接口的控制器和用于串行存储设备接口的控制器之间共享中断的设备包括：中断调节电路，其屏蔽来自并行存储设备接口的中断信号，如果没有存储设备耦合到并行存储器设备接口没有存储设备的并行存储设备接口中断的屏蔽耦合到并行存储设备接口，允许串行存储设备接口的控制器共享传统分配给并行存储设备接口的中断。

24. 发明授权

US06581173B2 Method and apparatus for verifying that data stored in a memory has not been corrupted 失效
标题翻译：用于验证存储在存储器中的数据未被破坏的方法和装置
公开(公告)号：US06581173B2
公开(公告)日：2003-06-17
申请号：US09844927
申请日：2001-04-26
申请人： David I. Poisner
发明人： David I. Poisner
IPC分类号： G11C2900
CPC分类号： G06F11/1497 , G06F11/1004 , G06F11/14
摘要： An integrated circuit device includes dedicated memory verification logic to compare data read from a set of cells in a memory at a first time to data read from the same set of memory cells at a second time.
摘要翻译：集成电路装置包括专用存储器验证逻辑，用于将从第一时间存储器中的一组单元读取的数据与第二次从同一组存储器单元读取的数据进行比较。

25. 发明授权

US06564330B1 Wakeup circuit for computer system that enables codec controller to generate system interrupt in response to detection of a wake event by a codec 有权
标题翻译：用于计算机系统的唤醒电路，使得编解码器控制器能够响应于由编解码器检测到唤醒事件而产生系统中断
公开(公告)号：US06564330B1
公开(公告)日：2003-05-13
申请号：US09472096
申请日：1999-12-23
申请人： Alberto J. Martinez , David I. Poisner , Karthi R. Vadivelu
发明人： Alberto J. Martinez , David I. Poisner , Karthi R. Vadivelu
IPC分类号： G06F126
CPC分类号： G06F1/24
摘要： A wake up circuit for a computer system with a codec controller. The circuit provides a wakeup signal to the computer system when a codec detects an event that requires the system to become active. This signal is provided whether the communications link between the codecs and their controller is active or inactive. When the link is inactive, as indicated by the absence of a bit clock, a data signal on any of the codec input lines triggers the controller to send a power activation signal to the system and to initiate an activation of the codec link. If the link is already active, the general purpose input status change bit is transmitted to the controller, which writes it into a register that is used to trigger a power activation signal to the system. An enable input permits the wakeup signal to be enabled or disabled under program control. The wakeup signal can be used to trigger a system management interrupt or other interrupt suitable for initiating a system resume function.
摘要翻译：用于具有编解码器控制器的计算机系统的唤醒电路。当编解码器检测到需要系统激活的事件时，该电路向计算机系统提供唤醒信号。提供该信号是否编解码器与其控制器之间的通信链路是活动的还是非活动的。当链路处于非活动状态时，如没有位时钟所示，任何编解码器输入线上的数据信号触发控制器向系统发送电源激活信号并启动编解码器链路的激活。如果链路已经处于活动状态，则通用输入状态改变位被发送到控制器，控制器将其写入用于触发系统功率激活信号的寄存器。启用输入允许在程序控制下启用或禁用唤醒信号。唤醒信号可用于触发适用于启动系统恢复功能的系统管理中断或其他中断。

26. 发明授权

US06421765B1 Method and apparatus for selecting functional space in a low pin count memory device 有权
标题翻译：用于在低引脚数存储器件中选择功能空间的方法和装置
公开(公告)号：US06421765B1
公开(公告)日：2002-07-16
申请号：US09340498
申请日：1999-06-30
申请人： David I. Poisner
发明人： David I. Poisner
IPC分类号： G06F1300
CPC分类号： G06F12/06
摘要： The present invention is an apparatus and method for selecting one of a first and a second storage element in response to a control signal issued by a processor in a low pin count device. The apparatus comprises a decoder to receive the control signal and an address signal having a select bit indicative of one of the first and the second storage elements. The decoder generates a select signal to access one of the first and the second storage elements based on the select bit.
摘要翻译：本发明是一种用于响应由处理器在低引脚数设备中发出的控制信号来选择第一和第二存储元件之一的装置和方法。该装置包括一个解码器，用于接收控制信号和一个具有指示第一和第二存储元件之一的选择位的地址信号。解码器基于选择位产生选择信号以访问第一和第二存储元件之一。

27. 发明授权

US5890012A System for programming peripheral with address and direction information and sending the information through data bus or control line when DMA controller asserts data knowledge line 失效
标题翻译：用于通过地址和方向信息编程外设的系统，并在DMA控制器断言数据知识行时通过数据总线或控制线发送信息
公开(公告)号：US5890012A
公开(公告)日：1999-03-30
申请号：US428572
申请日：1995-04-25
申请人： David I. Poisner
发明人： David I. Poisner
IPC分类号： G06F13/28 , G06F13/14 , G06F15/16
CPC分类号： G06F13/28
摘要： A slave DMA peripheral achieves the functionalities of a bus master without incurring the costs of additional address and control lines. Information regarding buffers to be accessed is loaded in the peripheral from the CPU. Actual buffer addresses, length values, and direction information are later programmed into the DMA controller by the peripheral. The present invention manages communication between the peripheral and main memory through the DMA controller. This allows the peripheral to access buffers in memory using a minimal number of lines.
摘要翻译：辅助DMA外设实现总线主机的功能，而不会产生附加地址和控制线的成本。有关要访问的缓冲区的信息从CPU加载到外设中。实际缓冲区地址，长度值和方向信息随后由外设编程到DMA控制器中。本发明通过DMA控制器管理外围和主存储器之间的通信。这允许外设使用最少数量的行访问存储器中的缓冲区。

28. 发明申请

US20120272090A1 SYSTEM RECOVERY USING EXTERNAL COMMUNICATION DEVICE 有权
标题翻译：系统恢复使用外部通信设备
公开(公告)号：US20120272090A1
公开(公告)日：2012-10-25
申请号：US13091912
申请日：2011-04-21
申请人： David I. Poisner
发明人： David I. Poisner
IPC分类号： G06F11/08
CPC分类号： G06F11/1415 , G06F11/3006 , G06F11/3055
摘要： A method for computer system recovery is presented. In one embodiment, the method includes establishing a connection, via an interface, to a computer system to support the system recovery of the computer system. The method includes executing an emulation application as a recovery agent. The method includes retrieving, based on identifiers associated with the computer system, remote data via another interface. The method further includes performing the system recovery by using at least a part of the remote data.
摘要翻译：介绍了一种计算机系统恢复方法。在一个实施例中，该方法包括经由接口建立到计算机系统的连接以支持计算机系统的系统恢复。该方法包括执行仿真应用程序作为恢复代理。该方法包括基于与计算机系统相关联的标识符，经由另一接口检索远程数据。该方法还包括通过使用远程数据的至少一部分来执行系统恢复。

29. 发明授权

US07783809B2 Virtualization of pin functionality in a point-to-point interface 有权
标题翻译：在点对点接口中实现引脚功能的虚拟化
公开(公告)号：US07783809B2
公开(公告)日：2010-08-24
申请号：US11173643
申请日：2005-06-30
申请人： Keshavan K. Tiruvallur , David I. Poisner , Herbert H. J. Hum , Frank Binns , David L. Hill , Robert J. Greiner , Raymond S. Tetrick
发明人： Keshavan K. Tiruvallur , David I. Poisner , Herbert H. J. Hum , Frank Binns , David L. Hill , Robert J. Greiner , Raymond S. Tetrick
IPC分类号： G06F13/24 , G06F13/32
CPC分类号： G06F17/5068 , G06F17/5045
摘要： Architectures and techniques that allow legacy pin functionality to be replaced with a “virtual wire” that may communicate information that would otherwise be communicated by a wired interface. A message may be passed between a system controller and a processor that includes a virtual wire value and a virtual wire change indicator. The virtual wire value may include a signal corresponding to one or more pins that have been eliminated from the physical interface and the virtual wire change value may include an indication of whether the virtual wire value has changed. The combination of the virtual wire value and the virtual wire change indicator may allow multiple physical pins to be replaced by message values.
摘要翻译：允许传统引脚功能被替换为“虚拟线”的架构和技术，“虚拟线”可以传达否则将由有线接口传送的信息。可以在系统控制器和包括虚拟线路值和虚拟换线指示器的处理器之间传递消息。虚拟线值可以包括对应于已经从物理接口消除的一个或多个引脚的信号，并且虚拟线更改值可以包括虚拟线值是否已经改变的指示。虚拟线路值和虚拟线路变化指示器的组合可以允许多个物理引脚被消息值替换。

30. 发明授权

US07400554B2 Automatic read of current time when exiting low-power state 有权
标题翻译：自动读取当前时间退出低功耗状态
公开(公告)号：US07400554B2
公开(公告)日：2008-07-15
申请号：US10037184
申请日：2002-01-02
申请人： David I. Poisner
发明人： David I. Poisner
IPC分类号： G04F10/08
CPC分类号： G06F9/4843 , G06F9/4893 , Y02D10/24
摘要： A method and apparatus is described for computing a duration of a reduced power consumption state. A time of exiting from the reduced power consumption state is read prior to an execution of an interrupt routine. The read time of exiting is then stored in a register and a calculation of a reduced power consumption state duration may be performed.
摘要翻译：描述了用于计算降低功耗状态的持续时间的方法和装置。在执行中断程序之前，读取从降低功耗状态退出的时间。然后将读出的时间存储在寄存器中，并且可以执行降低的功耗状态持续时间的计算。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式