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21. 发明授权

US5576991A Multistepped threshold convergence for a flash memory array 失效
标题翻译：闪存阵列的多级阈值收敛
公开(公告)号：US5576991A
公开(公告)日：1996-11-19
申请号：US269540
申请日：1994-07-01
申请人： Nader Radjy , Lee E. Cleveland , Jian Chen , Shane C. Hollmer
发明人： Nader Radjy , Lee E. Cleveland , Jian Chen , Shane C. Hollmer
IPC分类号： G11C17/00 , G11C16/02 , G11C16/16 , G11C16/34 , G11C11/40
CPC分类号： G11C16/3409 , G11C16/16 , G11C16/3404
摘要： A method of converging threshold voltages of memory cells in a flash EEPROM array after the memory cells have been erased, the method including applying a gate voltage having an initial negative value which is increased to a more positive value in steps during application of a drain disturb voltage. By applying a gate voltage with an initial negative value, leakage current during convergence is reduced enabling all cells on bit lines of the array to be converged in parallel.
摘要翻译：一种在存储器单元被擦除之后在闪存EEPROM阵列中会聚存储器单元的阈值电压的方法，该方法包括在施加漏极干扰期间施加具有初始负值的栅极电压，其逐步增加到更多的正值电压。通过施加具有初始负值的栅极电压，减小了会聚期间的漏电流，使得阵列的位线上的所有单元能够并行收敛。

22. 发明授权

US5511026A Boosted and regulated gate power supply with reference tracking for multi-density and low voltage supply memories 失效
标题翻译：增强和调节的门电源，具有多密度和低电压电源存储器的参考跟踪
公开(公告)号：US5511026A
公开(公告)日：1996-04-23
申请号：US160578
申请日：1993-12-01
申请人： Lee E. Cleveland , Shane C. Hollmer
发明人： Lee E. Cleveland , Shane C. Hollmer
IPC分类号： G11C17/00 , G11C11/56 , G11C16/02 , G11C16/06 , G11C16/08 , G11C16/30 , H01L21/822 , H01L27/04 , G11C7/00 , H03L1/00
CPC分类号： G11C11/5621 , G11C16/08 , G11C16/30 , G11C5/145 , G11C8/14
摘要： A gate power supply for supplying power to the gates of flash EEPROM memory cells in a multi-density or low voltage supply memory array to determine the states stored by the memory cells. The gate power supply includes a multi-phase voltage pump to increase voltage supplied to the gates of the memory cells above a system voltage supply, V.sub.CC to increase the working margin between memory cell states. The gate power supply further includes a low power supply standby pump to maintain the boosted voltage during an inactive mode. The wordline decoder for the memory is divided into sections with a large n-well parasitic capacitance of each decoder section acting as a reservoir to store the charge supplied by the low power standby pump. In an active mode, the parasitic capacitance in unselected decoder sections supplies power to the input of the selected diecoder section while the multi-phase pump is turning on. Zener regulation diodes are coupled to the inputs of each decoder section to regulate the voltage supplied to each section. A reference supply feeds back power from the input of the selected decoder section to the input of a reference array. The reference supply further provides circuitry to reduce mismatches between the memory array and the reference array.
摘要翻译：一种用于向多密度或低电压电源存储器阵列中的快速EEPROM存储单元的栅极供电以确定存储单元存储的状态的栅极电源。栅极电源包括多相电压泵，以增加提供给系统电压源上方的存储器单元的栅极的电压，以增加存储单元状态之间的工作裕度。栅极电源还包括低功率备用泵，以在非活动模式期间维持升压电压。用于存储器的字线解码器被分成具有作为存储器的每个解码器部分的大n阱寄生电容的部分，以存储由低功率备用泵提供的电荷。在活动模式中，未选择解码器部分中的寄生电容在多相泵接通时向所选择的解码器部分的输入端供电。齐纳调节二极管耦合到每个解码器部分的输入以调节提供给每个部分的电压。参考电源将功率从所选择的解码器部分的输入反馈到参考阵列的输入。参考电源还提供减少存储器阵列和参考阵列之间不匹配的电路。

23. 发明授权

US5406517A Distributed negative gate power supply 失效
标题翻译：分布式负栅极电源
公开(公告)号：US5406517A
公开(公告)日：1995-04-11
申请号：US109881
申请日：1993-08-23
申请人： Chung K. Chang , Johnny C. Chen , Michael A. Van Buskirk , Lee E. Cleveland
发明人： Chung K. Chang , Johnny C. Chen , Michael A. Van Buskirk , Lee E. Cleveland
IPC分类号： G11C17/00 , G11C16/06 , G11C16/30 , G11C13/00
CPC分类号： G11C16/30
摘要： A distributed negative gate power supply for generating and selectively supplying a relatively high negative voltage to control gates of memory cells in selected half-sectors via wordlines in an array of flash EEPROM memory cells during flash erasure. The distributed negative gate power supply includes a main charge pumping circuit (20a, 20b), a plurality of distribution sector pumping means (18a-18p). Each of the plurality of distribution sector pumping circuits is responsive to a half-sector select signal for selectively connecting the primary negative voltage to the wordlines of the selected half-sectors.
摘要翻译：一种分布式负栅极电源，用于在闪速擦除期间，通过闪存EEPROM存储单元阵列中的字线产生并选择性地向所选择的半扇区中的存储单元的控制栅极提供相对较高的负电压。分布式负栅极电源包括主电荷泵浦电路（20a，20b），多个分配扇区泵送装置（18a-18p）。多个分配扇区泵浦电路中的每一个响应于半扇区选择信号，用于选择性地将初级负电压连接到所选择的半扇区的字线。

24. 发明授权

US5376835A Power-on reset circuit 失效
标题翻译：上电复位电路
公开(公告)号：US5376835A
公开(公告)日：1994-12-27
申请号：US964806
申请日：1992-10-22
申请人： Michael A. Van Buskirk , Johnny C.-L. Chen , Chung K. Chang , Lee E. Cleveland , Antonio Montalvo
发明人： Michael A. Van Buskirk , Johnny C.-L. Chen , Chung K. Chang , Lee E. Cleveland , Antonio Montalvo
IPC分类号： H03K17/22 , H03K5/153 , H03K17/687
CPC分类号： H03K17/223
摘要： A power-on reset circuit for generating and maintaining a reset signal in an active low state during power-up until a power supply voltage exceeds a predetermined level includes a resetting circuit (12a) and a control logic circuit (12b). The reset circuit is responsive to a monitoring signal, a start-up signal and a reference voltage for generating a reset signal which is initially in the active low state. The reset circuit includes a differential comparator (54) having a first input for receiving the start-up signal, a second input for receiving the reference voltage, and an output for generating the reset signal. The control logic circuit is responsive to the monitoring signal and the reset signal for generating a logic control signal which is initially in a high state. The differential comparator is responsive to the control signal and is activated only after the power supply voltage has exceeded a predetermined level so as to maintain initially the reset signal on its output in the low state. The output of the differential comparator is forced to a high state after the monitoring signal has reached a low state and the start-up signal exceeds the reference voltage. Logic and/or memory circuitry (18) is provided which responds to the reset signal so as to force its outputs to a known logic state.
摘要翻译：一种用于在上电期间产生并维持处于低电平状态的复位信号，直到电源电压超过预定电平的上电复位电路包括复位电路（12a）和控制逻辑电路（12b）。复位电路响应于监视信号，启动信号和用于产生初始处于低电平状态的复位信号的参考电压。复位电路包括差分比较器（54），其具有用于接收启动信号的第一输入端，用于接收基准电压的第二输入端和用于产生复位信号的输出端。控制逻辑电路响应于监视信号和复位信号，用于产生最初处于高状态的逻辑控制信号。差分比较器响应于控制信号，并且仅在电源电压已经超过预定电平后被激活，以便将其输出上的复位信号初始化为低状态。在监视信号达到低电平并且启动信号超过参考电压之后，差分比较器的输出被强制为高电平。提供逻辑和/或存储器电路（18），其响应于复位信号，以便将其输出强制到已知的逻辑状态。

25. 发明授权

US5365484A Independent array grounds for flash EEPROM array with paged erase architechture 失效
标题翻译：具有分页擦除架构的闪存EEPROM阵列的独立阵列接地
公开(公告)号：US5365484A
公开(公告)日：1994-11-15
申请号：US109887
申请日：1993-08-23
申请人： Lee E. Cleveland , Michael A. Van Buskirk , Johhny C. Chen , Chung K. Chang
发明人： Lee E. Cleveland , Michael A. Van Buskirk , Johhny C. Chen , Chung K. Chang
IPC分类号： G11C17/00 , G11C16/06 , G11C16/16 , G11C16/30 , G11C13/00
CPC分类号： G11C16/16 , G11C16/30
摘要： An improved architecture for an array of flash EEPROM cells with paged erase is provided. The array is formed of a plurality of half-sectors. In each sector, the sources of the memory cell transistors are connected to a separate individual ground line. A ground line circuit is provided for generating a half-sector ground line signal. The separate individual ground line is connected to the ground line circuit for receiving the half-sector ground line signal which is at a predetermined positive potential during erase.
摘要翻译：提供了一种用于具有分页擦除的快闪EEPROM单元阵列的改进的架构。阵列由多个半扇区形成。在每个扇区中，存储单元晶体管的源极连接到单独的单独接地线。提供用于产生半扇区接地线信号的接地线电路。单独的单独地线连接到接地线电路，用于接收在擦除期间处于预定正电位的半扇区接地线信号。

26. 发明授权

US5359558A Flash eeprom array with improved high endurance 失效
标题翻译：闪光eeprom阵列具有改善的高耐力
公开(公告)号：US5359558A
公开(公告)日：1994-10-25
申请号：US109886
申请日：1993-08-23
申请人： Chung K. Chang , Johnny C. Chen , Michael A. Van Buskirk , Lee E. Cleveland
发明人： Chung K. Chang , Johnny C. Chen , Michael A. Van Buskirk , Lee E. Cleveland
IPC分类号： G11C17/00 , G11C16/02 , G11C16/04 , G11C16/06 , G11C16/10 , G11C16/28 , G11C16/34 , H01L27/10 , G11C11/40
CPC分类号： G11C16/3409 , G11C16/10 , G11C16/28 , G11C16/3404
摘要： An improved over-erased bit correction structure is provided for performing a correction operation on over-erased memory cells in an array of flash EEPROM memory cells after erase operation so as to render high endurance. Sensing circuitry (20) is used to detect column leakage current indicative of an over-erased bit during an APDE mode of operation and for generating a logic signal representative of data stored in the memory cell. A data input buffer circuit (26) is used to compare the logic signal and a data signal representative of data programmed in the memory cell so as to generate a bit match signal. A pulse counter (30) is coupled to the data input buffer circuit for counting a plurality of programming pulses applied thereto. The data input buffer circuit selectively connects only certain ones of the columns of bit lines to the pulse counter in which the bit match signal is at a high logic level so as to program back over-erased memory cells connected to only the certain ones of the columns of bit lines.
摘要翻译：提供了一种改进的过擦除位校正结构，用于对擦除操作之后的快闪EEPROM存储单元阵列中的擦除过的存储器单元执行校正操作，以使其具有高耐久性。感测电路（20）用于在APDE操作模式期间检测指示过擦除位的列泄漏电流，并用于产生表示存储在存储单元中的数据的逻辑信号。数据输入缓冲电路（26）用于比较逻辑信号和表示在存储器单元中编程的数据的数据信号，以产生位匹配信号。脉冲计数器（30）耦合到数据输入缓冲器电路，用于对施加到其上的多个编程脉冲进行计数。数据输入缓冲器电路仅选择性地将位线列中的某些列连接到脉冲计数器，其中比特匹配信号处于高逻辑电平，以便编程回只连接到仅某些位列列。

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