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21. 发明授权

US08156391B2 Data controlling in the MBIST chain architecture 失效
标题翻译： MBIST链架构中的数据控制
公开(公告)号：US08156391B2
公开(公告)日：2012-04-10
申请号：US12167305
申请日：2008-07-03
申请人： Alexandre Andreev , Anatoli Bolotov , Mikhail Grinchuk
发明人： Alexandre Andreev , Anatoli Bolotov , Mikhail Grinchuk
IPC分类号： G11C29/14 , G11C29/50
CPC分类号： G11C29/32 , G11C8/16 , G11C2029/3202
摘要： A memory collar including a first circuit and a second circuit. The first circuit may be configured to generate one or more data sequences in response to one or more test commands. The one or more data sequences may be presented to a memory during a test mode. The second circuit may be configured to pre-process one or more outputs generated by the memory in response to the one or more data sequences.
摘要翻译：一种包括第一电路和第二电路的存储器环。第一电路可以被配置为响应于一个或多个测试命令而生成一个或多个数据序列。在测试模式期间，可以将一个或多个数据序列呈现给存储器。第二电路可以被配置为响应于一个或多个数据序列预处理由存储器产生的一个或多个输出。

22. 发明申请

US20090300441A1 ADDRESS CONTROLLING IN THE MBIST CHAIN ARCHITECTURE 有权
标题翻译：地址控制在MBIST链建筑
公开(公告)号：US20090300441A1
公开(公告)日：2009-12-03
申请号：US12183562
申请日：2008-07-31
申请人： Alexandre Andreev , Anatoli Bolotov , Mikhail Grinchuk
发明人： Alexandre Andreev , Anatoli Bolotov , Mikhail Grinchuk
IPC分类号： G11C29/12 , G06F11/27
CPC分类号： G11C29/32 , G11C8/16 , G11C2029/3202
摘要： A memory collar includes a first circuit, a second circuit and a third circuit. The first circuit may be configured to generate a first control signal, a second control signal and a third control signal in response to one or more test commands. The second circuit may be configured to generate a fourth control signal in response to said third control signal and the fourth control signal. The third circuit may be configured to generate one or more address sequences. The one or more address sequences are presented to a memory during a test mode.
摘要翻译：存储器环包括第一电路，第二电路和第三电路。第一电路可以被配置为响应于一个或多个测试命令产生第一控制信号，第二控制信号和第三控制信号。第二电路可以被配置为响应于所述第三控制信号和第四控制信号而产生第四控制信号。第三电路可以被配置为生成一个或多个地址序列。在测试模式期间将一个或多个地址序列呈现给存储器。

23. 发明申请

US20060129874A1 Master controller architecture 失效
标题翻译：主控制器架构
公开(公告)号：US20060129874A1
公开(公告)日：2006-06-15
申请号：US10999720
申请日：2004-11-30
申请人： Alexandre Andreev , Sergey Gribok , Anatoli Bolotov
发明人： Alexandre Andreev , Sergey Gribok , Anatoli Bolotov
IPC分类号： G06F11/00
CPC分类号： G11C29/16 , G11C29/44 , G11C29/4401 , G11C29/72
摘要： A master controller for an RRAM subsystem. An interface communicates with at least one RRAM controller. A main control unit selects and implements test and repair operations on the RRAM subsystem through the RRAM controller. A timer determines a maximum number of test and repair operations that can be implemented within a given time. Thus, a master controller is included in the RRAM subsystem. The master controller has a relatively simple interface, and performs test and repair operations on the RRAM subsystem. The advantages of using the master controller include an elimination of additional test ports, simplification of the process of preparing the test vectors for RRAM testing, and the master controller is able to accumulate test results and initiate repairs based on those results. In this manner, the RRAM subsystem has a self-repair functionality.
摘要翻译：用于RRAM子系统的主控制器。接口与至少一个RRAM控制器通信。主控单元通过RRAM控制器对RRAM子系统进行测试和修复操作。定时器确定在给定时间内可以实现的最大测试和修复操作数。因此，主控制器包含在RRAM子系统中。主控制器具有相对简单的接口，并对RRAM子系统执行测试和修复操作。使用主控制器的优点包括消除额外的测试端口，简化了用于RRAM测试的测试向量的准备过程，并且主控制器能够根据这些结果积累测试结果并启动修复。以这种方式，RRAM子系统具有自修复功能。

24. 发明授权

US08312072B2 Universal Galois field multiplier 有权
标题翻译：通用伽罗瓦域乘法器
公开(公告)号：US08312072B2
公开(公告)日：2012-11-13
申请号：US12211268
申请日：2008-09-16
申请人： Sergei B. Gashkov , Alexandre Andreev
发明人： Sergei B. Gashkov , Alexandre Andreev
IPC分类号： G06F7/72
CPC分类号： G06F7/724
摘要： An apparatus including a multiplier circuit and a multiplexing circuit. The multiplier circuit may be configured to multiply a first multiplicand and a second multiplicand based on a programmable base value and generate a plurality of intermediate values, each intermediate value representing a result of the multiplication reduced by a respective irreducible polynomial. The multiplexing circuit may be configured to generate an output in response to the plurality of intermediate values received from the multiplier circuit and the programmable base value.
摘要翻译：一种包括乘法器电路和复用电路的装置。乘法器电路可以被配置为基于可编程基值乘以第一被乘数和第二被乘数，并且生成多个中间值，每个中间值表示乘法的结果减去相应的不可约多项式。复用电路可以被配置为响应于从乘法器电路接收的多个中间值和可编程基值产生输出。

25. 发明申请

US20090307543A1 TRANSPORT SUBSYSTEM FOR AN MBIST CHAIN ARCHITECTURE 失效
标题翻译：用于MBIST链架构的运输子系统
公开(公告)号：US20090307543A1
公开(公告)日：2009-12-10
申请号：US12183512
申请日：2008-07-31
申请人： Alexandre Andreev , Anatoli Bolotov , Mikhail Grinchuk
发明人： Alexandre Andreev , Anatoli Bolotov , Mikhail Grinchuk
IPC分类号： G11C29/12 , G06F11/27
CPC分类号： G11C29/48 , G11C29/1201 , G11C29/26 , G11C29/32 , G11C2029/2602 , G11C2029/5602
摘要： An apparatus comprising a controller, a plurality of transport circuits and a plurality of memory-controlling circuits. The controller may be configured to (i) present one or more commands and (ii) receive one or more responses. Each of the plurality of transport circuits may be configured to (i) receive one of the commands, (ii) present the responses, and (iii) generate one or more control signals. Each of the plurality of memory-controlling circuits may be (i) coupled to a respective one of the plurality of transport circuits and (ii) configured to (i) generate one or more memory access signals in response to the one or more control signals, (ii) receive one or more memory output signals from a respective memory in response to the one or more memory access signals and (iii) generate the responses in response to the one or more memory output signals. Each respective memory may be independently sized. The controller generally provides a common testing routine for each respective memory that may be adjusted for the size of each respective memory by the memory-controlling circuits.
摘要翻译：一种装置，包括控制器，多个传输电路和多个存储器控制电路。控制器可以被配置为（i）呈现一个或多个命令，并且（ii）接收一个或多个响应。多个传输电路中的每一个可以被配置为（i）接收命令之一，（ii）呈现响应，以及（iii）产生一个或多个控制信号。多个存储器控制电路中的每一个可以（i）耦合到多个传输电路中的相应一个，并且（ii）被配置为（i）响应于一个或多个控制信号而产生一个或多个存储器访问信号，（ii）响应于所述一个或多个存储器访问信号，从相应存储器接收一个或多个存储器输出信号，以及（iii）响应于所述一个或多个存储器输出信号产生响应。各个存储器可以独立地定尺寸。控制器通常为每个相应的存储器提供通用的测试程序，这些存储器可以通过存储器控制电路为每个相应的存储器的大小进行调整。

26. 发明申请

US20090300440A1 DATA CONTROLLING IN THE MBIST CHAIN ARCHITECTURE 失效
标题翻译：在MBIST链架构中的数据控制
公开(公告)号：US20090300440A1
公开(公告)日：2009-12-03
申请号：US12167305
申请日：2008-07-03
申请人： Alexandre Andreev , Anatoli Bolotov , Mikhail Grinchuk
发明人： Alexandre Andreev , Anatoli Bolotov , Mikhail Grinchuk
IPC分类号： G11C29/04 , G06F11/27
CPC分类号： G11C29/32 , G11C8/16 , G11C2029/3202
摘要： A memory collar including a first circuit and a second circuit. The first circuit may be configured to generate one or more data sequences in response to one or more test commands. The one or more data sequences may be presented to a memory during a test mode. The second circuit may be configured to pre-process one or more outputs generated by the memory in response to the one or more data sequences.
摘要翻译：一种包括第一电路和第二电路的存储器环。第一电路可以被配置为响应于一个或多个测试命令而生成一个或多个数据序列。在测试模式期间，可以将一个或多个数据序列呈现给存储器。第二电路可以被配置为响应于一个或多个数据序列预处理由存储器产生的一个或多个输出。

27. 发明申请

US20090282303A1 BUILT IN TEST CONTROLLER WITH A DOWNLOADABLE TESTING PROGRAM 有权
标题翻译：用可测试的测试程序构建测试控制器
公开(公告)号：US20090282303A1
公开(公告)日：2009-11-12
申请号：US12118477
申请日：2008-05-09
申请人： Alexandre Andreev , Anatoli A. Bolotov
发明人： Alexandre Andreev , Anatoli A. Bolotov
IPC分类号： G01R31/28
CPC分类号： G01R31/31724 , G11C5/04 , G11C29/16 , G11C2029/0401
摘要： An apparatus comprising a processor and an internal memory. The processor may be configured to test an external memory using (i) a netlist and (ii) a testing program. The internal memory may be configured to store the testing program. The testing program may be downloadable to the internal memory independently from the storing of the netlist.
摘要翻译：一种包括处理器和内部存储器的装置。处理器可以被配置为使用（i）网表和（ii）测试程序来测试外部存储器。内部存储器可以被配置为存储测试程序。测试程序可以独立于存储网表而被下载到内部存储器。

28. 发明授权

US08176397B2 Variable redundancy reed-solomon encoder 失效
标题翻译：可变冗余雷达独奏编码器
公开(公告)号：US08176397B2
公开(公告)日：2012-05-08
申请号：US12211985
申请日：2008-09-17
申请人： Pavel Panteleev , Alexandre Andreev , Elyar Gasanov , Ilya Neznanov
发明人： Pavel Panteleev , Alexandre Andreev , Elyar Gasanov , Ilya Neznanov
IPC分类号： G06F11/00
CPC分类号： H03M13/1515 , H03M13/2906 , H03M13/2942 , H03M13/6516
摘要： A fixed length Reed-Solomon encoder is configured to produce a first fixed number of redundant symbols. The fixed length Reed-Solomon encoder is configured with an encoding polynomial that is fixed. A symbol preprocessor maps each input data symbol to a transformed input data symbol. A symbol postprocessor maps a second fixed number of redundant symbols output from the fixed length Reed-Solomon encoder to a set of redundant symbols. The second fixed number of redundant symbols is less than the first fixed number of redundant symbols.
摘要翻译：固定长度的里德 - 所罗门编码器被配置为产生第一固定数量的冗余符号。固定长度Reed-Solomon编码器配置有固定的编码多项式。符号预处理器将每个输入数据符号映射到经变换的输入数据符号。符号后处理器将固定长度Reed-Solomon编码器输出的第二固定数量的冗余符号映射到一组冗余符号。第二固定数量的冗余符号小于第一固定数量的冗余符号。

29. 发明授权

US08046643B2 Transport subsystem for an MBIST chain architecture 失效
标题翻译：用于MBIST链架构的传输子系统
公开(公告)号：US08046643B2
公开(公告)日：2011-10-25
申请号：US12183512
申请日：2008-07-31
申请人： Alexandre Andreev , Anatoli Bolotov , Mikhail Grinchuk
发明人： Alexandre Andreev , Anatoli Bolotov , Mikhail Grinchuk
IPC分类号： G11C29/00 , G01R31/28
CPC分类号： G11C29/48 , G11C29/1201 , G11C29/26 , G11C29/32 , G11C2029/2602 , G11C2029/5602
摘要： An apparatus including a controller configured to present one or more commands and receive one or more responses, a plurality of transport circuits configured to receive one of the commands, present the responses, and generate one or more control signals, and a plurality of memory-controlling circuits, each coupled to a respective one of the plurality of transport circuits and configured to generate one or more memory access signals in response to the one or more control signals, receive one or more memory output signals from a respective memory in response to the one or more memory access signals, and generate the responses in response to the one or more memory output signals. Each respective memory may be independently sized. The controller generally provides a common testing routine for each respective memory that may be adjusted for the size of each respective memory by the memory-controlling circuits.
摘要翻译：一种装置，包括：控制器，被配置为呈现一个或多个命令并接收一个或多个响应;多个传输电路，被配置为接收命令中的一个，呈现响应，并产生一个或多个控制信号;以及多个存储器 - 控制电路，每个耦合到所述多个传输电路中的相应一个，并被配置为响应于所述一个或多个控制信号而产生一个或多个存储器访问信号，响应于所述控制电路响应于所述控制电路接收来自相应存储器的一个或多个存储器输出信号一个或多个存储器访问信号，并且响应于一个或多个存储器输出信号而产生响应。各个存储器可以独立地定尺寸。控制器通常为每个相应的存储器提供通用的测试程序，这些存储器可以通过存储器控制电路为每个相应的存储器的大小进行调整。

30. 发明申请

US20100070831A1 VARIABLE REDUNDANCY REED-SOLOMON ENCODER 失效
标题翻译：可变冗余冗余编码器
公开(公告)号：US20100070831A1
公开(公告)日：2010-03-18
申请号：US12211985
申请日：2008-09-17
申请人： Elyar Gasanov , Ilya Neznanov , Pavel Panteleev , Alexandre Andreev
发明人： Elyar Gasanov , Ilya Neznanov , Pavel Panteleev , Alexandre Andreev
IPC分类号： H03M13/15 , G06F11/07
CPC分类号： H03M13/1515 , H03M13/2906 , H03M13/2942 , H03M13/6516
摘要： A fixed length Reed-Solomon encoder is configured to produce a first fixed number of redundant symbols. The fixed length Reed-Solomon encoder is configured with an encoding polynomial that is fixed. A symbol preprocessor maps each input data symbol to a transformed input data symbol. A symbol postprocessor maps a second fixed number of redundant symbols output from the fixed length Reed-Solomon encoder to a set of redundant symbols. The second fixed number of redundant symbols is less than the first fixed number of redundant symbols.
摘要翻译：固定长度的里德 - 所罗门编码器被配置为产生第一固定数量的冗余符号。固定长度Reed-Solomon编码器配置有固定的编码多项式。符号预处理器将每个输入数据符号映射到经变换的输入数据符号。符号后处理器将固定长度Reed-Solomon编码器输出的第二固定数量的冗余符号映射到一组冗余符号。第二固定数量的冗余符号小于第一固定数量的冗余符号。

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