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21. 发明授权

US09417679B2 Adaptive connected standby for a computing device 有权
标题翻译：计算设备的自适应连接待机
公开(公告)号：US09417679B2
公开(公告)日：2016-08-16
申请号：US13674476
申请日：2012-11-12
申请人： Greg Sadowski , Alexander J. Branover , Maurice B. Steinman
发明人： Greg Sadowski , Alexander J. Branover , Maurice B. Steinman
IPC分类号： G06F1/32
CPC分类号： G06F1/3212 , G06F1/3287 , Y02D10/171 , Y02D10/174
摘要： Various computing devices and methods of managing the power consumption thereby are disclosed. In one aspect, a method of managing power consumption of a computing device that has a battery is provided. The method includes cycling the computing device between a connected standby active state and a connected standby idle state. The duration of the connected standby idle state is set based at least in part on a charge level of the battery.
摘要翻译：公开了各种计算设备和管理功耗的方法。一方面，提供一种管理具有电池的计算装置的功耗的方法。该方法包括在连接的待机活动状态和连接的待机空闲状态之间循环计算设备。连接的待机空闲状态的持续时间至少部分地基于电池的充电水平来设定。

22. 发明授权

US08924758B2 Method for SOC performance and power optimization 有权
标题翻译： SOC性能和功率优化方法
公开(公告)号：US08924758B2
公开(公告)日：2014-12-30
申请号：US13360012
申请日：2012-01-27
申请人： Maurice B. Steinman , Alexander J. Branover , Guhan Krishnan
发明人： Maurice B. Steinman , Alexander J. Branover , Guhan Krishnan
IPC分类号： G06F1/32
CPC分类号： G06F1/3243 , G06F1/324 , G06F1/3275 , G06F1/3296 , G06F9/5094 , Y02D10/126 , Y02D10/14 , Y02D10/172 , Y02D10/22
摘要： A system and method for efficient management of resources within a semiconductor chip for an optimal combination of power reduction and high performance. An intergrated circuit, such as a system on a chip (SOC), includes at least two processing units. The second processing unit includes a cache. The SOC includes a power management unit (PMU) that determines whether a first activity level for the first processing unit is above a first threshold and a second activity level for the second processing unit is below a second threshold. If this condition is true, then the PMU places a limit on a highest power-performance state (P-state) used by the second processing unit. The PMU sends an indication to flush the at least one cache within the second processing unit. The PMU changes a P-state used by the first processing unit to a higher performance P-state.
摘要翻译：一种用于有效管理半导体芯片内的资源以实现功率降低和高性能的最佳组合的系统和方法。诸如片上系统（SOC）的集成电路包括至少两个处理单元。第二处理单元包括高速缓存。 SOC包括功率管理单元（PMU），其确定第一处理单元的第一活动级别是否高于第一阈值，并且第二处理单元的第二活动级别低于第二阈值。如果该条件为真，则PMU对第二处理单元使用的最高功率状态（P状态）设置限制。 PMU发送指示以刷新第二处理单元内的至少一个高速缓存。 PMU将第一处理单元使用的P状态改变为更高性能的P状态。

23. 发明申请

US20130151869A1 METHOD FOR SOC PERFORMANCE AND POWER OPTIMIZATION 有权
标题翻译：用于SOC性能和功率优化的方法
公开(公告)号：US20130151869A1
公开(公告)日：2013-06-13
申请号：US13360012
申请日：2012-01-27
申请人： Maurice B. Steinman , Alexander J. Branover , Guhan Krishnan
发明人： Maurice B. Steinman , Alexander J. Branover , Guhan Krishnan
IPC分类号： G06F1/26
CPC分类号： G06F1/3243 , G06F1/324 , G06F1/3275 , G06F1/3296 , G06F9/5094 , Y02D10/126 , Y02D10/14 , Y02D10/172 , Y02D10/22
摘要： A system and method for efficient management of resources within a semiconductor chip for an optimal combination of power reduction and high performance. An intergrated circuit, such as a system on a chip (SOC), includes at least two processing units. The second processing unit includes a cache. The SOC includes a power management unit (PMU) that determines whether a first activity level for the first processing unit is above a first threshold and a second activity level for the second processing unit is below a second threshold. If this condition is true, then the PMU places a limit on a highest power-performance state (P-state) used by the second processing unit. The PMU sends an indication to flush the at least one cache within the second processing unit. The PMU changes a P-state used by the first processing unit to a higher performance P-state.
摘要翻译：一种用于有效管理半导体芯片内的资源以实现功率降低和高性能的最佳组合的系统和方法。诸如片上系统（SOC）的集成电路包括至少两个处理单元。第二处理单元包括高速缓存。 SOC包括功率管理单元（PMU），其确定第一处理单元的第一活动级别是否高于第一阈值，并且第二处理单元的第二活动级别低于第二阈值。如果该条件为真，则PMU对第二处理单元使用的最高功率状态（P状态）设置限制。 PMU发送指示以刷新第二处理单元内的至少一个高速缓存。 PMU将第一处理单元使用的P状态改变为更高性能的P状态。

24. 发明授权

US07844767B2 Method for identifying bad lanes and exchanging width capabilities of two CSI agents connected across a link 有权
标题翻译：用于识别通过链路连接的两个CSI代理的不良通道和交换宽度能力的方法
公开(公告)号：US07844767B2
公开(公告)日：2010-11-30
申请号：US10851925
申请日：2004-05-21
申请人： Naveen Cherukuri , Sanjay Dabral , David S. Dunning , Tim Frodsham , Theodore Z. Schoenborn , Rahul R. Shah , Maurice B. Steinman
发明人： Naveen Cherukuri , Sanjay Dabral , David S. Dunning , Tim Frodsham , Theodore Z. Schoenborn , Rahul R. Shah , Maurice B. Steinman
IPC分类号： G06F13/42 , G06F13/14 , G06F11/00
CPC分类号： G06F13/4265
摘要： A technique is described by which two link agents with ports coupled together using a point-to-point interconnect in a system exchange their link width support capabilities and negotiate a link width that is mutually agreeable. The interconnect between each pair of agents comprises a pair of uni-directional links having multiple electrical wires, or lanes, where one link is used by a first agent to transmit data to a second agent and another link is used by the second agent to transmit data to the first agent.
摘要翻译：描述了一种技术，其中具有使用系统中的点对点互连耦合在一起的端口的两个链路代理交换其链路宽度支持能力并协商相互同意的链路宽度。每对代理之间的互连包括具有多个电线或通道的一对单向链路，其中一个链路被第一代理用于向第二代理传输数据，另一链路由第二代理使用，数据到第一代理。

25. 发明授权

US07568118B2 Deterministic operation of an input/output interface 有权
标题翻译：输入/输出接口的确定性操作
公开(公告)号：US07568118B2
公开(公告)日：2009-07-28
申请号：US11231273
申请日：2005-09-20
申请人： Warren R. Anderson , Maurice B. Steinman , Richard M. Watson , Horst W. Wagner , Christopher C. Gianos , Suresh Balasubramanian , Tim Frodsham
发明人： Warren R. Anderson , Maurice B. Steinman , Richard M. Watson , Horst W. Wagner , Christopher C. Gianos , Suresh Balasubramanian , Tim Frodsham
IPC分类号： G06F13/42 , H04L5/00
CPC分类号： H04L7/00 , H04L7/0008 , H04L7/005
摘要： In one embodiment, the present invention includes a method for receiving data from a second device in a first device, forwarding the data from an input/output (I/O) clock domain to a system clock domain of the first device, and providing the data to a functional unit of the first device at a deterministic time. In such manner, the two devices may operate in lockstep fashion. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括一种用于从第一设备中的第二设备接收数据的方法，将数据从输入/输出（I / O）时钟域转发到第一设备的系统时钟域，在确定性时间将数据传送到第一设备的功能单元。以这种方式，两个装置可以锁定方式操作。描述和要求保护其他实施例。

26. 发明授权

US07362739B2 Methods and apparatuses for detecting clock failure and establishing an alternate clock lane 有权
标题翻译：用于检测时钟故障并建立备用时钟通道的方法和装置
公开(公告)号：US07362739B2
公开(公告)日：2008-04-22
申请号：US10874511
申请日：2004-06-22
申请人： Naveen Cherukuri , Tim Frodsham , Eduard Roytman , Sanjay Dabral , Rahul Shah , Theodore Z. Schoenborn , Maurice B. Steinman , David S. Dunning
发明人： Naveen Cherukuri , Tim Frodsham , Eduard Roytman , Sanjay Dabral , Rahul Shah , Theodore Z. Schoenborn , Maurice B. Steinman , David S. Dunning
IPC分类号： H04B7/216
CPC分类号： H04J3/0688 , H04L43/00 , H04L43/0847
摘要： Methods and apparatuses for determining clock failure for a multi-agent system employing a link-based interconnection scheme using a forwarded clock. For one embodiment of the invention, the cessation of the forwarded clock initiates a clock failure determination process. For one embodiment of the invention, upon a determination of clock failure, an alternate clock lane is implemented using a pre-designated data lane.
摘要翻译：用于确定使用转发时钟的基于链路的互连方案的多代理系统的时钟故障的方法和装置。对于本发明的一个实施例，转发时钟的停止启动时钟失败确定过程。对于本发明的一个实施例，在确定时钟故障时，使用预先指定的数据通道实现备用时钟通道。

27. 发明授权

US06754739B1 Computer resource management and allocation system 有权
标题翻译：计算机资源管理与分配系统
公开(公告)号：US06754739B1
公开(公告)日：2004-06-22
申请号：US09651945
申请日：2000-08-31
申请人： Richard E. Kessler , Michael S. Bertone , Gregg A. Bouchard , Maurice B. Steinman
发明人： Richard E. Kessler , Michael S. Bertone , Gregg A. Bouchard , Maurice B. Steinman
IPC分类号： G06F1300
CPC分类号： G06F9/544
摘要： A method and architecture for improved system resource management and allocation for the processing of request and response messages in a computer system. The resource management scheme provides for dynamically sharing system resources, such as data buffers, between request and response messages or transactions. In particular, instead of simply dedicating a portion of the system resources to requests and the remaining portion to responses, a minimum amount of resources are reserved for responses and a minimum amount for requests, while the remaining resources are dynamically shared between both types of messages. The method and architecture of the present invention allows for more efficient use of system resources, while avoiding deadlock conditions and ensuring a minimum service rate for requests.
摘要翻译：一种用于改进系统资源管理和分配以在计算机系统中处理请求和响应消息的方法和架构。资源管理方案提供在请求和响应消息或事务之间动态共享系统资源，例如数据缓冲器。特别地，不是简单地将系统资源的一部分专用于请求，而将余下的部分用于响应，而是为响应保留最小量的资源和用于请求的最小量，而剩余的资源在两种类型的消息之间动态共享。本发明的方法和体系结构允许更有效地利用系统资源，同时避免死锁状况并确保请求的最低服务速率。

28. 发明授权

US5638538A Turbotable: apparatus for directing address and commands between multiple consumers on a node coupled to a pipelined system bus 失效
标题翻译：可触发的：用于在耦合到流水线系统总线的节点上的多个消费者之间指导地址和命令的装置
公开(公告)号：US5638538A
公开(公告)日：1997-06-10
申请号：US372533
申请日：1995-01-13
申请人： Stephen R. VanDoren , Denis J. Foley , Maurice B. Steinman
发明人： Stephen R. VanDoren , Denis J. Foley , Maurice B. Steinman
IPC分类号： G06F13/36 , G06F13/00 , G06F12/00
CPC分类号： G06F13/36
摘要： A command queueing apparatus for directing address and command information amongst the various interfaces, or consumers, on a multi-CPU node in a computer system. The apparatus includes a core queue containing core queue entries, each core queue entry corresponding to a pending system bus operation. Each core queue entry includes one or more consumer information fields specific to each consumer. Also included is a plurality of virtual queues, each virtual queue corresponding to a consumer, each virtual queue having a virtual queue entry. A virtual queue entry for a consumer is a subset of the fields of a core queue entry, the subset of fields including the consumer information fields for the consumer corresponding to the virtual queue.
摘要翻译：一种用于在计算机系统中的多CPU节点上指导各种接口或消费者之间的地址和命令信息的命令排队装置。该装置包括一个包含核心队列条目的核心队列，每个核心队列条目对应于待处理的系统总线操作。每个核心队列条目包括每个消费者特有的一个或多个消费者信息字段。还包括多个虚拟队列，每个虚拟队列对应于消费者，每个虚拟队列具有虚拟队列条目。消费者的虚拟队列条目是核心队列条目的字段的子集，字段的子集包括与虚拟队列对应的消费者的消费者信息字段。

29. 发明授权

US09043625B2 Processor bridge power management 有权
标题翻译：处理器桥电源管理
公开(公告)号：US09043625B2
公开(公告)日：2015-05-26
申请号：US13446030
申请日：2012-04-13
申请人： Maurice B. Steinman , Alexander J. Branover , Denis J. Foley , Ljubisa Bajic
发明人： Maurice B. Steinman , Alexander J. Branover , Denis J. Foley , Ljubisa Bajic
IPC分类号： G06F1/32 , G06F1/00
CPC分类号： G06F1/3253 , G06F1/3296 , Y02D10/151 , Y02D10/172
摘要： A power controller can set the power state of a processor bridge based on which processor modules are in a communicative state. In addition, for a power state where selected processor modules are expected to be non-communicative, the power controller can set the supplied voltage to have a reduced voltage guard band as compared to other power states. These power management techniques can reduce the power consumed by the processor.
摘要翻译：功率控制器可以基于哪个处理器模块处于通信状态来设置处理器网桥的电源状态。另外，对于预期选择的处理器模块是不通信的电源状态，功率控制器可以将所提供的电压设置为与其它功率状态相比具有降低的电压保护带。这些电源管理技术可以减少处理器消耗的功耗。

30. 发明申请

US20140136869A1 ADAPTIVE CONNECTED STANDBY FOR A COMPUTING DEVICE 有权
标题翻译：用于计算设备的自适应连接待机
公开(公告)号：US20140136869A1
公开(公告)日：2014-05-15
申请号：US13674476
申请日：2012-11-12
申请人： Greg Sadowski , Alexander J. Branover , Maurice B. Steinman
发明人： Greg Sadowski , Alexander J. Branover , Maurice B. Steinman
IPC分类号： G06F1/32
CPC分类号： G06F1/3212 , G06F1/3287 , Y02D10/171 , Y02D10/174
摘要： Various computing devices and methods of managing the power consumption thereby are disclosed. In one aspect, a method of managing power consumption of a computing device that has a battery is provided. The method includes cycling the computing device between a connected standby active state and a connected standby idle state. The duration of the connected standby idle state is set based at least in part on a charge level of the battery.
摘要翻译：公开了各种计算设备和管理功耗的方法。一方面，提供一种管理具有电池的计算装置的功耗的方法。该方法包括在连接的待机活动状态和连接的待机空闲状态之间循环计算设备。连接的待机空闲状态的持续时间至少部分地基于电池的充电水平来设定。

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