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21. 发明授权

US07231626B2 Method of implementing an engineering change order in an integrated circuit design by windows 有权
标题翻译：通过Windows实现集成电路设计中的工程变更顺序的方法
公开(公告)号：US07231626B2
公开(公告)日：2007-06-12
申请号：US11015123
申请日：2004-12-17
申请人： Jason K. Hoff , Viswanathan Lakshmanan , Michael Josephides , Daniel W. Prevedel , Richard D. Blinne , Johathan P. Kuppinger
发明人： Jason K. Hoff , Viswanathan Lakshmanan , Michael Josephides , Daniel W. Prevedel , Richard D. Blinne , Johathan P. Kuppinger
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F17/5068 , G06F2217/04
摘要： A method of implementing an engineering change order includes steps of: (a) receiving as input an integrated circuit design; (b) receiving as input an engineering change order to the integrated circuit design; (c) creating at least one window in the integrated circuit design that encloses a change to the integrated circuit design introduced by the engineering change order wherein the window is bounded by coordinates that define an area that is less than an entire area of the integrated circuit design; (d) performing a routing of the integrated circuit design that excludes routing of any net that is not enclosed by the window; (e) replacing an area in a copy of the integrated circuit design that is bounded by the coordinates of the window with results of the incremental routing to generate a revised integrated circuit design; and (f) generating as output the revised integrated circuit design.
摘要翻译：一种实现工程变更订单的方法包括以下步骤：（a）作为输入接收集成电路设计; （b）作为输入接收集成电路设计的工程变更订单; （c）在集成电路设计中创建至少一个窗口，其包围由工程改变顺序引入的集成电路设计的变化，其中窗口由限定小于集成电路的整个区域的区域的坐标界定设计; （d）执行集成电路设计的路由，该路由排除不包括窗口的任何网络的路由; （e）将由窗口坐标限定的集成电路设计的副本中的区域替换为增量路由的结果以生成修订的集成电路设计; 和（f）产生经修订的集成电路设计的输出。

22. 发明授权

US07219317B2 Method and computer program for verifying an incremental change to an integrated circuit design 有权
标题翻译：用于验证集成电路设计的增量变化的方法和计算机程序
公开(公告)号：US07219317B2
公开(公告)日：2007-05-15
申请号：US10828408
申请日：2004-04-19
申请人： Viswanathan Lakshmanan , Richard D. Blinne , Jonathan P. Kuppinger
发明人： Viswanathan Lakshmanan , Richard D. Blinne , Jonathan P. Kuppinger
IPC分类号： G06F17/50
CPC分类号： G06F17/5022 , G06F17/5045
摘要： A method and computer program product for verifying an incremental change to an integrated circuit design include receiving as input an integrated circuit design database and an engineering change order. Objects in the integrated circuit design database are identified and marked to indicate a current state of the integrated circuit design database. The engineering change order is applied to the integrated circuit design database, and the integrated circuit design database is analyzed to generate a list of incremental changes to the integrated circuit design database resulting from the engineering change order. Objects in the integrated circuit design database included in the list of incremental changes are identified and marked to distinguish objects in the integrated circuit design database that were changed from the current state. The marked integrated circuit design database distinguishing the objects that were changed from the current state is generated as output.
摘要翻译：用于验证集成电路设计的增量变化的方法和计算机程序产品包括接收集成电路设计数据库和工程变更顺序作为输入。集成电路设计数据库中的对象被识别并标记为指示集成电路设计数据库的当前状态。工程变更单适用于集成电路设计数据库，并对集成电路设计数据库进行分析，以生成由工程变更订单产生的集成电路设计数据库的增量变化清单。集成电路设计数据库中包含增量变化列表中的对象被识别并标记为区分集成电路设计数据库中与当前状态相对应的对象。标记的集成电路设计数据库将区分从当前状态改变的对象作为输出生成。

23. 发明申请

US20060095883A1 Method of automating place and route corrections for an integrated circuit design from physical design validation 有权
标题翻译：通过物理设计验证自动化集成电路设计的位置和路线校正方法
公开(公告)号：US20060095883A1
公开(公告)日：2006-05-04
申请号：US10977386
申请日：2004-10-29
申请人： Viswanathan Lakshmanan , Michael Josephides , Richard Blinne
发明人： Viswanathan Lakshmanan , Michael Josephides , Richard Blinne
IPC分类号： G06F17/50 , G06F9/45 , G06F9/455
CPC分类号： G06F17/5081
摘要： A method and computer program product for automatically correcting errors in an integrated circuit design includes steps of: (a) performing a physical design validation of an integrated circuit design to verify compliance with a set of design rules; (b) generating a results database of design rule violations detected by the physical design validation; (c) identifying locations in the integrated circuit design from the results database for making design corrections according to a post-processing rule deck so that the locations of the design corrections comply with the set of design rules; and (d) implementing the design corrections in the integrated circuit design.
摘要翻译：一种用于自动校正集成电路设计中的错误的方法和计算机程序产品包括以下步骤：（a）执行集成电路设计的物理设计验证以验证是否符合一组设计规则; （b）生成通过物理设计验证检测到的设计规则违规的结果数据库; （c）从结果数据库中识别集成电路设计中的位置，以便根据后处理规则表进行设计更正，使设计更正的位置符合设计规则集; 和（d）在集成电路设计中实现设计校正。

24. 发明申请

US20060090144A1 Method of automating place and route corrections for an integrated circuit design from physical design validation 审中-公开
公开(公告)号：US20060090144A1
公开(公告)日：2006-04-27
申请号：US10975570
申请日：2004-10-27
申请人： Viswanathan Lakshmanan , Michael Josephides , Richard Blinne
发明人： Viswanathan Lakshmanan , Michael Josephides , Richard Blinne
IPC分类号： G06F17/50 , G06F9/45
CPC分类号： G06F17/5081
摘要： A method and computer program product for automatically correcting errors in an integrated circuit design includes steps of: (a) performing a physical design validation of an integrated circuit design to verify compliance with a set of design rules; (b) generating a results database of design rule violations detected by the physical design validation; (c) identifying locations in the integrated circuit design from the results database for making design corrections according to a post-processing rule deck so that the locations of the design corrections comply with the set of design rules; and (d) implementing the design corrections in the integrated circuit design.

25. 发明申请

US20050080607A1 Incremental dummy metal insertions 有权
标题翻译：增量的虚拟金属插入
公开(公告)号：US20050080607A1
公开(公告)日：2005-04-14
申请号：US10683369
申请日：2003-10-10
申请人： Viswanathan Lakshmanan , Richard Blinne , Vikram Shrowty , Lena Montecillo
发明人： Viswanathan Lakshmanan , Richard Blinne , Vikram Shrowty , Lena Montecillo
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F2217/12 , Y02P90/265
摘要： A method and system for performing dummy metal insertion in design data for an integrated circuit is disclosed, wherein the design data includes dummy metal objects inserted by a dummy fill tool. After a portion of the design data is changed, a check is performed to determine whether any dummy metal objects intersect with any other objects in the design data. If so, the intersecting dummy metal objects are deleted from the design data, thereby avoiding having to rerun the dummy fill tool.
摘要翻译：公开了一种用于在集成电路的设计数据中执行虚拟金属插入的方法和系统，其中设计数据包括由虚拟填充工具插入的虚拟金属物体。在设计数据的一部分改变之后，执行检查以确定任何虚拟金属物体是否与设计数据中的任何其他对象相交。如果是这样，则从设计数据中删除相交的虚拟金属物体，从而避免重新运行虚拟填充工具。

26. 发明授权

US06668359B1 Verilog to vital translator 失效
标题翻译：重要翻译Verilog
公开(公告)号：US06668359B1
公开(公告)日：2003-12-23
申请号：US10003823
申请日：2001-10-31
申请人： Nader Fakhry , Viswanathan Lakshmanan
发明人： Nader Fakhry , Viswanathan Lakshmanan
IPC分类号： G06F1750
CPC分类号： G06F17/5022
摘要： A method of translating a register transfer level code model includes receiving as inputs a user defined primitives map file, a truth table map file, a gate primitives map file, a register transfer level description file of a library cell, a standard delay format file, and a pin order information file for the register transfer level code model; creating data structures for a VITAL model; parsing at least one of the user defined primitives map file, the truth table map file, the gate primitives map file, the register transfer level description file, and the standard delay format file to generate an equivalent VITAL model in the data structures created for the VITAL model wherein the VITAL model is functionally equivalent to the register transfer level code model; and generating as output a VITAL model file from the data structures created for the VITAL model.
摘要翻译：一种翻译寄存器传送级代码模型的方法包括：接收用户定义的基元映射文件，真值表映射文件，门基元映射文件，库单元的寄存器传输级别描述文件，标准延迟格式文件，以及用于寄存器传送级代码模型的引脚顺序信息文件; 为VITAL模型创建数据结构; 解析用户定义的基元映射文件，真值表映射文件，门基元映射文件，寄存器传输级别描述文件和标准延迟格式文件中的至少一个，以在针对所创建的数据结构中生成等价的VITAL模型 VITAL模型，其中VITAL模型在功能上等同于寄存器传送级代码模型; 并从为VITAL模型创建的数据结构中生成VITAL模型文件作为输出。

27. 发明授权

US06658630B1 Method to translate UDPs using gate primitives 有权
标题翻译：使用门字元翻译UDP的方法
公开(公告)号：US06658630B1
公开(公告)日：2003-12-02
申请号：US09710359
申请日：2000-11-09
申请人： Vance Threatt , Viswanathan Lakshmanan
发明人： Vance Threatt , Viswanathan Lakshmanan
IPC分类号： G06F1750
CPC分类号： G06F17/5045 , G06F17/5022
摘要： A software program to translate a Verilog UDP (User Defined Primitive) into basic logic gates, in order to allow easier porting into other HDL languages and non-Verilog models, such as the LogicVision model. In a preferred embodiment the program is in Perl script, and reads in a Verilog source file. On finding a UDP, the script writes out a gate level description of the UDP into a Perl hash data structure, which is later used to output a LogicVision model.
摘要翻译：将Verilog UDP（用户定义的基元）转换为基本逻辑门的软件程序，以便更容易地移植到其他HDL语言和非Verilog模型中，例如LogicVision模型。在优选实施例中，程序是Perl脚本，并且读入Verilog源文件。在找到UDP时，脚本将UDP的门级描述写入Perl哈希数据结构中，后者用于输出LogicVision模型。

28. 发明授权

US06453451B1 Generating standard delay format files with conditional path delay for designing integrated circuits 有权
标题翻译：生成具有条件路径延迟的标准延迟格式文件，用于设计集成电路
公开(公告)号：US06453451B1
公开(公告)日：2002-09-17
申请号：US09880607
申请日：2001-06-12
申请人： Viswanathan Lakshmanan , Kenton Dalton
发明人： Viswanathan Lakshmanan , Kenton Dalton
IPC分类号： G06F1750
CPC分类号： G06F17/5022
摘要： A method of generating a back-annotated standard delay format file for designing integrated circuits with conditional/moded delays is disclosed that includes the steps of receiving as inputs a main input file, a conditional delay specifications file, and a selected option switch; inserting delay information from the conditional delay specifications file for each cell entry in the main input file according to the selected option switch into an output data structure; and generating the back-annotated standard delay format file from the output data structure.
摘要翻译：公开了一种生成用于设计具有条件/调制延迟的集成电路的反向标注的标准延迟格式文件的方法，其包括以下步骤：接收作为输入的主输入文件，条件延迟规范文件和所选择的选项开关; 将根据所选择的选项切换到主输入文件中的每个单元条目的条件延迟规范文件的延迟信息插入到输出数据结构中; 以及从输出数据结构生成反向注释的标准延迟格式文件。

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