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21. 发明申请

US20100174967A1 CONTROL APPARATUS AND CONTROL METHOD 有权
标题翻译：控制装置和控制方法
公开(公告)号：US20100174967A1
公开(公告)日：2010-07-08
申请号：US12652773
申请日：2010-01-06
申请人： Satoru Funaki , Yasuhiro Kiyofuji , Masashi Suenaga , Shin Kokura , Eiji Kobayashi , Akihiro Onozuka , Yusuke Seki , Toshiki Shimizu , Yukiko Tahara , Yuta Sugimoto
发明人： Satoru Funaki , Yasuhiro Kiyofuji , Masashi Suenaga , Shin Kokura , Eiji Kobayashi , Akihiro Onozuka , Yusuke Seki , Toshiki Shimizu , Yukiko Tahara , Yuta Sugimoto
IPC分类号： H03M13/05 , G06F11/10
CPC分类号： G06F11/1008 , H03M13/09
摘要： A failure is detected immediately and certainly, and continuation of processing in an unstable state is prevented. A first error detection code is generated from first information which is output as a result of execution of a predetermined program conducted by a first processor. A second error detection code is generated from second information which is output as a result of execution of the program conducted by a second processor which is configured so as to output the same computation result as that of the first processor. It is detected whether the first information is the same as the second information, and it is detected whether the first error detection code is the same as the second error detection code. Writing the first information or the second information into a main memory is controlled on the basis of a result of the detection.
摘要翻译：立即且肯定地检测到故障，并且防止处于不稳定状态的处理的继续。作为执行由第一处理器执行的预定程序的结果而输出的第一信息产生第一错误检测码。从作为由第二处理器执行的程序的执行结果输出的第二信息生成第二错误检测码，该第二处理器被配置为输出与第一处理器相同的计算结果。检测第一信息是否与第二信息相同，并且检测第一错误检测码是否与第二错误检测码相同。基于检测结果来控制将第一信息或第二信息写入主存储器。

22. 发明申请

US20110113277A1 PROCESSING UNIT, PROCESS CONTROL SYSTEM AND CONTROL METHOD 有权
标题翻译：加工单元，过程控制系统和控制方法
公开(公告)号：US20110113277A1
公开(公告)日：2011-05-12
申请号：US12938557
申请日：2010-11-03
申请人： Noritaka Matsumoto , Tsutomu Yamada , Eiji Kobayashi , Akihiro Ohashi , Shin Kokura
发明人： Noritaka Matsumoto , Tsutomu Yamada , Eiji Kobayashi , Akihiro Ohashi , Shin Kokura
IPC分类号： G06F1/12
CPC分类号： G06F11/0766 , G06F11/0724 , G06F11/076
摘要： A processing unit is connected to another processing unit through a system bus composed of serial signal communication line and synchronization signal communication line to be able to communicate therewith. When an operation unit detects abnormal state in the processing unit, the operation unit supplies notification of detection of the abnormal state to synchronization unit. The synchronization unit transmits the received detection notification of abnormal state to the other processing unit through the synchronization signal communication line. Conversion unit receives parallel communication data from the operation unit through important signal line instead of general signal line and converts the received parallel signal into serial signal to be transmitted to the other processing unit through the serial signal communication line, thereby soundness among processing units connected to the system bus is ensured when the system bus is configured to attain serial communication.
摘要翻译：处理单元通过由串行信号通信线路和同步信号通信线路组成的系统总线连接到另一个处理单元，以能够与其通信。当操作单元检测到处理单元中的异常状态时，操作单元将异常状态的检测通知提供给同步单元。同步单元通过同步信号通信线路将接收到的异常状态的检测通知发送给其他处理单元。转换单元通过重要信号线代替通用信号线从操作单元接收并行通信数据，并将接收到的并行信号转换为串行信号，以通过串行信号通信线路发送到另一个处理单元，从而在连接到当系统总线被配置为实现串行通信时，确保系统总线。

23. 发明授权

US08671300B2 Processing unit, process control system and control method 有权
标题翻译：处理单元，过程控制系统和控制方法
公开(公告)号：US08671300B2
公开(公告)日：2014-03-11
申请号：US12938557
申请日：2010-11-03
申请人： Noritaka Matsumoto , Tsutomu Yamada , Eiji Kobayashi , Akihiro Ohashi , Shin Kokura
发明人： Noritaka Matsumoto , Tsutomu Yamada , Eiji Kobayashi , Akihiro Ohashi , Shin Kokura
IPC分类号： G06F1/04 , G06F1/12 , G06F15/16
CPC分类号： G06F11/0766 , G06F11/0724 , G06F11/076
摘要： A processing unit is connected to another processing unit through a system bus composed of serial signal communication line and synchronization signal communication line to be able to communicate therewith. When an operation unit detects abnormal state in the processing unit, the operation unit supplies notification of detection of the abnormal state to synchronization unit. The synchronization unit transmits the received detection notification of abnormal state to the other processing unit through the synchronization signal communication line. Conversion unit receives parallel communication data from the operation unit through important signal line instead of general signal line and converts the received parallel signal into serial signal to be transmitted to the other processing unit through the serial signal communication line, thereby soundness among processing units connected to the system bus is ensured when the system bus is configured to attain serial communication.
摘要翻译：处理单元通过由串行信号通信线路和同步信号通信线路组成的系统总线连接到另一个处理单元，以能够与其通信。当操作单元检测到处理单元中的异常状态时，操作单元将异常状态的检测通知提供给同步单元。同步单元通过同步信号通信线路将接收到的异常状态的检测通知发送给其他处理单元。转换单元通过重要信号线代替通用信号线从操作单元接收并行通信数据，并将接收到的并行信号转换为串行信号，以通过串行信号通信线路发送到另一个处理单元，从而在连接到当系统总线被配置为实现串行通信时，确保系统总线。

24. 发明授权

US5699541A Memory system using schottky diodes to reduce load capacitance 失效
标题翻译：使用肖特基二极管降低负载电容的存储系统
公开(公告)号：US5699541A
公开(公告)日：1997-12-16
申请号：US406147
申请日：1995-03-20
申请人： Kenichi Kurosawa , Shin Kokura , Michio Morioka , Tetsuaki Nakamikawa , Sakou Ishikawa
发明人： Kenichi Kurosawa , Shin Kokura , Michio Morioka , Tetsuaki Nakamikawa , Sakou Ishikawa
IPC分类号： G11C11/417 , G06F13/16 , G11C7/10 , G11C11/409 , G06F12/00 , G06F9/26 , G06F9/32 , G06F12/02
CPC分类号： G11C7/1051 , G11C7/1078
摘要： A computer memory system is disclosed with an input/output circuitry capable of separating the load separating the load capacitance of an output circuit of a semiconductor memory connected to a memory bus from the memory bus. In order to separate the load capacitance of a semiconductor memory connected to a memory bus signal line, a Schottky diode is arranged between the semiconductor memory and the memory bus line, and a voltage control circuit is provided to control whether a reverse bias voltage is applied to the Schottky diode. The speed of signal transmission does not decrease even when a large number of semiconductor memories are connected to the memory bus since the load capacitance of the semiconductor memories is separated from the bus. Therefore, it is possible to construct a high speed and large capacity memory system.
摘要翻译：公开了具有输入/输出电路的计算机存储器系统，该输入/输出电路能够将连接到存储器总线的半导体存储器的输出电路的负载电容与存储器总线分开。为了分离连接到存储器总线信号线的半导体存储器的负载电容，在半导体存储器和存储器总线之间布置肖特基二极管，并且提供电压控制电路以控制是否施加反向偏置电压到肖特基二极管。即使当半导体存储器的负载电容与总线分离时，即使大量的半导体存储器连接到存储器总线，信号传输的速度也不会降低。因此，可以构建高速，大容量的存储系统。

25. 发明授权

US5841963A Dual information processing system having a plurality of data transfer channels 失效
标题翻译：双信息处理系统具有多个数据传输通道
公开(公告)号：US5841963A
公开(公告)日：1998-11-24
申请号：US861471
申请日：1997-05-21
申请人： Tetsuaki Nakamikawa , Shin Kokura , Kenichi Kurosawa , Shinichiro Yamaguchi , Yoshihiro Miyazaki , Hiroshi Ohguro
发明人： Tetsuaki Nakamikawa , Shin Kokura , Kenichi Kurosawa , Shinichiro Yamaguchi , Yoshihiro Miyazaki , Hiroshi Ohguro
IPC分类号： G06F11/16 , G06F15/17
CPC分类号： G06F11/1658
摘要： A dual computer system consisting of two computer systems connected by a plurality of data transfer units and a plurality of data transfer channels for a memory copy made to again synchronize both the computer systems at the time of recovery from a fault. When no fault occurs on the data transfer channels, the data transfer units share the load of data transfer in the memory copy operation, and when a fault occurs on any data transfer unit during the memory copy operation, the remaining normal data transfer units are used to again transfer data, whereby a memory copy is made at high speed for again synchronizing both the computer systems at the time of recovery from a fault, and system reliability at the time of recovery from a fault is improved.
摘要翻译：由由多个数据传送单元连接的两个计算机系统和用于存储器副本的多个数据传送通道组成的双计算机系统，使得在从故障恢复时再次同步计算机系统。当数据传输通道没有发生故障时，数据传输单元在存储器复制操作中共享数据传输的负载，并且当在存储器复制操作期间在任何数据传送单元发生故障时，使用剩余的正常数据传送单元再次传送数据，从而高速地进行存储器复制，以便在从故障恢复时再次同步计算机系统，并且提高从故障恢复时的系统可靠性。

26. 发明申请

US20110302393A1 CONTROL SYSTEMS AND DATA PROCESSING METHOD 审中-公开
标题翻译：控制系统和数据处理方法
公开(公告)号：US20110302393A1
公开(公告)日：2011-12-08
申请号：US13153724
申请日：2011-06-06
申请人： Noritaka Matsumoto , Tsutomu Yamada , Akihiro Ohashi , Shin Kokura
发明人： Noritaka Matsumoto , Tsutomu Yamada , Akihiro Ohashi , Shin Kokura
IPC分类号： G06F9/302
CPC分类号： G06F9/3017 , G05B19/052 , G05B2219/13028 , G05B2219/15114
摘要： When executing sequential processing such as a ladder logic, converting a program formed of an instruction set of another processor to a program executable by an own processor in software and then conducting processing lowers the real time property. In a control system, a storage unit stores a program for the own processor and a program for another processor. A processor reads data from the storage unit, executes processing described as a program, and gives an instruction to change over a method for acquiring data from the storage unit, to a conversion instruction unit according to data contents. A changeover unit is connected to the storage unit directly or via the conversion unit to change over the data acquiring method according to an instruction from the conversion instruction unit. The conversion unit converts data read from the storage unit to data executable by the processor, according to a conversion scheme.
摘要翻译：当执行诸如梯形逻辑的顺序处理时，将由另一处理器的指令集形成的程序转换成由软件可由自己的处理器执行的程序，然后执行处理降低实时属性。在控制系统中，存储单元存储用于自己的处理器的程序和用于另一个处理器的程序。处理器从存储单元读取数据，执行作为程序描述的处理，并且根据数据内容给出将从存储单元获取数据的方法改变为转换指令单元的指令。切换单元直接或经由转换单元连接到存储单元，以根据来自转换指令单元的指令改变数据获取方法。转换单元根据转换方案将从存储单元读取的数据转换为可由处理器执行的数据。

27. 发明授权

US06453391B2 Multiplexed computer system 失效
标题翻译：多路复用计算机系统
公开(公告)号：US06453391B2
公开(公告)日：2002-09-17
申请号：US09882258
申请日：2001-06-18
申请人： Yuuichiro Morita , Tetsuaki Nakamikawa , Shinichiro Yamaguchi , Naoto Miyazaki , Shin Kokura , Yoshihiro Miyazaki
发明人： Yuuichiro Morita , Tetsuaki Nakamikawa , Shinichiro Yamaguchi , Naoto Miyazaki , Shin Kokura , Yoshihiro Miyazaki
IPC分类号： G06F1200
CPC分类号： G06F11/1658 , G06F11/2028 , G06F11/2035 , G06F11/2043 , G06F11/2097 , G06F12/0804
摘要： A multiplexed computer system allows memory accessing by a processor, a peripheral equipment or a like apparatus even during execution of memory copying to improve the processing performance during on-line maintenance. To this end, the multiplexed computer system includes a plurality of processing units which effect the same operation in synchronism with each other. Each of the processing units includes a copy processor register for designating a processor to read out contents of a memory unit, a memory copy control unit for transferring copies of the stored contents of the memory unit and data to be written into the memory unit in the same order as that of accesses to the memory unit of the other processing unit, a copy mode flag indicating that memory copy processing for making the stored contents of the memory unit of the self system and stored contents of the memory unit of the other processing unit coincide with each other is proceeding, and a copy task flag indicating that the processor is reading out, during memory copying processing, the stored contents of the memory unit.
摘要翻译：复用的计算机系统即使在执行存储器复制期间也允许由处理器，外围设备或类似设备进行的存储器访问，以提高在线维护期间的处理性能。为此，多路复用的计算机系统包括多个处理单元，其相互同步地进行相同的操作。每个处理单元包括用于指定处理器以读取存储器单元的内容的复制处理器寄存器，用于将存储器单元的存储内容的副本和要写入的存储器单元的副本传送到存储器单元的存储器复制控制单元与对其他处理单元的存储单元的访问相同的顺序，指示用于使自身系统的存储单元的存储内容和其他处理单元的存储单元的存储内容的存储器复制处理的复制模式标志并且在存储器复制处理期间指示处理器正在读出存储单元的存储内容的复制任务标志。

28. 发明授权

US6003116A Multiplexed computer system with the capability to copy data from one processor memory to another 失效
标题翻译：具有将数据从一个处理器存储器复制到另一个处理器的能力的多路复用计算机系统
公开(公告)号：US6003116A
公开(公告)日：1999-12-14
申请号：US739393
申请日：1996-10-29
申请人： Yuuichiro Morita , Tetsuaki Nakamikawa , Shinichiro Yamaguchi , Naoto Miyazaki , Shin Kokura , Yoshihiro Miyazaki
发明人： Yuuichiro Morita , Tetsuaki Nakamikawa , Shinichiro Yamaguchi , Naoto Miyazaki , Shin Kokura , Yoshihiro Miyazaki
IPC分类号： G06F11/18 , G06F11/20 , G06F12/08 , G06F15/16 , G06F15/177 , G06F12/00 , G06F13/00
CPC分类号： G06F11/1658 , G06F12/0804 , G06F11/2028 , G06F11/2035 , G06F11/2043 , G06F11/2097
摘要： A multiplexed computer system allows memory accessing by a processor, a peripheral equipment or a like apparatus even during execution of memory copying to improve the processing performance during on-line maintenance. To this end, the multiplexed computer system includes a plurality of processing units which carry out the same operation in synchronism with each other. Each of the processing units includes a copy processor register for designating a processor to read out contents of a memory unit, copying circuits which transfer copies of the stored contents of the memory unit and data to be written into the memory unit in the same order as that of accesses to the memory unit to a memory unit of another processing unit, a copy mode flag indicating that memory copying processing for making the stored contents of the memory unit of the self system and stored contents of the memory unit of the other processing unit coincide with each other is proceeding, and a copy task flag indicating that the processor is reading out, during memory copying processing, the stored contents of the memory unit.
摘要翻译：复用的计算机系统即使在执行存储器复制期间也允许由处理器，外围设备或类似设备进行的存储器访问，以提高在线维护期间的处理性能。为此，复用的计算机系统包括多个处理单元，它们彼此同步地执行相同的操作。每个处理单元包括一个复制处理器寄存器，用于指定一个处理器来读取存储器单元的内容，复制电路，将存储单元的存储内容的副本和要写入存储单元的数据按照与对存储器单元访问另一处理单元的存储器单元的复制模式标志，指示用于使自身系统的存储单元的存储内容存储的存储器复制处理和另一处理单元的存储单元的存储的复制模式标志并且在存储器复制处理期间指示处理器正在读出存储单元的存储内容的复制任务标志。

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