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21. 发明授权

US5321540A Optical frequency division multiplexing network 失效
标题翻译：光分频复用网络
公开(公告)号：US5321540A
公开(公告)日：1994-06-14
申请号：US800255
申请日：1991-11-29
申请人： Atsushi Takai , Ryoji Takeyari , Akihiko Takase
发明人： Atsushi Takai , Ryoji Takeyari , Akihiko Takase
IPC分类号： H04B10/07 , H04B10/27 , H04B10/291 , H04J14/02 , H04Q3/60 , H04Q11/00 , H04B10/00
CPC分类号： H04Q11/0062 , H04J14/02 , H04J14/0201 , H04J14/0204 , H04J14/0205 , H04J14/0206 , H04J14/0209 , H04J14/0212 , H04J14/0213 , H04Q2011/0009 , H04Q2011/0011 , H04Q2011/0013 , H04Q2011/0015 , H04Q2011/0039 , H04Q2011/0086
摘要： An optical frequency division multiplexing network includes first optical communication paths connected to terminals, respectively, a second optical communication path connected to the outside and a node composed of a selection unit for selecting signals having optical frequencies to be sent to the plurality of terminals, respectively, from signals transmitted through the second optical communication path in optical frequency division multiplexing, a conversion unit for converting the selected signals into signals having a single optical frequency and an output unit for producing the converted signals to the terminals through the first optical communication paths, respectively.
摘要翻译：光分频复用网络包括分别连接到终端的第一光通信路径，连接到外部的第二光通信路径和由用于选择要发送到多个终端的光频信号的选择单元组成的节点通过光分频多路复用通过第二光通信路径发送的信号，将所选择的信号转换成具有单一光频率的信号的转换单元和用于通过第一光通信路径向终端产生转换信号的输出单元，分别。

22. 发明授权

US5164937A Packet concentrator and packet switching system 失效
标题翻译：分组集中器和分组开关系统
公开(公告)号：US5164937A
公开(公告)日：1992-11-17
申请号：US551930
申请日：1990-07-12
申请人： Shirou Tanabe , Akihiko Takase , Masao Kunimoto , Yoshito Sakurai
发明人： Shirou Tanabe , Akihiko Takase , Masao Kunimoto , Yoshito Sakurai
IPC分类号： H04L12/951
CPC分类号： H04L49/3009 , H04L49/254 , H04L49/103 , H04L49/30 , H04L49/50
摘要： A method and system are provided for concentrating calls for a packet switching system in a hierarchical communication network. A plurality of terminals communicate with an associated plurality of packet concentrators that, in turn, communicate with switching equipment. The system and method comprise initiating a call at a call terminal to be communicated to the packet concentrator and identifying the call terminal by associating a line number communicating the terminal with the concentrator with a first logical channel number for communication from the packet concentrator to the switching equipment. The logic channel number is recorded in association with the first number line at the packet concentrator whereby call communication back to the call terminal can be made on the proper line number by relating the line number with the logic channel line of the call and thereby avoiding the need to switch logic channels between the concentrator and the switching equipment to avoid costly call processing at the concentrator. Further benefits provided by executing of the general call processing at the switching equipment including tariff control.

23. 发明授权

US07463633B2 Packet switching system, packet switching network and packet switching method 失效
标题翻译：分组交换系统，分组交换网络和分组交换方式
公开(公告)号：US07463633B2
公开(公告)日：2008-12-09
申请号：US09879953
申请日：2001-06-14
申请人： Noboru Endo , Akihiko Takase , Hajime Abe , Kazuho Miki
发明人： Noboru Endo , Akihiko Takase , Hajime Abe , Kazuho Miki
IPC分类号： H04L12/28
CPC分类号： H04L49/254 , H04L49/251 , H04L49/30 , H04L49/3009 , H04L49/3081 , H04L49/602 , H04L49/606 , H04L2012/5667 , H04Q11/0478
摘要： Upon initialization, a VPC is set up between edge nodes. A control processor of each node creates an IP address/VPC mapping table using IP routing information and an address mapping table mapping correspondence between IP addresses and ATM addresses and supplied by a network management system. A gateway assigns a VCC to each packet input to the network. A sending-side edge node inputs the packet to the VPC corresponding to its destination by referring to the IP address/VPC mapping table. A transit node performs packet switching over VP. A receiving-side edge node transfers each packet to the gateway corresponding to its destination. If a series of packets meet a predetermined condition in a given edge node, its control processor sends VCC information to input interfaces of the edge node so that the packets are switched by an ATM switch in the edge node without intervention of the control processor.
摘要翻译：在初始化时，在边缘节点之间建立一个VPC。每个节点的控制处理器使用IP路由信息和地址映射表来映射IP地址和ATM地址之间的对应关系并由网络管理系统提供的IP地址/ VPC映射表。网关为每个输入到网络的数据包分配一个VCC。发送侧边缘节点通过参考IP地址/ VPC映射表将分组输入到与其目的地对应的VPC。传输节点通过VP执行分组交换。接收侧边缘节点将每个分组传送到与其目的地相对应的网关。如果一系列分组满足给定边缘节点的预定条件，则其控制处理器向边缘节点的输入接口发送VCC信息，使得分组由边缘节点中的ATM交换机切换，而无需控制处理器的干预。

24. 发明申请

US20050175351A1 Optical frequency division multiplexing network 失效
标题翻译：光分频复用网络
公开(公告)号：US20050175351A1
公开(公告)日：2005-08-11
申请号：US10623160
申请日：2003-07-21
申请人： Atsushi Takai , Ryoji Takeyari , Akihiko Takase
发明人： Atsushi Takai , Ryoji Takeyari , Akihiko Takase
IPC分类号： H04B10/07 , H04B10/27 , H04B10/291 , H04J14/02 , H04Q3/60 , H04Q11/00 , H04B10/00
CPC分类号： H04Q11/0062 , H04J14/02 , H04J14/0201 , H04J14/0204 , H04J14/0205 , H04J14/0206 , H04J14/0209 , H04J14/0212 , H04J14/0213 , H04Q2011/0009 , H04Q2011/0011 , H04Q2011/0013 , H04Q2011/0015 , H04Q2011/0039 , H04Q2011/0086
摘要： An optical frequency division multiplexing network includes first optical communication paths connected to terminals, respectively, a second optical communication path connected to the outside and a node composed of a selection unit for selecting signals having optical frequencies to be sent to the plurality of terminals, respectively, from signals transmitted through the second optical communication path in optical frequency division multiplexing, a conversion unit for converting the selected signals into signals having a single optical frequency and an output unit for producing the converted signals to the temrinals through the first optical communication paths, respectively.
摘要翻译：光分频复用网络包括分别连接到终端的第一光通信路径，连接到外部的第二光通信路径和由用于选择要发送到多个终端的光频信号的选择单元组成的节点通过光分频多路复用通过第二光通信路径发送的信号，将所选择的信号转换为具有单个光频率的信号的转换单元和用于通过第一光通信路径产生转换信号到转换信号的输出单元，分别。

25. 发明授权

US06330227B1 Cell output control apparatus and method 失效
标题翻译：单元输出控制装置及方法
公开(公告)号：US06330227B1
公开(公告)日：2001-12-11
申请号：US09382669
申请日：1999-08-25
申请人： Kota Miyoshi , Takahiko Kozaki , Hajime Abe , Akihiko Takase
发明人： Kota Miyoshi , Takahiko Kozaki , Hajime Abe , Akihiko Takase
IPC分类号： G06F1100
CPC分类号： H04L12/5602 , H04L41/00 , H04L2012/5632 , H04L2012/5635 , H04L2012/5649 , H04L2012/5658 , H04L2012/5667 , H04L2012/5679 , H04Q11/0478
摘要： The cell output control apparatus includes a cell time slot allotment circuit for allotting, cells to be transmitted, to cell time slots with the cell transmission intervals changed, a first holder circuit for holding the value of ACR (Allowed Cell Rate), a first calculator circuit for calculating the ratio, LCR (Line Cell Rate)/ACR, a quantizer circuit for quantizing the ratio, LCR/ACR and controlling the allotment of cell time slots on the basis of the quantization error produced by the quantization, a counter for counting the values of cell time slots, a second calculator circuit for calculating the cell time slots for cells, and a second holder circuit for holding the calculated results, whereby it is possible to absorb the quantization error produced when the ratio, LCR/ACR is quantized into an integral value.
摘要翻译：小区输出控制装置包括：小区时隙分配电路，用于将发送的小区分配给小区发送间隔改变的小区时隙，用于保持ACR（允许小区率）的值的第一保持电路，第一计算器用于计算比率的电路，LCR（线路单元速率）/ ACR，用于量化比率的量化器电路，LCR / ACR，并且基于由量化产生的量化误差来控制单元时隙的分配，用于计数的计数器单元时隙的值，用于计算单元的单元格时隙的第二计算器电路和用于保持所计算的结果的第二保持器电路，由此可以吸收当比率LCR / ACR被量化时产生的量化误差成为一个整体价值。

26. 发明授权

US06185212B2 ATM cell processing apparatus 失效
标题翻译： ATM信元处理装置
公开(公告)号：US06185212B2
公开(公告)日：2001-02-06
申请号：US09056770
申请日：1998-04-08
申请人： Kenichi Sakamoto , Akio Makimoto , Akihiko Takase , Norihiko Moriwaki , Atsushi Kiuchi
发明人： Kenichi Sakamoto , Akio Makimoto , Akihiko Takase , Norihiko Moriwaki , Atsushi Kiuchi
IPC分类号： H04L1228
CPC分类号： H04L49/254 , H04L49/30 , H04L2012/5681
摘要： An ATM cell processing apparatus including a DRAM for a frame producing buffer of a frame producing unit. In order to absorb the anisotropy of the access rate of the DRAM access, the random access mode of the DRAM access is always used. To compensate a drop in access rate in this case, the DRAM is arranged is an array form and each cell is divided. Resultant partial cell data are written into and read from respective DRAM banks in order. As a result, a fast cell buffer having a large capacity can be formed. The present cell buffer can be applied to a FIFO and the like as well.
摘要翻译：一种ATM信元处理装置，包括用于帧产生单元的帧产生缓冲器的DRAM。为了吸收DRAM访问的访问速率的各向异性，始终使用DRAM访问的随机存取模式。为了补偿这种情况下的访问速率的下降，DRAM被排列成阵列形式，并且每个单元被分割。所产生的部分单元数据按顺序写入和从相应的DRAM存储体读取。结果，可以形成具有大容量的快速电池缓冲器。本单元缓冲器也可以应用于FIFO等。

27. 发明授权

US5926456A Path changing system and method for use in ATM communication apparatus 失效
标题翻译：用于ATM通信设备的路径改变系统和方法
公开(公告)号：US5926456A
公开(公告)日：1999-07-20
申请号：US744630
申请日：1996-11-06
申请人： Masataka Takano , Yoji Oka , Akihiko Takase , Setsuo Takahashi
发明人： Masataka Takano , Yoji Oka , Akihiko Takase , Setsuo Takahashi
IPC分类号： H04Q3/00 , H04L12/801 , H04L12/911 , H04L12/939 , H04Q11/04 , H04J3/14 , H04L12/56
CPC分类号： H04L49/309 , H04L41/0659 , H04L45/10 , H04L45/22 , H04L45/28 , H04L49/25 , H04L49/256 , H04L49/3009 , H04L49/3081 , H04L49/557 , H04L2012/5619 , H04L2012/5627 , H04L49/30 , H04L49/555
摘要： An ATM path changing system and method for use in an ATM communication apparatus and ATM communication network are provided which can set an alternating route in the event of a failure occurring in a transmission line or VP. A header converter in a line controller includes a plurality of output path routing tables, a selector, a comparator, a register for failure RTG and a register for failure VPI and when the contents of the register for failure RTG or VPI coincides with a RTG or VPI of the output path routing tables, an output is selected in accordance with the contents of a selected emergency-route RTG or VPI register.
摘要翻译：提供了一种在ATM通信装置和ATM通信网络中使用的ATM路径改变系统和方法，其可以在传输线路或VP发生故障的情况下设置交替路由。线路控制器中的报头转换器包括多个输出路径路由表，选择器，比较器，用于故障RTG的寄存器和用于故障VPI的寄存器，以及当故障寄存器RTG或VPI的内容与RTG或VPI一致时输出路径路由表的VPI，根据所选紧急路由RTG或VPI寄存器的内容选择输出。

28. 发明授权

US5465348A Trouble diagnosis system of UPC circuit 失效
标题翻译： UPC电路故障诊断系统
公开(公告)号：US5465348A
公开(公告)日：1995-11-07
申请号：US2772
申请日：1993-01-08
申请人： Shigeo Amemiya , Takao Ogura , Takafumi Chujo , Hiroshi Takeo , Michio Kusayanagi , Naoaki Yamanaka , Yoichi Sato , Akihiko Takase , Shigeo Shinada , Mituhiro Takano , Kiyoshi Saitou , Kazuhiko Hohara , Tetuhiro Okabe
发明人： Shigeo Amemiya , Takao Ogura , Takafumi Chujo , Hiroshi Takeo , Michio Kusayanagi , Naoaki Yamanaka , Yoichi Sato , Akihiko Takase , Shigeo Shinada , Mituhiro Takano , Kiyoshi Saitou , Kazuhiko Hohara , Tetuhiro Okabe
IPC分类号： G06F11/20 , H04L12/70 , H04L12/813 , G06F11/00
CPC分类号： H04L49/3081 , H04L12/5602 , H04L2012/5615 , H04L2012/5627 , H04L2012/5628 , H04L2012/5636
摘要： A UPC circuit fault diagnosis system for diagnosing a failure in a UPC circuit controls cell traffic volume on the basis of prescribed information about cell traffic. Failure diagnosis of a UPC circuit is provided by a usage parameter determination of at least one kind of cell, using more than one system and comparing determination results. The diagnosis system has an operating UPC circuit for controlling a total of m kinds of cells, and a standby UPC circuit for controlling a total of n kinds of cells. The system also has a total of q bridge memories for keeping a chronological record of the prescribed information of arriving cells. A fault diagnosis of the bridge memories is provided by comparing the contents of the bridge memories, using more than one system.
摘要翻译：用于诊断UPC电路故障的UPC电路故障诊断系统基于关于小区业务的规定信息来控制小区业务量。 UPC电路的故障诊断由至少一种单元的使用参数确定提供，使用多于一个系统并比较确定结果。诊断系统具有用于控制总共m种单元的操作UPC电路，以及用于控制总共n种单元的备用UPC电路。该系统还具有总共q个桥接存储器，用于保持到达单元的规定信息的按时间顺序的记录。通过使用多个系统比较桥接器的内容来提供桥接器的故障诊断。

29. 发明授权

US5280475A Traffic shaping method and circuit 失效
标题翻译：流量整形方法及电路
公开(公告)号：US5280475A
公开(公告)日：1994-01-18
申请号：US745466
申请日：1991-08-14
申请人： Junichirou Yanagi , Akihiko Takase , Takahiko Kozaki , Shinobu Gohara
发明人： Junichirou Yanagi , Akihiko Takase , Takahiko Kozaki , Shinobu Gohara
IPC分类号： H04Q3/00 , H04L12/815 , H04L12/863 , H04L12/931 , H04L12/951 , H04Q11/04 , H04L12/56
CPC分类号： H04L12/5601 , H04L12/5602 , H04L49/108 , H04L49/255 , H04L49/3081 , H04Q11/0478 , H04L2012/568
摘要： A traffic shaping method and circuit of a packet switching system in which input packets having a fixed length and multiplexed on a plurality of inputs are multiplexed to be delivered on any output of a plurality of outputs, connects the input packet to a list structure using an address chain formed for each output, forms the list structure even for each line identifier provided in the packet, and assigns the identifier for each time slot of the output to take out the packet from the list structure, to thereby prevent the packet having the same identifier from being multiplexed and delivering to the output continuously.
摘要翻译：一种分组交换系统的流量整形方法和电路，其中具有固定长度并在多个输入上复用的输入分组被多路复用以在多个输出的任何输出上传送，将输入分组连接到列表结构，使用为每个输出形成的地址链，甚至对于分组中提供的每个行标识符也形成列表结构，并且分配输出的每个时隙的标识符以从列表结构中取出分组，从而防止具有相同的分组标识符被多路复用并连续传送到输出。

30. 发明授权

US5155487A Cell delineation method and cell delineation circuit 失效
标题翻译：细胞描绘方法和细胞描绘电路
公开(公告)号：US5155487A
公开(公告)日：1992-10-13
申请号：US664115
申请日：1991-03-04
申请人： Katuyoshi Tanaka , Junichirou Yanagi , Akihiko Takase
发明人： Katuyoshi Tanaka , Junichirou Yanagi , Akihiko Takase
IPC分类号： H04L7/08 , H03M13/09 , H04L1/00 , H04L7/00 , H04L7/04 , H04L12/70 , H04L12/951
CPC分类号： H04L1/0061 , H03M13/091 , H04L1/0043 , H04L2012/5674
摘要： In a cell delineation circuit, an input signal is converted into parallel signals, and a plurality of parallel signals (i.e. series of parallel signals) which are shifted one bit by one bit from each other are formed from those parallel signals. CRC (Cyclic Redundancy Check) calculations are executed in parallel for the plurality of parallel signals. A series in which a pattern to be calculated satisfies a CRC rule is determined from results of the CRC calculations, and this series is generated, thereby establishing a cell delineation.
摘要翻译：在单元描绘电路中，输入信号被转换成并行信号，并且由这些并行信号形成彼此移位一比特的多个并行信号（即并行信号串）。针对多个并行信号并行执行CRC（循环冗余校验）计算。根据CRC计算的结果确定其中要计算的模式满足CRC规则的一系列，并且生成该系列，由此建立单元描绘。

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