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21. 发明授权

KR100493040B1 반도체 소자의 커패시터 및 그 제조방법 失效
标题翻译：半导体器件的电容器及其制造方法
公开(公告)号：KR100493040B1
公开(公告)日：2005-06-07
申请号：KR1020020087241
申请日：2002-12-30
申请人： 삼성전자주식회사
发明人： 원석준 , 윤명근 , 정용국 , 권대진
IPC分类号： H01L21/8242
CPC分类号： H01L21/022 , H01L21/02175 , H01L21/02178 , H01L21/02337 , H01L21/3141 , H01L21/3143 , H01L21/31616 , H01L21/31637 , H01L21/31641 , H01L21/31645 , H01L21/31691 , H01L27/10852 , H01L28/40 , H01L28/56 , H01L28/65
摘要： 산화 알루미늄막/고유전체막/산화 알루미늄막으로 구성된 유전막을 포함하는 반도체 소자의 커패시터 및 그 제조방법에 대하여 개시한다. 본 발명에 의한 반도체 소자의 커패시터는 반도체 기판에 형성된 커패시터 하부 전극과 커패시터 하부 전극 상에 산화 알루미늄으로 형성된 제1 유전막, 제1 유전막 상에 산화 알루미늄보다 유전 상수가 큰 물질로 형성된 제2 유전막 및 제2 유전막 상에 산화 알루미늄으로 형성된 제3 유전막으로 구성된 유전막과 이 유전막 상에 형성된 커패시터 상부 전극을 포함한다. 본 발명에 의한 커패시터는 전력의 소모가 적고 고집적화에 유리하도록 단위 면적당 높은 커패시턴스를 갖는 등 여러 가지 전기적 특성이 우수하다.

22. 发明公开

KR1020050040464A 수직으로 연장된 배선간 엠아이엠 커패시터를 갖는로직소자 및 그것을 제조하는 방법 有权
标题翻译：在互连之间具有垂直延伸的金属绝缘体 - 金属电容器的逻辑器件及其形成方法
公开(公告)号：KR1020050040464A
公开(公告)日：2005-05-03
申请号：KR1020030075670
申请日：2003-10-28
申请人： 삼성전자주식회사
发明人： 원석준 , 정용국 , 권대진 , 송민우 , 김원홍
IPC分类号： H01L27/10
CPC分类号： H01L28/91 , H01L21/76807 , H01L21/76838 , H01L27/0805
摘要： 수직으로 연장된 배선간 엠아이엠 커패시터를 갖는 로직소자 및 그것을 제조하는 방법이 개시된다. 상기 로직소자는 반도체 기판을 포함한다. 상기 반도체 기판 상부에 하부배선이 위치하고, 상기 하부배선 상부에 상부배선이 위치한다. 상기 하부배선과 상기 상부배선 사이에 U자형(U-shaped) 하부 금속플레이트가 개재된다. 상기 U자형 하부 금속플레이트는 상기 하부배선에 직접 접한다. 커패시터 유전막이 상기 하부 금속플레이트의 내면(inner surface)을 덮는다. 또한, 상기 커패시터 유전막은 상기 하부 금속플레이트의 가장자리(brim)와 상기 상부배선 사이에 개재된 연장부를 갖는다. 한편, 상부 금속플레이트가 상기 커패시터 유전막의 내면을 덮는다. 상기 상부 금속플레이트는 상기 상부배선에 직접 접하고, 상기 커패시터 유전막에 의해 한정된다.

23. 发明公开

KR1020050033323A 하프늄 산화막의 제조방법 无效
标题翻译：氧化铝膜的制备方法
公开(公告)号：KR1020050033323A
公开(公告)日：2005-04-12
申请号：KR1020030069315
申请日：2003-10-06
申请人： 삼성전자주식회사
发明人： 원석준 , 정용국 , 송민우
IPC分类号： H01L21/316
摘要： A method for fabricating a hafnium oxide film is provided to obtain an improved leakage current characteristic and a higher permittivity than a conventional permittivity by forming a high permittivity layer of hafnium floating state and a leakage current suppression layer. A crystallized high permittivity layer of hafnium floating state (HfxOy;Y=1,X>0.5) is formed on a semiconductor substrate. A leakage current suppression layer oriented along a crystal structure of the high permittivity layer is formed on the crystallized high permittivity layer. The high permittivity layer has a permittivity of 25 to 120. The high permittivity layer having a thickness of 300Å to 1000Å is formed using CVD(chemical vapor deposition) method.
摘要翻译：提供一种制造氧化铪膜的方法，通过形成铪浮动状态的高介电常数层和泄漏电流抑制层，获得比常规介电常数更高的漏电流特性和更高的介电常数。在半导体衬底上形成铪浮态（Hf x O y; Y = 1，X> 0.5）的结晶高介电常数层。在结晶化高电容率层上形成沿着高电容率层的晶体结构取向的漏电流抑制层。高电容率层的介电常数为25〜120。使用CVD（化学气相沉积）法形成厚度为300至1000的高介电常数层。

24. 发明公开

KR1020050028748A 적어도 3층의 고유전막들을 갖는 아날로그 커패시터 및그것을 제조하는 방법 有权
标题翻译：具有至少3层高K电介质层的模拟电容器及其制造方法
公开(公告)号：KR1020050028748A
公开(公告)日：2005-03-23
申请号：KR1020030065272
申请日：2003-09-19
申请人： 삼성전자주식회사
发明人： 정용국 , 원석준 , 권대진 , 김원홍
IPC分类号： H01L27/02
CPC分类号： H01L28/40 , H01L21/31637 , H01L21/31645
摘要： An analog capacitor having at least 3 high-k dielectric layers is provided to optimize a voltage coefficient of capacitance and a leakage current characteristic while having a high-k dielectric layer by making high-k dielectric layer with an excellent voltage coefficient of capacitance come in contact with plates and by interposing a high-k dielectric layer capable of preventing a leakage current between the high-k dielectric layers. A lower plate(11) is formed. An upper plate(15) corresponding to the lower plate is formed. At least three high-k dielectric layers(13) are interposed between the lower and upper plates, including a bottom dielectric layer(13a) in contact with the lower plate, a top dielectric layer(13c) in contact with the upper plate, and a middle dielectric layer(13b) interposed between the bottom and top dielectric layers. Each of bottom and top dielectric layers is a high dielectric layer having a small absolute value of the coefficient of a quadratic term of a voltage coefficient as compared with the middle dielectric layer. The middle dielectric layer is a high dielectric layer having a small leakage current as compared with the bottom and top dielectric layers, respectively.
摘要翻译：提供具有至少3个高k电介质层的模拟电容器，以通过使具有优异的电容电压系数的高k电介质层进入而具有高k电介质层，从而优化电容的电压系数和漏电流特性通过插入能够防止高k电介质层之间的漏电流的高k电介质层与板接触。形成下板（11）。形成对应于下板的上板（15）。至少三个高k电介质层（13）插入在下板和上板之间，包括与下板接触的底电介质层（13a），与上板接触的顶介电层（13c），以及插入在所述底部和顶部电介质层之间的中间介电层（13b）。底部和顶部电介质层是与中间介电层相比具有电压系数的二次项的系数的绝对值小的高介电层。中间介电层是分别与底部和顶部电介质层相比具有小的漏电流的高电介质层。

25. 发明授权

KR100429876B1 고밀도 씨딩층을 갖는 루테늄막을 구비하는 반도체 소자의제조 방법 및 그러한 반도체 소자를 형성하기 위한 제조장비 有权
标题翻译： 고밀도씨을갖는루늄늄막을구을구비하는반체법법및및반비비비비비비비비비비비
公开(公告)号：KR100429876B1
公开(公告)日：2004-05-04
申请号：KR1020010045486
申请日：2001-07-27
申请人： 삼성전자주식회사
发明人： 원석준 , 박순연 , 유차영
IPC分类号： H01L27/04
CPC分类号： H01L28/60 , C23C16/0281 , C23C16/18 , H01L21/28556 , H01L28/55
摘要： A method for fabricating a semiconductor device is provided. The method includes the steps of: forming an insulating layer having an opening region on a semiconductor substrate; forming a first ruthenium layer on the insulating layer and the opening region by sputtering at a first pressure; forming a second ruthenium layer on the first ruthenium layer by first chemical vapor deposition (CVD) at a first flow rate of oxygen gas and at a second pressure, wherein the second pressure is greater than the first pressure; and forming a third ruthenium layer on the second ruthenium layer by second CVD at a second flow rate of oxygen gas and at a third pressure, wherein the third pressure is greater than the first pressure.
摘要翻译：提供了一种用于制造半导体器件的方法。该方法包括以下步骤：在半导体衬底上形成具有开口区域的绝缘层; 在第一压力下通过溅射在绝缘层和开口区域上形成第一钌层; 通过第一化学气相沉积（CVD）以氧气的第一流速和第二压力在所述第一钌层上形成第二钌层，其中所述第二压力大于所述第一压力; 以及以氧气的第二流率和第三压力通过第二CVD在第二钌层上形成第三钌层，其中第三压力大于第一压力。

26. 发明公开

KR1020040000886A 자기 랜덤 액세스 메모리(ＭＲＡＭ) 디바이스 및 그의제조방법 无效
标题翻译：磁性随机存取存储器（MRAM）器件及其制造方法
公开(公告)号：KR1020040000886A
公开(公告)日：2004-01-07
申请号：KR1020020035889
申请日：2002-06-26
申请人： 삼성전자주식회사
发明人： 김현조 , 원석준
IPC分类号： G11C11/15
CPC分类号： G11C11/161 , G11C7/18 , G11C8/14 , H01L43/08 , H01L43/12
摘要： PURPOSE: A magnetic random access memory(MRAM) device and a fabrication method thereof are provided to solve problems due to alien substances and etching damage of a tunnel insulation film. CONSTITUTION: A word line(51) is arranged on a substrate(50) along one direction. The first ferromagnetic material film(53) is formed on an area of the above word line. The second ferromagnetic material film(57a) is formed on an upper part of the first ferromagnetic material film. A tunnel insulation film(56) is formed on the first ferromagnetic material film to cover a bottom plane and sides of the second ferromagnetic material film. And a bit line(58) is arranged along one direction orthogonal to the above word line by being adjacent to the tunnel insulation film and the second ferromagnetic material film.
摘要翻译：目的：提供一种磁性随机存取存储器（MRAM）器件及其制造方法，以解决由外来物质引起的问题和隧道绝缘膜的蚀刻损伤。构成：沿着一个方向在基板（50）上排列字线（51）。第一铁磁材料膜（53）形成在上述字线的区域上。第二铁磁材料膜（57a）形成在第一铁磁材料膜的上部。隧道绝缘膜（56）形成在第一铁磁材料膜上以覆盖第二铁磁材料膜的底面和侧面。并且通过与隧道绝缘膜和第二铁磁材料膜相邻，沿着与上述字线正交的一个方向布置位线（58）。

27. 发明公开

KR1020030046902A 하부 플레이트 전극을 갖는 반도체소자의 캐패시터 및 그제조방법 无效
标题翻译：具有底板电极的半导体电容器及其制造方法
公开(公告)号：KR1020030046902A
公开(公告)日：2003-06-18
申请号：KR1020010077228
申请日：2001-12-07
申请人： 삼성전자주식회사
发明人： 원석준 , 정용국
IPC分类号： H01L27/108
摘要： PURPOSE: A semiconductor capacitor having bottom plate electrode and fabrication method thereof are provided to form a storage electrode of cylinder or stack type instead of a conventional method of exposing a bottom electrode using wet solution. CONSTITUTION: The first interlayer dielectric(205) having a conductive plug(210) is formed on a semiconductor substrate(200). A storage electrode(240) having cylindrical outside and inside parts is formed on the conductive plug. A dielectric layer(235) and plate electrode(230) are formed on the outside part of the storage electrode. A supporting layer beneath a bottom plate electrode(220) is formed to prevent short between the bottom plate electrode and the conductive plug.
摘要翻译：目的：提供具有底板电极的半导体电容器及其制造方法，以形成圆柱体或堆叠型存储电极，而不是使用湿溶液暴露底部电极的常规方法。构成：在半导体衬底（200）上形成具有导电插塞（210）的第一层间电介质（205）。在导电插头上形成具有圆筒形外部和内部的存储电极（240）。在存储电极的外侧部分上形成电介质层（235）和平板电极（230）。形成底板电极（220）下方的支撑层，以防止底板电极和导电插塞之间的短路。

28. 发明公开

KR1020030038831A 커패시터 제조방법 无效
标题翻译：制造电容器的方法
公开(公告)号：KR1020030038831A
公开(公告)日：2003-05-17
申请号：KR1020010068375
申请日：2001-11-03
申请人： 삼성전자주식회사
发明人： 원석준
IPC分类号： H01L27/108
摘要： PURPOSE: A method for manufacturing a capacitor is provided to prevent a storage electrode from falling down due to the penetration of an etch solution into a lower mold layer by completely isolating the lower mold layer. CONSTITUTION: After forming a lower mold layer(206), an etch stop layer(208) and an upper mold layer(210) on a semiconductor substrate(200), a storage electrode hole(212) is formed by sequentially etching the upper mold layer, the etch stop layer and the lower mold layer in order to expose a storage electrode plug(204). A dielectric layer(214) is formed at both sidewalls of the storage electrode hole. After sequentially forming a storage electrode layer and a buffer layer on the resultant structure, a storage electrode(216s) is formed by removing the buffer layer and the storage electrode layer formed on the upper mold layer(210). After forming an upper dielectric layer(220) and a sacrificial isolation layer(222), the etch stop layer(208) is exposed by removing the sacrificial isolation layer(222) and the upper mold layer(210). At this time, the lower mold layer(206) is isolated by the etch stop layer(208) and the dielectric layer(214), so that an etch solution is restrained from penetrating into the lower mold layer(206).
摘要翻译：目的：提供一种用于制造电容器的方法，以防止由于通过完全隔离下模层将蚀刻溶液渗透到下模层中而使存储电极掉落。构成：在形成下模层（206）之后，在半导体衬底（200）上形成蚀刻停止层（208）和上模层（210），存储电极孔（212）通过依次蚀刻上模层，蚀刻停止层和下模层，以便露出存储电极插头（204）。在存储电极孔的两个侧壁处形成电介质层（214）。在所得结构上顺序地形成存储电极层和缓冲层之后，通过去除形成在上模层（210）上的缓冲层和存储电极层，形成存储电极（216s）。在形成上介电层（220）和牺牲隔离层（222）之后，通过去除牺牲隔离层（222）和上模层（210）来暴露蚀刻停止层（208）。此时，下模层（206）通过蚀刻停止层（208）和电介质层（214）隔离，使得蚀刻溶液被阻止渗透到下模层（206）中。

29. 发明公开

KR1020030010518A 귀금속 산화막을 포함하는 층에 주름을 형성하여 집적회로 전극 및 캐패시터를 형성하는 방법, 및 그에 의하여제조되는 집적 회로 전극 및 캐패시터 失效
标题翻译：通过包括金属层和IC电极和电容器的缠绕层形成IC电极和电容器的方法
公开(公告)号：KR1020030010518A
公开(公告)日：2003-02-05
申请号：KR1020020043693
申请日：2002-07-24
申请人： 삼성전자주식회사
发明人： 주재현 , 김완돈 , 원석준
IPC分类号： H01L27/108
CPC分类号： H01L28/84 , H01L28/55 , H01L28/60
摘要： PURPOSE: A method for forming an IC electrode and a capacitor by wrinkling a layer including a noble metal layer and an IC electrode and a capacitor are provided to increase a surface area by forming uniform morphology on the IC electrode including metal without high temperature. CONSTITUTION: A noble metal oxide layer is formed on an upper portion of an IC substrate(110). The noble metal oxide layer is formed with a noble metal such as ruthenium. A wrinkle layer(130) is formed on the noble metal oxide layer by removing partially oxygen from the noble metal oxide layer. The wrinkle layer(130) is formed by exposing the noble metal oxide layer under deoxidation atmosphere. The wrinkles of the wrinkle layer(130) can be formed by deoxidizing the noble metal oxide layer. In addition, the wrinkles can be formed by removing partially compositions of the noble metal oxide layer. The wrinkle layer(130) can be used as an IC electrode. A barrier layer(140) is formed between the IC substrate(110) and the noble metal oxide layer.
摘要翻译：目的：提供通过使包含贵金属层和IC电极和电容器的层起皱来形成IC电极和电容器的方法，以通过在包括金属的IC电极上形成均匀的形态来增加表面积，而不需要高温。构成：在IC基板（110）的上部形成贵金属氧化物层。贵金属氧化物层由钌等贵金属形成。通过从贵金属氧化物层去除部分氧而在贵金属氧化物层上形成皱纹层（130）。通过在脱氧气氛下暴露贵金属氧化物层而形成皱纹层（130）。可以通过使贵金属氧化物层脱氧来形成皱纹层（130）的皱纹。此外，可以通过除去贵金属氧化物层的部分组合物来形成皱纹。皱纹层（130）可以用作IC电极。在IC基板（110）和贵金属氧化物层之间形成阻挡层（140）。

30. 发明公开

KR1020030000555A 금속-절연층-금속 캐패시터 제조 방법 失效
标题翻译： MIM电容器及其制造方法
公开(公告)号：KR1020030000555A
公开(公告)日：2003-01-06
申请号：KR1020010036584
申请日：2001-06-26
申请人： 삼성전자주식회사
发明人： 주재현 , 김완돈 , 원석준 , 박순연
IPC分类号： H01L27/04
CPC分类号： H01L28/84 , H01L28/55 , H01L28/60 , H01L28/90
摘要： PURPOSE: An MIM(Metal-Insulator-Metal) capacitor and a method for fabricating the same are provided to increase an effective area of an MIM capacitor and improve an electrical characteristic of the MIM capacitor. CONSTITUTION: The first interlayer dielectric having a contact plug(810) is prepared. The second interlayer dielectric(820) having an aperture for exposing the contact plug(810) is formed. The first metal layer and the second metal layer are formed on both sidewalls and a bottom of the aperture and an upper face of the second interlayer dielectric(820). An upper surface of the second interlayer dielectric(820) is exposed by polishing the first and the second metal layers. A hemispheric grain bump(837) is formed on an upper surface of the second metal layer(835a) by performing a thermal process. A lower electrode(L2) includes the first metal layer(830a), the unchanged second metal layer(835a), and the hemispheric grain bump(837).
摘要翻译：目的：提供MIM（金属 - 绝缘体 - 金属）电容器及其制造方法，以增加MIM电容器的有效面积并提高MIM电容器的电气特性。构成：制备具有接触塞（810）的第一层间电介质。形成具有用于暴露接触插塞（810）的孔的第二层间电介质（820）。第一金属层和第二金属层形成在孔的两个侧壁和底部以及第二层间电介质（820）的上表面上。第二层间电介质（820）的上表面通过研磨第一金属层和第二金属层而被曝光。通过进行热处理，在第二金属层（835a）的上表面上形成半球形颗粒突起（837）。下电极（L2）包括第一金属层（830a），不变的第二金属层（835a）和半球形颗粒凸块（837）。

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