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    • 22. 发明授权
    • Circuitry and method for an at-speed scan test
    • 用于高速扫描测试的电路和方法
    • US08271841B2
    • 2012-09-18
    • US11762353
    • 2007-06-13
    • Zhen Song Li
    • Zhen Song Li
    • G01R31/30G06F11/00
    • G01R31/318552G01R31/318555G01R31/318594
    • A method for testing an integrated circuit to detect delay faults resulting from a signal path from a first block of the integrated circuit to a second block of the integrated circuit, wherein first and second blocks are running at different application speeds. The method may include shifting first data into scan memory cells of the integrated circuit at a first frequency; applying a launch test clock pulse to the first block at a second frequency; applying a capture test clock pulse to the second block at the second frequency, wherein the first edges of the launch and capture pulses are delayed with respect to each other by a period that is a reciprocal of the second frequency; shifting second data from the scan memory cells to an output at the first frequency; and comparing the second data at the output with expected values.
    • 一种用于测试集成电路以检测从集成电路的第一块到集成电路的第二块的信号路径产生的延迟故障的方法,其中第一和第二块以不同的应用速度运行。 该方法可以包括以第一频率将第一数据移位到集成电路的扫描存储单元中; 以第二频率向第一块应用发射测试时钟脉冲; 以第二频率将捕获测试时钟脉冲施加到第二块,其中发射和捕获脉冲的第一边缘相对于彼此延迟具有第二频率的倒数的周期; 将第二数据从扫描存储单元移位到第一频率的输出; 并将输出中的第二数据与期望值进行比较。