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21. 发明申请

US20110050176A1 BATTERY STATE MONITORING CIRCUIT AND BATTERY DEVICE 有权
标题翻译：电池状态监测电路和电池装置
公开(公告)号：US20110050176A1
公开(公告)日：2011-03-03
申请号：US12874027
申请日：2010-09-01
申请人： Toshiyuki Koike , Atsushi Sakurai , Kazuaki Sano , Wataru Sakamoto , Fumihiko Maetani , Shohei Tsukamoto
发明人： Toshiyuki Koike , Atsushi Sakurai , Kazuaki Sano , Wataru Sakamoto , Fumihiko Maetani , Shohei Tsukamoto
IPC分类号： H02J7/04
CPC分类号： H02J7/0031 , H01M10/42
摘要： Provided are a battery state monitoring circuit and a battery device that are capable of reliably controlling charge by a charger even if a voltage of a secondary battery drops to around 0 V. In the battery device provided with the battery state monitoring circuit, respective gate voltages of a P-type metal oxide semiconductor (PMOS) transistor and an N-type metal oxide semiconductor (NMOS) transistor, which together form a voltage detection circuit for detecting a voltage of around 0 V of the secondary battery, are applied by a voltage dividing resistor circuit that is connected across terminals of the secondary battery.
摘要翻译：提供了即使二次电池的电压下降到0V左右，也能够可靠地控制充电器的电池状态监视电路和电池装置。在设置有电池状态监视电路的电池装置中，各自的栅极电压的P型金属氧化物半导体（PMOS）晶体管和N型金属氧化物半导体（NMOS）晶体管一起形成用于检测二次电池的0V左右的电压的电压检测电路，分压电阻器连接在二次电池的端子上。

22. 发明申请

US20110050172A1 CHARGE/DISCHARGE CONTROL CIRCUIT AND CHARGING TYPE POWER SUPPLY DEVICE 有权
标题翻译：充电/放电控制电路和充电式电源装置
公开(公告)号：US20110050172A1
公开(公告)日：2011-03-03
申请号：US12869128
申请日：2010-08-26
申请人： Kazuaki Sano , Wataru Sakamoto
发明人： Kazuaki Sano , Wataru Sakamoto
IPC分类号： H02J7/00
CPC分类号： H02J7/0026
摘要： Provided are a charge/discharge control circuit and a charging type power supply device which include an intermediate terminal disconnection detection circuit having low current consumption. In the charge/discharge control circuit, a constant current circuit serving as an intermediate terminal disconnection detection circuit is provided to a terminal to which secondary batteries are connected, and includes a depletion type metal oxide semiconductor (MOS) transistor and a resistor connected between a gate terminal and a source terminal of the depletion type MOS transistor.
摘要翻译：提供一种包括具有低电流消耗的中间端子断开检测电路的充电/放电控制电路和充电型电源装置。在充放电控制电路中，作为中间端子断开检测电路的恒流电路被提供给连接有二次电池的端子，并且包括耗尽型金属氧化物半导体（MOS）晶体管和连接在二极管栅极端子和耗尽型MOS晶体管的源极端子。

23. 发明申请

US20100320527A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME 失效
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US20100320527A1
公开(公告)日：2010-12-23
申请号：US12792378
申请日：2010-06-02
申请人： Takayuki OKAMURA , Noboru OOIKE , Wataru SAKAMOTO , Takashi IZUMIDA
发明人： Takayuki OKAMURA , Noboru OOIKE , Wataru SAKAMOTO , Takashi IZUMIDA
IPC分类号： H01L29/792 , H01L21/28
CPC分类号： H01L27/11565 , H01L21/28282 , H01L27/11568
摘要： A nonvolatile semiconductor memory device according to embodiment includes: a semiconductor substrate having an upper portion being partitioned into a plurality of semiconductor portions extending in a first direction; a charge storage film provided on the semiconductor portion; a word-line electrode provided on the semiconductor substrate and extending in a second direction intersecting with the first direction; and a pair of selection gate electrodes provided on both sides of the word-line electrode in the first direction on the semiconductor substrate and extending in the second direction, a shortest distance between a corner portion of each of the semiconductor portions and each of the selection gate electrodes being longer than a shortest distance between the corner portion of the semiconductor portion and the word-line electrode in a cross section parallel to the second direction.
摘要翻译：根据实施例的非易失性半导体存储器件包括：半导体衬底，其具有被分隔成沿第一方向延伸的多个半导体部分的上部; 设置在半导体部分上的电荷存储膜; 字线电极，其设置在所述半导体基板上并沿与所述第一方向交叉的第二方向延伸; 以及一对选择栅电极，其设置在所述半导体基板上的所述字线电极的所述第一方向的两侧，并且沿所述第二方向延伸，所述半导体部分的每个的角部与所述选择中的每一个之间的最短距离栅电极比与半导体部分的角部和字线电极之间的平行于第二方向的截面中的最短距离更长。

24. 发明授权

US06884364B2 Lead-free piezoelectric ceramic composition wherin Cu is contained in (KxA1-x)y(Nb1-zBz)O3perovskite compound, and process of preparing the same 失效
标题翻译：（KxA1-x）y（Nb1-zBz）O3钙钛矿型化合物中含有Cu的无铅压电陶瓷组合物及其制备方法
公开(公告)号：US06884364B2
公开(公告)日：2005-04-26
申请号：US10668004
申请日：2003-09-23
申请人： Fuyutoshi Sato , Shin-ichi Hirano , Masato Matsubara , Wataru Sakamoto , Toshinobu Yogo , Koichi Kikuta
发明人： Fuyutoshi Sato , Shin-ichi Hirano , Masato Matsubara , Wataru Sakamoto , Toshinobu Yogo , Koichi Kikuta
IPC分类号： C04B35/00 , C04B35/46 , C04B35/495 , H01L41/187
CPC分类号： C04B35/495 , C04B35/6303 , C04B2235/3201 , C04B2235/3251 , C04B2235/3255 , C04B2235/3281 , C04B2235/656 , C04B2235/72 , C04B2235/768 , C04B2235/77 , C04B2235/80 , C04B2235/85 , H01L41/1873 , H01L41/43
摘要： A lead-free piezoelectric ceramic composition wherein a suitable amount of Cu is contained in a perovskite compound of a non-stoichiometric composition represented by a formula (KxA1-x)y(Nb1-zBz)O3, wherein “A” represents at least one of Na and Bi, while “B” represents at least one of Ta and Ti, and wherein 0
摘要翻译：一种无铅压电陶瓷组合物，其中在由式（K x x A 1-x-x）表示的非化学计量组成的钙钛矿化合物中含有适量的Cu，）Nb 3（Nb 1-z B z）O 3，其中“A”表示以下中的至少一个： Na和Bi，而“B”表示Ta和Ti中的至少一种，并且其中0 >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>> h 1和n 2个取代的C 1 -C 10烷基。

25. 发明授权

US06317369B1 Semiconductor device allowing higher speed data transmission to and from external unit 有权
标题翻译：半导体器件允许更高速度的数据传输到外部单元
公开(公告)号：US06317369B1
公开(公告)日：2001-11-13
申请号：US09704048
申请日：2000-11-02
申请人： Takashi Kubo , Wataru Sakamoto
发明人： Takashi Kubo , Wataru Sakamoto
IPC分类号： G11C700
CPC分类号： G11C7/1093 , G11C7/1066 , G11C7/1078 , G11C7/1087 , G11C7/22
摘要： When H data is transmitted, an input buffer receives the data by using a rising edge of one of complementary two strobe signals in principle. When L data is transmitted, the input buffer receives the data by using a falling edge of one of the complementary two strobe signals in principle. Since the delay amount of data which changes from L data to H data is almost the same as that of a rising edge of a strobe signal, data is received at high speed according to delay change caused by the polarity of data.
摘要翻译：当发送H数据时，输入缓冲器原则上通过使用互补两个选通信号中的一个的上升沿来接收数据。当发送L数据时，输入缓冲器原则上通过使用互补两个选通信号之一的下降沿来接收数据。由于从L数据变化为H数据的数据的延迟量与选通信号的上升沿的数据的延迟量几乎相同，所以根据由数据的极性引起的延迟变化，高速接收数据。

26. 发明授权

US06184738B2 Input buffer for supplying semiconductor device with internal signal based on comparison of external signal with reference potential 失效
标题翻译：输入缓冲器，用于根据外部信号与参考电位的比较为半导体器件提供内部信号
公开(公告)号：US06184738B2
公开(公告)日：2001-02-06
申请号：US09019199
申请日：1998-02-05
申请人： Hisashi Iwamoto , Aiko Nishino , Wataru Sakamoto
发明人： Hisashi Iwamoto , Aiko Nishino , Wataru Sakamoto
IPC分类号： H03L500
CPC分类号： H03K19/018528
摘要： An input buffer of a semiconductor device is provided. A first voltage shift circuit converts an input signal formed of a low amplitude logic signal overlapping 1.65V or 2.9V to a first signal formed of a complimentary signal formed of the low amplitude logic signal overlapping 2.9V or 1.65V. A second voltage shift circuit converts a reference potential of 1.65V or 2.9V to a second signal of 2.9V or 1.65V. A differential amplifier compares the reference potential with the input signal when the reference potential is 1.65V, and compares the first signal and the second signal when the reference potential is 2.9V. The input buffer thus operates normally whichever of 1.65V and 2.9V is the reference potential.
摘要翻译：提供半导体器件的输入缓冲器。第一电压移位电路将由1.65V或2.9V重叠的低幅度逻辑信号形成的输入信号转换成由与低幅度逻辑信号形成的互补信号形成的第一信号重叠2.9 V或1.65V。第二电压移位电路将1.65V或2.9V的参考电位转换为2.9V或1.65V的第二信号。当参考电位为1.65V时，差分放大器将参考电位与输入信号进行比较，当参考电位为2.9V时，比较第一信号和第二信号。因此，输入缓冲器通常正常为1.65V和2.9V为参考电位。

27. 发明申请

US20190100031A1 DRYING DEVICE, LIQUID DISCHARGE APPARATUS, AND TREATMENT LIQUID APPLICATOR 审中-公开
公开(公告)号：US20190100031A1
公开(公告)日：2019-04-04
申请号：US16040007
申请日：2018-07-19
申请人： Hideaki NISHIMURA , Toshihiro YOSHINUMA , Wataru SAKAMOTO , Sho SAWAHATA , Ken ONODERA
发明人： Hideaki NISHIMURA , Toshihiro YOSHINUMA , Wataru SAKAMOTO , Sho SAWAHATA , Ken ONODERA
IPC分类号： B41J11/00 , B41J29/377 , B41J2/14 , B41F23/04
CPC分类号： B41J11/002 , B41F23/0443 , B41J2/1408 , B41J29/377 , B41J2202/08
摘要： A drying device includes a plurality of blowers to blow air onto an object to be dried, the plurality of blowers being disposed along a direction of conveyance of the object to be dried, and a plurality of heaters to heat air inside the plurality of blowers. Each of the plurality of blowers includes an elongated nozzle arranged along a nozzle direction perpendicular to the direction of conveyance of the object to be dried, and an airflow generator to generate airflow to be blown from the elongated nozzle. The plurality of blowers includes a first blower including the airflow generator at a first end of the first blower in the nozzle direction and a second blower including the airflow generator at a second end of the second blower opposite the first end in the nozzle direction.

28. 发明授权

US08837223B2 Nonvolatile semiconductor memory device and method for manufacuring the same 有权
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US08837223B2
公开(公告)日：2014-09-16
申请号：US13600991
申请日：2012-08-31
申请人： Wataru Sakamoto , Fumitaka Arai , Takashi Kobayashi , Ken Komiya , Shinichi Sotome , Tatsuya Kato
发明人： Wataru Sakamoto , Fumitaka Arai , Takashi Kobayashi , Ken Komiya , Shinichi Sotome , Tatsuya Kato
IPC分类号： G11C16/04 , G11C16/34 , G11C11/56 , H01L21/28 , H01L29/788 , G11C16/10
CPC分类号： G11C16/04 , G11C11/5628 , G11C16/0483 , G11C16/10 , G11C16/3459 , H01L21/28273 , H01L27/11524 , H01L27/11531 , H01L29/788
摘要： A nonvolatile semiconductor memory device according to an embodiment includes: a memory cell array in which a plurality of NAND cell units are arranged, the NAND cell units including a plurality of memory cells, and select gate transistors, the memory cell including a semiconductor layer, a gate insulating film, a charge accumulation layer, and a control gate; and a control circuit. The control circuit adjusts a write condition of each of the memory cells in accordance with write data to each of the memory cells and memory cells adjacent to the memory cells within the data to be written.
摘要翻译：根据实施例的非易失性半导体存储器件包括：其中布置多个NAND单元单元的存储单元阵列，包括多个存储单元的NAND单元单元和选择栅极晶体管，所述存储单元包括半导体层，栅极绝缘膜，电荷蓄积层和控制栅极; 和控制电路。控制电路根据写入数据将每个存储器单元的写入条件调整到与要写入的数据内的存储单元相邻的存储单元和存储单元。

29. 发明申请

US20130235666A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACURING THE SAME 有权
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US20130235666A1
公开(公告)日：2013-09-12
申请号：US13600991
申请日：2012-08-31
申请人： Wataru Sakamoto , Fumitaka Arai , Takashi Kobayashi , Ken Komiya , Shinichi Sotome , Tatsuya Kato
发明人： Wataru Sakamoto , Fumitaka Arai , Takashi Kobayashi , Ken Komiya , Shinichi Sotome , Tatsuya Kato
IPC分类号： G11C16/04 , H01L29/788 , H01L21/28
CPC分类号： G11C16/04 , G11C11/5628 , G11C16/0483 , G11C16/10 , G11C16/3459 , H01L21/28273 , H01L27/11524 , H01L27/11531 , H01L29/788
摘要： A nonvolatile semiconductor memory device according to an embodiment includes: a memory cell array in which a plurality of NAND cell units are arranged, the NAND cell units including a plurality of memory cells, and select gate transistors, the memory cell including a semiconductor layer, a gate insulating film, a charge accumulation layer, and a control gate; and a control circuit. The control circuit adjusts a write condition of each of the memory cells in accordance with write data to each of the memory cells and memory cells adjacent to the memory cells within the data to be written.
摘要翻译：根据实施例的非易失性半导体存储器件包括：其中布置多个NAND单元单元的存储单元阵列，包括多个存储单元的NAND单元单元和选择栅极晶体管，所述存储单元包括半导体层，栅极绝缘膜，电荷蓄积层和控制栅极; 和控制电路。控制电路根据写入数据将每个存储器单元的写入条件调整到与要写入的数据内的存储单元相邻的存储单元和存储单元。

30. 发明申请

US20130207175A1 NONVOLATILE SEMICONDUCTOR STORAGE DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US20130207175A1
公开(公告)日：2013-08-15
申请号：US13589517
申请日：2012-08-20
申请人： Wataru SAKAMOTO
发明人： Wataru SAKAMOTO
IPC分类号： H01L21/3205 , H01L21/82 , H01L27/088
CPC分类号： H01L21/32053 , H01L21/28273 , H01L21/764 , H01L21/82 , H01L27/088 , H01L27/11529 , H01L29/66825
摘要： A nonvolatile semiconductor storage device including a first transistor comprising a first gate electrode including a charge storage layer, an interelectrode insulating film, and a control electrode layer; a second transistor comprising a second gate electrode including a lower electrode, an upper electrode, and an upper silicide portion above the upper electrode; and a third transistor comprising a third gate electrode including a lower electrode, an upper electrode, and an upper silicide portion above the upper electrode; wherein the lower electrodes of the second and the third gate electrodes have a first side and a second side taken along a length direction of the second and the third gate electrodes, the lower electrodes of the second and the third gate electrodes including a lower silicide portion in which at least the first side of the lower electrodes are partially silicided.
摘要翻译：一种非易失性半导体存储装置，包括：第一晶体管，包括包含电荷存储层的第一栅电极，电极间绝缘膜和控制电极层; 第二晶体管，包括在上电极上方包括下电极，上电极和上硅化物部分的第二栅电极; 以及第三晶体管，包括在所述上电极上方包括下电极，上电极和上硅化物部分的第三栅电极; 其中所述第二和第三栅电极的下电极具有沿着所述第二和第三栅电极的长度方向截取的第一侧和第二侧，所述第二和第三栅电极的下电极包括下硅化物部分其中至少第一侧的下部电极部分地被硅化。

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