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21. 发明申请

US20100169968A1 PROCESSOR EXTENSIONS FOR EXECUTION OF SECURE EMBEDDED CONTAINERS 有权
标题翻译：处理器扩展用于执行安全嵌入式集装箱
公开(公告)号：US20100169968A1
公开(公告)日：2010-07-01
申请号：US12347890
申请日：2008-12-31
申请人： Vedvyas Shanbhogue , Arvind Kumar , Purushottam Goel
发明人： Vedvyas Shanbhogue , Arvind Kumar , Purushottam Goel
IPC分类号： G06F12/02 , G06F21/24 , G06F9/50
CPC分类号： G06F12/1408 , G06F9/45558 , G06F9/4812 , G06F9/5077 , G06F2009/45579 , G06F2212/1052 , H04L9/14 , H04L9/3242 , H04L63/168 , H04L2209/24 , Y02D10/22 , Y02D10/24 , Y02D10/36
摘要： Methods and apparatus relating to processor extensions for execution of secure embedded containers are described. In an embodiment, a scalable solution for manageability function is provided, e.g., for UMPC environments or otherwise where utilizing a dedicated processor or microcontroller for manageability is inappropriate or impractical. For example, in an embodiment, an OS (Operating System) or VMM (Virtual Machine Manager) Independent (generally referred to herein as “OI”) architecture involves creating one or more containers on a processor by dynamically partitioning resources (such as processor cycles, memory, devices) between the HOST OS/VMM and the OI container. Other embodiments are also described and claimed.
摘要翻译：描述与用于执行安全嵌入式容器的处理器扩展有关的方法和装置。在一个实施例中，提供了用于可管理性功能的可扩展解决方案，例如对于UMPC环境，或者其他利用专用处理器或微控制器进行可管理性是不合适或不切实际的。例如，在一个实施例中，OS（操作系统）或VMM（虚拟机管理器）独立（本文通常称为“OI”）架构涉及通过动态地划分资源（例如处理器周期）来在处理器上创建一个或多个容器，内存，设备）在HOST OS / VMM和OI容器之间。还描述和要求保护其他实施例。

22. 发明申请

US20090172660A1 NEGOTIATED ASSIGNMENT OF RESOURCES TO A VIRTUAL MACHINE IN A MULTI-VIRTUAL MACHINE ENVIRONMENT 有权
标题翻译：多虚拟机环境中虚拟机资源的协调分配
公开(公告)号：US20090172660A1
公开(公告)日：2009-07-02
申请号：US11964660
申请日：2007-12-26
申请人： Carl G. Klotz, JR. , Steve L. Grobman , Vedvyas Shanbhogue
发明人： Carl G. Klotz, JR. , Steve L. Grobman , Vedvyas Shanbhogue
IPC分类号： G06F9/455
CPC分类号： G06F9/5077
摘要： A system and method are disclosed. In one embodiment the system includes a physical resource that is capable of generating I/O data. The system also includes multiple virtual machines to utilize the physical resource. Among the virtual machines are a resource source virtual machine that is capable of owning the physical resource. The resource source virtual machine is also capable of sending a stream of one or more I/O packets generated from the I/O data that targets a resource sink virtual machine. The resource sink virtual machine is designated as a termination endpoint of the I/O data from the physical device. Also among the virtual machines are one or more resource filter virtual machines. Each of the resource filter virtual machines is capable of filtering I/O packets of a particular type from the stream prior to the stream reaching the resource sink virtual machine.
摘要翻译：公开了一种系统和方法。在一个实施例中，系统包括能够产生I / O数据的物理资源。该系统还包括多个虚拟机来利用物理资源。虚拟机中的资源源虚拟机能够拥有物理资源。资源源虚拟机还能够发送从作为资源宿虚拟机的I / O数据生成的一个或多个I / O包的流。资源宿虚拟机被指定为来自物理设备的I / O数据的终止端点。虚拟机中还有一个或多个资源过滤器虚拟机。每个资源过滤器虚拟机能够在到达资源宿虚拟机的流之前从流中过滤特定类型的I / O分组。

23. 发明申请

US20080244574A1 Dynamically relocating devices between virtual machines 审中-公开
标题翻译：在虚拟机之间动态地重新定位设备
公开(公告)号：US20080244574A1
公开(公告)日：2008-10-02
申请号：US11728429
申请日：2007-03-26
申请人： Vedvyas Shanbhogue , Madhukar Tallam
发明人： Vedvyas Shanbhogue , Madhukar Tallam
IPC分类号： G06F9/455
CPC分类号： G06F9/45558 , G06F2009/45579
摘要： A virtual machine monitor may reassign hardware bus devices from one virtual machine to another. The virtual machine monitor may turn a device off, reassign it to a different virtual machine, and then turn the device back on. Device interrupts are remapped from the source virtual machine to the target virtual machine.
摘要翻译：虚拟机监视器可以将硬件总线设备从一个虚拟机重新分配给另一个虚拟机。虚拟机监视器可能会关闭设备，将其重新分配给其他虚拟机，然后重新打开设备。设备中断从源虚拟机重新映射到目标虚拟机。

24. 发明申请

US20170017791A1 RETURN ADDRESS OVERFLOW BUFFER 有权
标题翻译：返回地址溢出缓冲区
公开(公告)号：US20170017791A1
公开(公告)日：2017-01-19
申请号：US14798134
申请日：2015-07-13
申请人： Jason W. Brandt , Vedvyas Shanbhogue , Baiju Patel
发明人： Jason W. Brandt , Vedvyas Shanbhogue , Baiju Patel
IPC分类号： G06F21/56
CPC分类号： G06F21/52
摘要： Embodiments of an invention for a return address overflow buffer are disclosed. In one embodiment, a processor includes a stack pointer to store a reference to a first return address stored on a stack, an obscured address stack pointer to store a reference to an encrypted second return address stored in a memory, hardware to decrypt the encrypted second return address to generate a decrypted second return address, and a return address verification logic, responsive to receiving a return instruction, to compare the first return address to the decrypted second return address.
摘要翻译：公开了一种用于返回地址溢出缓冲器的发明的实施例。在一个实施例中，处理器包括堆栈指针，用于存储对存储在堆栈上的第一返回地址的引用，模糊地址堆栈指针，用于存储对存储在存储器中的加密的第二返回地址的引用，硬件来解密加密的第二返回地址以产生解密的第二返回地址，以及返回地址验证逻辑，响应于接收到返回指令，将第一返回地址与解密的第二返回地址进行比较。

25. 发明申请

US20160364308A1 PROVIDING AUTONOMOUS SELF-TESTING OF A PROCESSOR 有权
标题翻译：提供处理器的自动自检
公开(公告)号：US20160364308A1
公开(公告)日：2016-12-15
申请号：US14737768
申请日：2015-06-12
申请人： Vedvyas Shanbhogue , Eric Rasmussen , Deep K. Buch , Gordon McFadden , Kameswar Subramaniam , Amy L. Santoni , Willard M. Wiseman , Bret L. Toll
发明人： Vedvyas Shanbhogue , Eric Rasmussen , Deep K. Buch , Gordon McFadden , Kameswar Subramaniam , Amy L. Santoni , Willard M. Wiseman , Bret L. Toll
IPC分类号： G06F11/263 , G06F11/22
CPC分类号： G06F11/2635 , G06F11/1417 , G06F11/1433 , G06F11/2242 , G06F11/2268 , G06F11/27
摘要： In an embodiment, a processor includes at least one core, a power management unit having a first test register including a first field to store a test patch identifier associated with a test patch and a second field to store a test mode indicator to request a core functionality test, and a microcode storage to store microcode to be executed by the at least one core. Responsive to the test patch identifier, the microcode may access a firmware interface table and obtain the test patch from a non-volatile storage according to an address obtained from the firmware interface table. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，处理器包括至少一个核心，功率管理单元，其具有第一测试寄存器，该第一测试寄存器包括第一字段以存储与测试补丁相关联的测试补丁标识符，以及第二字段以存储测试模式指示符以请求核心功能测试，以及微代码存储器，用于存储由所述至少一个核执行的微代码。响应于测试补丁标识符，微代码可以根据从固件接口表获得的地址从非易失性存储器访问固件接口表并获得测试补丁。描述和要求保护其他实施例。

26. 发明申请

US20160180079A1 Execution Profiling Mechanism 有权
标题翻译：执行分析机制
公开(公告)号：US20160180079A1
公开(公告)日：2016-06-23
申请号：US14576665
申请日：2014-12-19
申请人： Ravi L. Sahita , Xiaoning Li , Barry E. Huntley , Ofer Levy , Vedvyas Shanbhogue , Yuriy Bulygin , Ido Ouziel , Michael Lemay , John M. Esper
发明人： Ravi L. Sahita , Xiaoning Li , Barry E. Huntley , Ofer Levy , Vedvyas Shanbhogue , Yuriy Bulygin , Ido Ouziel , Michael Lemay , John M. Esper
IPC分类号： G06F21/52
CPC分类号： G06F21/52 , G06F9/45558 , G06F11/30 , G06F21/554 , G06F2009/45591 , G06F2221/033
摘要： A method comprises filtering branch trap events at a branch event filter, monitoring a branch event filter to capture indirect branch trap events that cause a control flow trap exception, receiving the indirect branch trap events at a handler and the handler processing the indirect branch trap events
摘要翻译：一种方法包括在分支事件过滤器处过滤分支陷阱事件，监视分支事件过滤器以捕获导致控制流陷阱异常的间接分支陷阱事件，在处理器处接收间接分支陷阱事件，并处理处理间接分支陷阱事件

27. 发明申请

US20160117265A1 MAINTAINING A SECURE PROCESSING ENVIRONMENT ACROSS POWER CYCLES 有权
标题翻译：维护安全循环的安全环境
公开(公告)号：US20160117265A1
公开(公告)日：2016-04-28
申请号：US14525421
申请日：2014-10-28
申请人： Francis X. MCKEEN , Vincent Scarlata , Carlos Rozas , Ittai Anati , Vedvyas Shanbhogue
发明人： Francis X. MCKEEN , Vincent Scarlata , Carlos Rozas , Ittai Anati , Vedvyas Shanbhogue
IPC分类号： G06F12/14 , G06F12/08
CPC分类号： G06F12/1416 , G06F9/4418 , G06F12/0804 , G06F12/0875 , G06F12/1408 , G06F12/1441 , G06F21/53 , G06F2212/1016 , G06F2212/1028 , G06F2212/1052 , G06F2212/152 , G06F2212/452 , Y02D10/13
摘要： Embodiments of an invention for maintaining a secure processing environment across power cycles are disclosed. In one embodiment, a processor includes an instruction unit and an execution unit. The instruction unit is to receive an instruction to evict a root version array page entry from a secure cache. The execution unit is to execute the instruction. Execution of the instruction includes generating a blob to contain information to maintain a secure processing environment across a power cycle and storing the blob in a non-volatile memory.
摘要翻译：公开了用于在电力周期内保持安全处理环境的发明的实施例。在一个实施例中，处理器包括指令单元和执行单元。指令单元接收从安全缓存驱逐根版本阵列页条目的指令。执行单元执行指令。该指令的执行包括生成一个blob以包含信息以在整个电源周期内维护一个安全的处理环境，并将该blob存储在一个非易失性存储器中。

28. 发明申请

US20160078222A1 RETURNING TO A CONTROL TRANSFER INSTRUCTION 有权
标题翻译：返回到控制传输指令
公开(公告)号：US20160078222A1
公开(公告)日：2016-03-17
申请号：US14484751
申请日：2014-09-12
申请人： Baiju PATEL , Vedvyas Shanbhogue , Ravi Sahita
发明人： Baiju PATEL , Vedvyas Shanbhogue , Ravi Sahita
IPC分类号： G06F21/52 , G06F9/30 , G06F21/74
CPC分类号： G06F21/52 , G06F9/30003 , G06F9/30054 , G06F9/3836 , G06F21/74 , G06F2221/033
摘要： In an embodiment, the present invention includes a processor having a decode unit and an execution unit. The decode unit is to decode control transfer instructions and the execution unit is to execute control transfer instructions, the control transfer instructions including a call instruction and a return instruction. The processor is to operate in a first mode in which the processor is to raise a fault if a next instruction to be executed immediately after the return instruction is not the call instruction.
摘要翻译：在一个实施例中，本发明包括具有解码单元和执行单元的处理器。解码单元用于解码控制传输指令，并且执行单元执行控制传输指令，控制传输指令包括呼叫指令和返回指令。处理器将在第一模式下操作，其中如果在返回指令之后立即执行的下一个指令不是调用指令，则处理器将引起故障。

29. 发明申请

US20150186659A1 MODIFYING MEMORY PERMISSIONS IN A SECURE PROCESSING ENVIRONMENT 有权
标题翻译：在安全的处理环境中修改存储器许可
公开(公告)号：US20150186659A1
公开(公告)日：2015-07-02
申请号：US14141941
申请日：2013-12-27
申请人： Rebekah LESLIE-HURD , Ilya ALEXANDROVICH , Ittai ANATI , Alex BERENZON , Michael GOLDSMITH , Simon JOHNSON , Francis MCKEEN , Carlos ROZAS , Uday SAVAGAONKAR , Vincent SCARLATA , Vedvyas SHANBHOGUE , Wesley SMITH
发明人： Rebekah LESLIE-HURD , Ilya ALEXANDROVICH , Ittai ANATI , Alex BERENZON , Michael GOLDSMITH , Simon JOHNSON , Francis MCKEEN , Carlos ROZAS , Uday SAVAGAONKAR , Vincent SCARLATA , Vedvyas SHANBHOGUE , Wesley SMITH
IPC分类号： G06F21/60
CPC分类号： G06F21/604 , G06F9/3004 , G06F12/0875 , G06F12/145 , G06F12/1466 , G06F12/1491 , G06F21/72
摘要： Embodiments of an invention for modifying memory permissions in a secure processing environment are disclosed. In one embodiment, a processor includes an instruction unit and an execution unit. The instruction unit is to receive an instruction to modify access permissions for a page in a secure enclave. The execution unit is to execute the instruction. Execution of the instruction includes setting new access permissions in an enclave page cache map entry. Furthermore, the page is immediately accessible from inside the secure enclave according to the new access permissions.
摘要翻译：公开了用于在安全处理环境中修改存储器许可的发明的实施例。在一个实施例中，处理器包括指令单元和执行单元。指令单元将接收修改安全飞地中页面访问权限的指令。执行单元执行指令。执行该指令包括在飞地页面缓存映射条目中设置新的访问权限。此外，根据新的访问权限，该页面可以从安全飞地内部立即访问。

30. 发明申请

US20150121366A1 VIRTUALIZATION EXCEPTIONS 有权
标题翻译：虚拟化例外
公开(公告)号：US20150121366A1
公开(公告)日：2015-04-30
申请号：US14064759
申请日：2013-10-28
申请人： Gilbert Neiger , Mayank Bomb , Manohar Castelino , Robert Chappell , David Durham , Barry Huntley , Anton Ivanov , Madhavan Parthasarathy , Scott Rodgers , Ravi Sahita , Vedvyas Shanbhogue
发明人： Gilbert Neiger , Mayank Bomb , Manohar Castelino , Robert Chappell , David Durham , Barry Huntley , Anton Ivanov , Madhavan Parthasarathy , Scott Rodgers , Ravi Sahita , Vedvyas Shanbhogue
IPC分类号： G06F9/455
CPC分类号： G06F9/45558 , G06F9/30076 , G06F9/45533 , G06F9/4555 , G06F9/4812 , G06F11/07 , G06F2009/45583
摘要： Embodiments of an invention for virtualization exceptions are disclosed. In one embodiment, a processor includes instruction hardware, control logic, and execution hardware. The instruction hardware is to receive a plurality of instructions, including an instruction to enter a virtual machine. The control logic is to determine, in response to a privileged event occurring within the virtual machine, whether to generate a virtualization exception. The execution hardware is to generate a virtualization exception in response to the control logic determining to generate a virtualization exception.
摘要翻译：公开了用于虚拟化异常的发明的实施例。在一个实施例中，处理器包括指令硬件，控制逻辑和执行硬件。指令硬件是接收多个指令，包括进入虚拟机的指令。控制逻辑是为了响应在虚拟机内发生的特权事件来确定是否生成虚拟化异常。执行硬件是响应于控制逻辑确定生成虚拟化异常来生成虚拟化异常。

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