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21. 发明专利

TWI225741B 從一STS/STM酬載中的資料部份、非同步化一DS-3訊號及/或一E3訊號的方法及裝置 METHOD AND APPARATUS FOR DESYNCHRONIZING A DS-3 SIGNAL AND/OR AN E3 SIGNAL FROM THE DATA PORTION OF AN STS/STM PAYLOAD 失效
简体标题：从一STS/STM酬载中的数据部份、异步化一DS-3信号及/或一E3信号的方法及设备 METHOD AND APPARATUS FOR DESYNCHRONIZING A DS-3 SIGNAL AND/OR AN E3 SIGNAL FROM THE DATA PORTION OF AN STS/STM PAYLOAD
公开(公告)号：TWI225741B
公开(公告)日：2004-12-21
申请号：TW091110741
申请日：2002-05-22
申请人：傳斯威曲公司 TRANSWITCH CORPORATION
发明人：丹尼爾C. 雅皮 DANIEL C. UPP
IPC分类号： H04L
CPC分类号： H04J3/076 , H03L7/06
摘要：本發明揭示一種非同步器(desynchronizer)，該同步化器包含兩個FIFO。第一FIFO有兩條位址計數器(寫入與讀取)、一中間計數暫存器、計算寫入與中間計數以及中間計數與讀取計數之間差距的電路系統、一用以執行指標洩漏(pointer leak)及其他算術功能的邏輯區塊，以及一數位控制振盪器(DCO)。第二FIFO有寫入與讀取計數器、一相位頻率偵測器，以及一受制於第二FIFO之長度測量的內部VCO。非同步器接收資料位元、指標移動指示，及來自一DS-3/E3非映射器(demapper)的填充指示(stuff indications)，並以第一FIFO、位址計數器等，將低頻率成分移除掉，包括 SONET/SDH系統間距，以提供第二FIFO一具有高頻率相位調變的DS-3/E3訊號。第二FIFO移除掉剩下的高頻率間距抖動。
简体摘要：本发明揭示一种异步器(desynchronizer)，该同步化器包含两个FIFO。第一FIFO有两条位址计数器(写入与读取)、一中间计数寄存器、计算写入与中间计数以及中间计数与读取计数之间差距的电路系统、一用以运行指针泄漏(pointer leak)及其他算术功能的逻辑区块，以及一数码控制振荡器(DCO)。第二FIFO有写入与读取计数器、一相位频率侦测器，以及一受制于第二FIFO之长度测量的内部VCO。异步器接收数据比特、指针移动指示，及来自一DS-3/E3非映射器(demapper)的填充指示(stuff indications)，并以第一FIFO、位址计数器等，将低频率成分移除掉，包括 SONET/SDH系统间距，以提供第二FIFO一具有高频率相位调制的DS-3/E3信号。第二FIFO移除掉剩下的高频率间距抖动。

22. 发明申请

WO2010074872A1 SYSTEM-ON-A-CHIP AND MULTI-CHIP SYSTEMS SUPPORTING ADVANCED TELECOMMUNICATIONS AND OTHER DATA PROCESSING APPLICATIONS 审中-公开
标题翻译：支持高级电信系统的芯片和多芯片系统及其他数据处理应用
公开(公告)号：WO2010074872A1
公开(公告)日：2010-07-01
申请号：PCT/US2009/065621
申请日：2009-11-24
申请人： TRANSWITCH CORPORATION , HEDDES, Marco , MUKHOPADHYAY, Suvhasis , YEO, Michael, Singngee , RAVASI, Massimo , SHANLEY, Timothy, M. , MALIK, Rakesh, Kumar
发明人： HEDDES, Marco , MUKHOPADHYAY, Suvhasis , YEO, Michael, Singngee , RAVASI, Massimo , SHANLEY, Timothy, M. , MALIK, Rakesh, Kumar
IPC分类号： G06F15/76
CPC分类号： G06F15/7825
摘要： A system-on-chip integrated circuit and multi-chip systems based thereon that are particularly adapted for advanced telecommunications and other advanced data processing applications.
摘要翻译：一种基于片上系统的集成电路和基于其的多芯片系统，其特别适用于高级电信和其他高级数据处理应用。

23. 发明申请

WO2008063921A3 METHODS AND APPARATUS FOR WEIGHTED MULTICASTING OF DATA STREAMS 审中-公开
公开(公告)号：WO2008063921A3
公开(公告)日：2008-05-29
申请号：PCT/US2007/084250
申请日：2007-11-09
申请人： TRANSWITCH CORPORATION , CAGGIONI, Francesco
发明人： CAGGIONI, Francesco
IPC分类号： H04L12/28
摘要： A multicast table which associates data streams with recipients has more values than zero and one. By making this change in multicast tables, several interesting applications can be implemented. Applications include digital TV transmission, combined transmission of different bandwidth signals, video conferencing applications and mirror web server updating applications.

24. 发明申请

WO2007024728A2 COMBINED HARDWARE AND SOFTWARE IMPLEMENTATION OF LINK CAPACITY ADJUSTMENT SCHEME (LCAS) IN SONET (SYNCHRONOUS OPTICAL NETWORK) VIRTUAL CONCATENATION (VCAT) 审中-公开
标题翻译： SONET（同步光网络）虚拟接口（VCAT）中链路容量调整方案（LCAS）的组合硬件和软件实现
公开(公告)号：WO2007024728A2
公开(公告)日：2007-03-01
申请号：PCT/US2006/032429
申请日：2006-08-21
申请人： TRANSWITCH CORPORATION , MALIK, Rakesh, Kumar , MUKHERJEE, Dev, Shankar , CHILWAL, Harsh , GUPTA, Dinesh
发明人： MALIK, Rakesh, Kumar , MUKHERJEE, Dev, Shankar , CHILWAL, Harsh , GUPTA, Dinesh
IPC分类号： H04L12/56
CPC分类号： H04J3/1611
摘要： Combined hardware and software processing is applied in an end node of the network which includes mapping/demapping and deskewing. Most of the LCAS procedure is implemented in software so that it can be modified easily. Some of the procedure is implemented in hardware to meet stringent timing requirements. In particular, the handshaking protocol is implemented in software and the procedure for actually changing of the link capacity in response to the handshaking is implemented in hardware, The hardware and software communicate via a shared memory which includes a receive packet FIFO, receive control and status registers, a transmit packet FIFO, transmit control and status registers, and a transmit time slot interchange table.
摘要翻译：组合的硬件和软件处理应用于网络的终端节点，包括映射/解映射和去歪斜。大多数LCAS程序都是以软件实现的，因此可以轻松修改。一些程序在硬件中实现以满足严格的时序要求。具体来说，握手协议是以软件实现的，并且响应于握手实际改变链路容量的过程在硬件中实现。硬件和软件通过共享存储器进行通信，该共享存储器包括接收分组FIFO，接收控制和状态寄存器，发送包FIFO，发送控制和状态寄存器以及发送时隙交换表。

25. 发明申请

WO2003094403A3 AN ATM DEVICE FOR INCREASING THE NUMBER OF UTOPIA PORTS TO AVOID HEAD OF LINE BLOCKING 审中-公开
公开(公告)号：WO2003094403A3
公开(公告)日：2003-11-13
申请号：PCT/US2003/013049
申请日：2003-04-28
申请人： TRANSWITCH CORPORATION
发明人： SHANLEY, Timothy, M. , PRESTON, Thomas, M. , PARRELLA, Eugene, L. , SRINIVASAN, Desikan, V.
IPC分类号： G01R31/08
摘要： An ATM device (210 in Fig.5) includes means for increasing the number of UTOPIA ports and means for avoiding head of line blocking. Data for a plurality of UTOPIA PHY ports are multiplexed over a first UTOPIA PHY port (216a) and backpressure information is provided to the ATM device via a second UTOPIA PHY port (216b). The backpressure information is preferably formatted in a single 56-byte UTOPIA cell. The means for avoiding head of line blocking includes a scheduler (218), at least one multicast queue (212), at least one unicast queue (214a-214n), a multicast session table (220), a multicast timer (222), and a problem PHY vector (224). Scheduling is alternated between multicast queue(s) and unicast queue(s). If a PHY device in a multicast session is inactive, it is skipped and the next PHY in the session is serviced. When the session has serviced all of the active PHYs and there remain only inactive PHYs in the session table, the session is ended.

26. 发明申请

WO2003005763A2 METHODS AND APPARATUS FOR EXTENDING THE TRANSMISSION RANGE OF UTOPIA INTERFACES AND UTOPIA PACKET INTERFACES 审中-公开
标题翻译：用于扩展UTOPIA接口和UTOPIA分组接口的传输范围的方法和装置
公开(公告)号：WO2003005763A2
公开(公告)日：2003-01-16
申请号：PCT/US2002/021365
申请日：2002-07-03
申请人： TRANSWITCH CORPORATION
发明人： TAN, Zhenping , LIU, Zheng , LIU, Jian , NOVICK, Ronald, P.
IPC分类号： H04Q11/00
CPC分类号： H04L49/9036 , H04L12/5601 , H04L47/50 , H04L47/6235 , H04L49/90 , H04L49/9047 , H04L49/9078 , H04L2012/5616 , H04L2012/5672
摘要： Methods and apparatus for extending the transmission range of a UTOPIA ATM (or packet) interface include providing two UTOPIA extension devices, one for coupling a PHY layer device to a transmission cloud and for coupling an ATM layer (or LINK layer) device to the transmission cloud. Each device includes a UTOPIA interface emulator, a link controller, and a media transceiver. The media transceiver can be made to support various media such as a backplane, copper cable, optical fiber, or a wireless medium. The UTOPIA extension device preferably includes a UTOPIA inlet buffer, a UTOPIA outlet buffer, an inlet clock decoupling buffer, an outlet clock decoupling buffer, and a flow control module. The UTOPIA inlet and outlet buffers are used for traffic management and the clock decoupling buffers allow the UTOPIA interface emulator and the link controller to operate in different clock domains. The link controller provides error control and backpressure delivery to support flow control.
摘要翻译：用于扩展UTOPIA ATM（或分组）接口的传输范围的方法和装置包括提供两个UTOPIA扩展设备，一个用于将PHY层设备耦合到传输云并用于将ATM层（或LINK层）设备耦合到传输云。每个设备包括UTOPIA接口仿真器（20），链路控制器（22）和媒体收发器（24）。媒体收发器可以被制成支持诸如背板，铜缆，光纤或无线介质的各种介质。 UTOPIA扩展设备优选地包括UTOPIA入口缓冲器，UTOPIA插座缓冲器，入口时钟解耦缓冲器，出口时钟解耦缓冲器和流控制模块。 UTOPIA入口和出口缓冲器用于流量管理，时钟去耦缓冲器允许UTOPIA接口仿真器和链路控制器在不同的时钟域中工作。链路控制器提供错误控制和反压输送以支持流量控制。

27. 发明申请

WO1996002095A1 TWO STAGE CLOCK DEJITTER CIRCUIT FOR REGENERATING AN E4 TELECOMMUNICATIONS SIGNAL FROM THE DATA COMPONENT OF AN STS-3C SIGNAL 审中-公开
标题翻译：用于从STS-3C信号的数据组件再生E4电信信号的两级时钟鉴权电路
公开(公告)号：WO1996002095A1
公开(公告)日：1996-01-25
申请号：PCT/US1995008260
申请日：1995-06-30
申请人： TRANSWITCH CORPORATION
发明人： TRANSWITCH CORPORATION , UPP, Daniel, C.
IPC分类号： H04J03/22
CPC分类号： G06F5/12 , G06F2205/061 , G06F2205/126 , H04J3/076
摘要： A two stage desynchronizer (10) is provided to receive a gapped data component of an STS-3C(STM-1) signal and provide therefrom an ungapped DS-4NA (E4) data signal. The first stage (10a) includes a data byte formation block which takes the gapped STS-3C payload data and formulates the data into bytes, a first FIFO (25) which receives the bytes, and a first FIFO read controller (30) which utilizes the STS-3C clock signal and causes bytes of data to be read out according to a schedule which reads bytes eight or nine times out of every ten STS-3C clock cycles. For each row (270 byte times) of the STS-3C frame, either 241 or 242 bytes are read out of the FIFO according to a slightly gapped schedule where the reading of the 242nd byte at least partially depends upon the number of stuffs in the signal and the pointer movements received. The second stage (10b) of the desynchronizer (10) includes a second FIFO (50), a second FIFO fullness measurement block (60), and a VCXO (80). The second FIFO fullness measurement block (60) uses the incoming slightly gapped byte clock and the ungapped DS-4NA output clock as inputs for effectively measuring the relative fullness of the second FIFO (50), and provides a control signal based on the relative fullness.
摘要翻译：提供两级去同步器（10）以接收STS-3C（STM-1）信号的间隙数据分量，从而提供无差异的DS-4NA（E4）数据信号。第一级（10a）包括数据字节形成块，其获取有间隙的STS-3C有效载荷数据并将数据形成为字节，接收字节的第一FIFO（25）和第一FIFO读控制器（30），其利用 STS-3C时钟信号，并根据在每十个STS-3C时钟周期中读取字节八或九次的调度来读出数据字节。对于STS-3C帧的每一行（270字节时间），根据稍微有间隙的时间表，从FIFO读出241或242字节，其中第242个字节的读取至少部分地取决于信号和指针移动接收。去同步器（10）的第二级（10b）包括第二FIFO（50），第二FIFO满度测量块（60）和VCXO（80）。第二FIFO饱和度测量块（60）使用输入的稍微有间隙的字节时钟和无间隙DS-4NA输出时钟作为有效测量第二FIFO（50）的相对丰满度的输入，并且基于相对丰满度提供控制信号。

28. 发明申请

WO1995034145A1 APPARATUS AND METHOD FOR LIMITING JITTER IN A TELECOMMUNICATIONS SIGNAL 审中-公开
标题翻译：电信信号限制抖动的装置和方法
公开(公告)号：WO1995034145A1
公开(公告)日：1995-12-14
申请号：PCT/US1995007020
申请日：1995-06-02
申请人： TRANSWITCH CORPORATION
发明人： TRANSWITCH CORPORATION , NG, Tat, K. , D'JAMOOS, Michael
IPC分类号： H04J03/07
CPC分类号： H04J3/076 , H04J3/0623
摘要： In a system where jitter in a first telecommunications signal (e.g., TUG-3) which is being mapped into a second telecommunications signal (e.g., STS-3C) is reduced by moving the TUG-3 pointer in the opposite direction of the pointer movement of STS-3C signal, the improvement is in suspending FIFO measurement (504) from the time of the STS-3C pointer movement until the next TUG-3 stuff or destuff, and in further limiting jitter by moving the measurement points for the TUG-3 FIFO measurements without conducting TUG-3 pointer movements when the TUG-3 pointer movement would otherwise be moved into or over the transport overhead of the TUG-3 signal. The TUG-3 pointer movement is held in abeyance until two additional pointer movements in the same direction are received, and then the jump is made.
摘要翻译：在其中映射到第二电信信号（例如，STS-3C）的第一电信信号（例如，TUG-3）中的抖动通过在指针移动的相反方向上移动TUG-3指针而减小的系统中 STS-3C信号的改进是从STS-3C指针移动时间到暂停FIFO测量（504）直到下一个TUG-3填充或破坏，并且通过移动TUG-3的测量点进一步限制抖动，当TUG-3指针移动否则将移动到TUG-3信号的传输开销中或之上时，不进行TUG-3指针移动的3个FIFO测量。 TUG-3指针移动被保持，直到接收到相同方向上的两个附加指针移动，然后跳转。

29. 发明申请

WO1995008887A1 ASYNCHRONOUS DATA TRANSFER AND SOURCE TRAFFIC CONTROL SYSTEM 审中-公开
标题翻译：非同步数据传输和源交通控制系统
公开(公告)号：WO1995008887A1
公开(公告)日：1995-03-30
申请号：PCT/US1994010642
申请日：1994-09-20
申请人： TRANSWITCH CORPORATION
发明人： TRANSWITCH CORPORATION , UPP, Daniel, C.
IPC分类号： H04L12/403
CPC分类号： H04L12/5601 , H04L12/403 , H04L12/4035 , H04L2012/5613 , H04L2012/5615 , H04L2012/5679 , H04Q11/0478
摘要： An asynchronous data transfer and source traffic control system includes a bus master (100) and a plurality of bus users (112, 114, 116) coupled to a bidirectional data bus (120-128). The bus master (100) provides two clock signals (120, 122) to each bus user (112, 114, 116), a system clock (120) and a frame clock (122). The frame clock designates the start of a frame. A frame format preferably includes fifteen or sixteen system clock cycles, the first of which is designated the request field and the last of which includes a grant field. One or more other cycles may be assigned control and/or routing information and the remainder of the cycles comprise a data field of fixed length. During the request field, any number of bus users (112, 114, 116) may request access which is received by the bus master (100). During the grant field, the bus master (100) grants access to a selected bus user (112, 114, 116) for the entire data portion of the next frame. Which user (112, 114, 116) is granted access to the next frame is determined according to an arbitration algorithm in the bus master (100) which may be unknown to the bus users (112, 114, 116). The asynchronous data transfer and source traffic control system has particular application in accommodating the transfer of the contents of ATM cells used in BISDN systems.
摘要翻译：异步数据传输和源流量控制系统包括耦合到双向数据总线（120-128）的总线主机（100）和多个总线用户（112,114,116）。总线主机（100）向每个总线用户（112,114,116），系统时钟（120）和帧时钟（122）提供两个时钟信号（120,122）。帧时钟指定帧的开始。帧格式优选地包括十五或十六个系统时钟周期，其中第一个被指定为请求字段，其中最后一个包括授权字段。一个或多个其它周期可被分配控制和/或路由信息，并且其余周期包括固定长度的数据字段。在请求字段期间，任何数量的总线用户（112,114,116）可请求由总线主机（100）接收的访问。在授权字段期间，总线主机（100）授权对下一帧的整个数据部分的所选总线用户（112,114,116）的访问。根据总线主机（100）中可能对总线用户（112,114,116）可能是未知的仲裁算法来确定哪个用户（112,114,116）被授权对下一帧的访问。异步数据传输和源流量控制系统在适应BISDN系统中使用的ATM信元的内容传输方面具有特殊的应用。

30. 发明申请

WO1990006660A1 VIRTUAL TRIBUTARY CROSS CONNECT SWITCH AND SWITCH NETWORK UTILIZING THE SAME 审中-公开
标题翻译：虚拟交互式连接开关和开关网络
公开(公告)号：WO1990006660A1
公开(公告)日：1990-06-14
申请号：PCT/US1989005491
申请日：1989-12-05
申请人： TRANSWITCH CORPORATION
发明人： TRANSWITCH CORPORATION , UPP, Daniel, C.
IPC分类号： H04Q11/04
CPC分类号： H04Q11/04 , H04J3/0623 , H04J3/1611
摘要： Switching components and switching networks utilizing a plurality of identical switching components are provided for cross-connecting virtual tributaries of a plurality of substantially SONET formatted signals. The switching components each receive at least one SONET formatted signal and disassemble the signal into its virtual tributary (VT) payload components while marking the V5 byte. The VT data is buffered and switched in phase, time, and space to effect the cross-connect onto SONET signal generating output buses which are synchronously clocked buses running through the switching components. The space switch (110-a1...110-a28) is essentially a non-blocking switch matrix. The time switch (110-a1...110a28) is a comparison means associated with each incoming VT which compares the VT destination of the data in the buffer (110-a1...110a28) to a virtual tributary time indication based on the phase of the synchronous clocked output buses. When the bus phase is indicative of the VT destination of the data, the data is sent to the output bus (160-1...160-32) dictated by the space switch connection.

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