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21. 发明申请

US20120056672A1 Class-AB/B amplifier and quiescent control circuit for implementation with same 失效
公开(公告)号：US20120056672A1
公开(公告)日：2012-03-08
申请号：US12807403
申请日：2010-09-03
申请人： Sherif Galal , Alex Jianzhong Chen , Khaled Abdelfattah , Todd L. Brooks
发明人： Sherif Galal , Alex Jianzhong Chen , Khaled Abdelfattah , Todd L. Brooks
IPC分类号： H03F3/16
CPC分类号： H03F3/211 , H03F1/301 , H03F3/3022 , H03F2200/375 , H03F2200/453 , H03F2203/30015
摘要： Disclosed is a Class-AB/B amplifier comprising a first output stage including a first plurality of amplification devices and a second output stage including a second plurality of amplification devices. According to one embodiment, the first output stage operates when the Class-AB/B amplifier is in a quiescent state and the second output stage operates when the Class-AB/B amplifier is in an active state. The Class-AB/B amplifier also comprises a level shifting circuit that adjusts a control voltage of the second output stage, where the level shifting circuit is adapted to activate the second output stage when the Class-AB/B amplifier enters the active state. Embodiments of the Class-AB/B amplifier may include a level shifting circuit that implements either a fixed or signal-dependent level shift, and a quiescent control circuit that substantially eliminates any systematic offset arising from the active feedback circuit inside the replica bias circuit.

22. 发明授权

US08103022B2 Method and system for detecting, and controlling power for, an auxiliary microphone 有权
标题翻译：用于检测和控制辅助麦克风的电源的方法和系统
公开(公告)号：US08103022B2
公开(公告)日：2012-01-24
申请号：US11565576
申请日：2006-11-30
申请人： Hongwei Kong , Nelson Sollenberger , Li Fung Chang , Andy Tong , Todd L. Brooks , Claude Hayek
发明人： Hongwei Kong , Nelson Sollenberger , Li Fung Chang , Andy Tong , Todd L. Brooks , Claude Hayek
IPC分类号： H04R3/00 , H04B1/38
CPC分类号： H04R5/04 , H04R2420/01 , H04R2420/07 , H04R2499/11
摘要： Methods and systems for detecting, and controlling power for, an auxiliary microphone are disclosed. Aspects of one method may include a detection block intermittently enabling a bias circuit block to provide a bias signal to determine if an auxiliary microphone may be communicatively coupled to a mobile device. The detection block may process 1-bit digital samples received from the bias circuit bock to determine whether the auxiliary microphone may be communicatively coupled. The detection block may also process the 1-bit digital samples to determine if a button associated with the auxiliary microphone may have been pushed or activated.
摘要翻译：公开了用于检测和控制辅助麦克风的功率的方法和系统。一种方法的方面可以包括间歇地使得偏置电路块提供偏置信号以确定辅助麦克风是否可通信地耦合到移动设备的检测块。检测块可以处理从偏置电路块接收的1位数字样本，以确定辅助麦克风是否可以通信耦合。检测块还可以处理1位数字样本，以确定与辅助麦克风相关联的按钮是否可能被推动或激活。

23. 发明授权

US08018363B2 Nonlinear mapping in digital-to-analog and analog-to-digital converters 有权
标题翻译：数模转换器和模数转换器的非线性映射
公开(公告)号：US08018363B2
公开(公告)日：2011-09-13
申请号：US12557352
申请日：2009-09-10
申请人： Todd L. Brooks , Kevin L. Miller , Josephus A. Van Engelen
发明人： Todd L. Brooks , Kevin L. Miller , Josephus A. Van Engelen
IPC分类号： H03M3/00
CPC分类号： H03M7/3013
摘要： In a high-fidelity digital modulator, a mapper is provided to minimize quantization noise, jitter, and cross-talk between multiple digital-to-analog or analog-to-digital converters. The mapper receives a quantized level from a quantizer and maps the quantized level to an output sequence. The mapper includes a table defining multiple sequences corresponding to each quantized level. Each sequence includes two or more symbols, having one of multiple values. The mapper also includes a generator that selects one of the multiple sequences as the output sequence. The last symbol of a first output sequence is equal to the first symbol of the next output sequence and so on. The generator selects the output sequence by alternating between a first and a second sequence for each quantized level received. The generator selects the output sequence by alternating between sequences having a positive and a negative common mode energy for each odd valued quantized level received.
摘要翻译：在高保真数字调制器中，提供映射器以最小化多个数模转换器或模数转换器之间的量化噪声，抖动和串扰。映射器从量化器接收量化电平，并将量化电平映射到输出序列。映射器包括定义对应于每个量化级别的多个序列的表。每个序列包括具有多个值之一的两个或多个符号。映射器还包括选择多个序列之一作为输出序列的发生器。第一个输出序列的最后一个符号等于下一个输出序列的第一个符号，依此类推。发生器通过在接收到的每个量化级别的第一和第二序列之间交替来选择输出序列。发生器通过在接收到的每个奇数值量化电平具有正和负共模能量的序列之间交替来选择输出序列。

24. 发明申请

US20100066580A1 Nonlinear Mapping in Digital-to-Analog and Analog-to-Digital Converters 有权
标题翻译：数模转换器和模数转换器的非线性映射
公开(公告)号：US20100066580A1
公开(公告)日：2010-03-18
申请号：US12557352
申请日：2009-09-10
申请人： Todd L. BROOKS , Kevin L. MILLER , Josephus A. VAN ENGELEN
发明人： Todd L. BROOKS , Kevin L. MILLER , Josephus A. VAN ENGELEN
IPC分类号： H03M1/12 , H04N7/26
CPC分类号： H03M7/3013
摘要： In a high-fidelity digital modulator, a mapper is provided to minimize quantization noise, jitter, and cross-talk between multiple digital-to-analog or analog-to-digital converters. The mapper receives a quantized level from a quantizer and maps the quantized level to an output sequence. The mapper includes a table defining multiple sequences corresponding to each quantized level. Each sequence includes two or more symbols, having one of multiple values. The mapper also includes a generator that selects one of the multiple sequences as the output sequence. The last symbol of a first output sequence is equal to the first symbol of the next output sequence and so on. The generator selects the output sequence by alternating between a first and a second sequence for each quantized level received. The generator selects the output sequence by alternating between sequences having a positive and a negative common mode energy for each odd valued quantized level received.
摘要翻译：在高保真数字调制器中，提供映射器以最小化多个数模转换器或模数转换器之间的量化噪声，抖动和串扰。映射器从量化器接收量化电平，并将量化电平映射到输出序列。映射器包括定义对应于每个量化级别的多个序列的表。每个序列包括具有多个值之一的两个或多个符号。映射器还包括选择多个序列之一作为输出序列的发生器。第一个输出序列的最后一个符号等于下一个输出序列的第一个符号，依此类推。发生器通过在接收到的每个量化级别的第一和第二序列之间交替来选择输出序列。发生器通过在接收到的每个奇数值量化电平具有正和负共模能量的序列之间交替来选择输出序列。

25. 发明申请

US20100057471A1 METHOD AND SYSTEM FOR PROCESSING AUDIO SIGNALS VIA SEPARATE INPUT AND OUTPUT PROCESSING PATHS 审中-公开
标题翻译：通过分离输入和输出处理程序处理音频信号的方法和系统
公开(公告)号：US20100057471A1
公开(公告)日：2010-03-04
申请号：US12248426
申请日：2008-10-09
申请人： Hongwei Kong , Nelson Sollenberger , Taiyi Cheng , Mark Hahm , Todd L. Brooks , Xicheng Jiang
发明人： Hongwei Kong , Nelson Sollenberger , Taiyi Cheng , Mark Hahm , Todd L. Brooks , Xicheng Jiang
IPC分类号： G10L19/00
CPC分类号： H04M1/6025 , H04R1/1091 , H04R25/554 , H04R27/00 , H04R2227/003 , H04R2420/07
摘要： Aspects of a method and system for processing audio signals via separate input and output processing paths are provided. In this regard, a hardware audio CODEC comprising one or more audio inputs and one or more audio outputs and may be enabled to route, via one or more switching elements, audio signals from any of the inputs to any of the outputs. The CODEC may be enabled to simultaneously process a plurality of audio signals based on a configuration of the switching elements. Upstream from the switching elements, received audio signals may be processed independent of an output to which the may be communicated. Downstream from said switching elements audio signals may be processed independent of an input via which the signals were received.
摘要翻译：提供了通过单独的输入和输出处理路径处理音频信号的方法和系统的方面。在这方面，包括一个或多个音频输入和一个或多个音频输出的硬件音频编解码器，并且可以使得能够经由一个或多个开关元件将来自任何输入的音频信号路由到任何输出。可以使CODEC可以基于开关元件的配置来同时处理多个音频信号。从开关元件的上游，接收的音频信号可以独立于可以被传送到的输出进行处理。来自所述开关元件的下游音频信号可以独立于接收信号的输入进行处理。

26. 发明授权

US07211843B2 System and method for programming a memory cell 有权
标题翻译：用于编程存储器单元的系统和方法
公开(公告)号：US07211843B2
公开(公告)日：2007-05-01
申请号：US10355260
申请日：2003-01-31
申请人： Khim L. Low , Todd L. Brooks , Agnes Woo , Akira Ito
发明人： Khim L. Low , Todd L. Brooks , Agnes Woo , Akira Ito
IPC分类号： H01L27/10
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： The present invention relates to systems and methods for programming a memory cell. More specifically, the present invention relates to a controlled application of current to a memory cell over a controlled time period. The invention utilizes a current mirror configuration having a first transistor and a second transistor, wherein the second transistor is coupled to the memory cell. Programming of the memory cell includes applying a voltage to the first transistor, whereby a first current is generated in the first transistor. A gate of the second transistor is coupled to the first transistor, whereby a second current is generated in the second transistor. The second current is proportional to the first current. The second current is provided to the memory cell, whereby the second current programs the memory cell.
摘要翻译：本发明涉及用于编程存储器单元的系统和方法。更具体地说，本发明涉及在受控时间段内对存储器单元的电流的受控应用。本发明利用具有第一晶体管和第二晶体管的电流镜配置，其中第二晶体管耦合到存储单元。存储单元的编程包括向第一晶体管施加电压，由此在第一晶体管中产生第一电流。第二晶体管的栅极耦合到第一晶体管，由此在第二晶体管中产生第二电流。第二电流与第一电流成比例。第二电流被提供给存储器单元，由此第二电流对存储单元进行编程。

27. 发明授权

US07049848B2 Linear buffer 有权
公开(公告)号：US07049848B2
公开(公告)日：2006-05-23
申请号：US10626701
申请日：2003-07-25
申请人： Todd L. Brooks , Anilkumar V. Tammineedi
发明人： Todd L. Brooks , Anilkumar V. Tammineedi
IPC分类号： H03K19/0175 , H03K19/094
CPC分类号： H03F1/3205 , H03F3/005 , H03F3/45475 , H03F3/505 , H03F2200/168 , H03F2200/331 , H03F2200/417 , H03F2200/453 , H03F2203/45101 , H03F2203/5031
摘要： A source-follower transistor based buffer provides high linearity. A replica transistor is used to generate a replica voltage substantially equal to the output voltage of the buffer. The replica voltage is level shifted by a level shift circuit and applied at the drain of the source-follower transistor to improve the linearity of the buffer. The buffer may be used in conjunction with a switched-capacitor sampling circuit. A damping circuit may be used to reduce charge glitches due to sampling. The damping circuit may be a low pass filter. The buffer may be used in an interface circuit that produces an output signal from an input signal and controls the level of the output signal.

28. 发明授权

US06735302B1 DSP based SLIC architecture with current-sensing voltage synthesis impedance matching and DC feed control 有权
标题翻译：基于DSP的SLIC架构，具有电流感应电压合成阻抗匹配和直流馈电控制
公开(公告)号：US06735302B1
公开(公告)日：2004-05-11
申请号：US09579932
申请日：2000-05-26
申请人： Steven L. Caine , Todd L. Brooks
发明人： Steven L. Caine , Todd L. Brooks
IPC分类号： H04M1900
CPC分类号： H04L25/0278 , H03F3/217 , H03F3/3008 , H03F3/3069 , H03F3/68 , H04L25/0284 , H04L25/0296 , H04M19/005
摘要： A CODEC and a SLIC assembly perform current-sensing-voltage synthesis impedance matching and DC feed control functions. Signal processing that does not require high voltage, such as impedance matching and DC feed control, is performed in the digital domain by the CODEC while the SLIC assembly includes high voltage circuitry. This configuration is useful for Voice over Internet Protocol (VOIP) applications with a short subscriber line loop or other long loop applications. The SLIC includes high voltage operational amplifiers (op amps) to drive ring and tip signals. Bipolar transistors are also provided as bias compensating diodes for bias point stabilization over dynamic operating conditions such as temperature. The high voltage op amps include a composite MOSFET-bipolar complimentary symmetry driver stage that offers the bias control and stability of a bipolar device topology and drive capabilities of a power MOSFET device.
摘要翻译： CODEC和SLIC组件执行电流感测电压合成阻抗匹配和直流馈电控制功能。不需要高电压的信号处理（如阻抗匹配和直流馈电控制）在数字域中由CODEC执行，而SLIC组件包括高压电路。此配置对于具有短用户线路环路或其他长环路应用的语音互联网协议（VOIP）应用是有用的。 SLIC包括高压运算放大器（运算放大器）来驱动环形和尖端信号。双极晶体管也被提供作为偏置补偿二极管，用于在诸如温度的动态工作条件下的偏置点稳定。高压运算放大器包括复合MOSFET - 双极互补对称驱动器级，可提供双极型器件拓扑结构的偏置控制和稳定性以及功率MOSFET器件的驱动能力。

29. 发明授权

US6124813A Self-linearizing multi-bit DACs 失效
标题翻译：自动线性化多位DAC
公开(公告)号：US6124813A
公开(公告)日：2000-09-26
申请号：US870981
申请日：1997-06-06
申请人： David Robertson , Anthony Del Muro , Steve Harston , Todd L. Brooks
发明人： David Robertson , Anthony Del Muro , Steve Harston , Todd L. Brooks
IPC分类号： H03M1/06 , H03M1/74 , H03M3/00
CPC分类号： H03M1/0665 , H03M1/74 , H03M3/464
摘要： Improved data scramblers and swapper cells and improved digital to analog converters are provided. The improved swapper cells permit data to be propagated through the cell immediately upon receipt. The determination of whether to swap data or pass it directly through is based on a history of data values propagated through the cell, but is independent of the values of the particular inputs being swapped. The data scrambler is structured to permit the possible data inputs on swapper cells in the scrambler to be restricted. A minimum delay data scrambler for use in a fast digital to analog converter is disclosed using these components.
摘要翻译：提供了改进的数据加扰器和交换器单元以及改进的数模转换器。改进的交换器单元允许在收到数据后立即传播数据。是否交换数据或直接传递数据的确定是基于通过单元格传播的数据值的历史记录，而是独立于要交换的特定输入的值。数据加扰器被构造成允许加扰器中交换器单元上的可能的数据输入被限制。使用这些组件公开了用于快速数模转换器的最小延迟数据扰频器。

30. 发明授权

US5854574A Reference buffer with multiple gain stages for large, controlled effective transconductance 失效
标题翻译：具有多个增益级的参考缓冲器，用于大的，受控的有效跨导
公开(公告)号：US5854574A
公开(公告)日：1998-12-29
申请号：US639208
申请日：1996-04-26
申请人： Lawrence Singer , Todd L. Brooks
发明人： Lawrence Singer , Todd L. Brooks
IPC分类号： H03F3/30 , H03F3/45 , H03F1/34 , H03F1/42
CPC分类号： H03F3/45659 , H03F3/3028 , H03F3/45183 , H03F3/45946 , H03F2203/45068 , H03F2203/45216 , H03F2203/45352 , H03F2203/45508 , H03F2203/45644 , H03F2203/45658
摘要： A reference buffer suitable for driving switched-capacitor or resistive load circuits provides a very low output impedance. The reference buffer utilizes an amplifier with a very large and controlled transconductance configured in feedback and compensated by a load capacitance. Cascaded gain stages are used to provide a large, controlled transconductance. In one embodiment, a reference buffer amplifier includes a plurality of voltage gain amplifiers connected in cascade and at least one transconductance amplifier connected to a last-connected of the plurality of voltage gain amplifiers. The amplifier may further include at least one current mirror amplifier connected to the at least one transconductance amplifier. In another embodiment, the reference buffer amplifier includes at least one transconductance amplifier and at least one current mirror amplifier cascade-connected to the at least one transconductance amplifier. The amplifiers can be differential or single-ended.
摘要翻译：适用于驱动开关电容或电阻负载电路的参考缓冲器提供非常低的输出阻抗。参考缓冲器使用具有非常大的和受控跨导的放大器，其配置为反馈并由负载电容补偿。级联增益级用于提供大的受控跨导。在一个实施例中，参考缓冲放大器包括串联连接的多个电压增益放大器和连接到多个电压增益放大器的最后连接的至少一个跨导放大器。放大器还可以包括连接到至少一个跨导放大器的至少一个电流镜放大器。在另一个实施例中，参考缓冲放大器包括至少一个跨导放大器和与至少一个跨导放大器级联连接的至少一个电流镜放大器。放大器可以是差分或单端。

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