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21. 发明申请

US20110109366A1 Method and Apparatus to Limit Circuit Delay Dependence on Voltage for Single Phase Transition 失效
标题翻译：限制电路延迟依赖于单相转换电压的方法和装置
公开(公告)号：US20110109366A1
公开(公告)日：2011-05-12
申请号：US12613673
申请日：2009-11-06
申请人： Derick G. Behrends , Todd A. Christensen , Travis R. Hebig , Daniel M. Nelson
发明人： Derick G. Behrends , Todd A. Christensen , Travis R. Hebig , Daniel M. Nelson
IPC分类号： H03H11/26
CPC分类号： H03K5/1534 , H03K5/133
摘要： A delay circuit receives a data input having an input transition and that generates a data output having an output transition. The delay circuit is powered by a voltage source having a voltage. A first delay element is configured to generate a first data signal with a first edge that has a relatively constant delay relative to the input transition irrespective of the voltage of the voltage source. A second delay element is configured to generate a second data signal with a second edge that has a delay relative to the input transition as a function of the voltage of the voltage source. A selection element causes the output transition at the data output to correspond to a latest selected one of the first edge and the second edge. The delay circuit may be employed in a pulse generating circuit.
摘要翻译：延迟电路接收具有输入转变的数据输入并产生具有输出转变的数据输出。延迟电路由具有电压的电压源供电。第一延迟元件被配置为产生第一数据信号，其中第一边缘相对于输入转换具有相对恒定的延迟，而与电压源的电压无关。第二延迟元件被配置为产生具有作为电压源的电压的函数的相对于输入转变的延迟的第二边缘的第二数据信号。选择元件使得数据输出处的输出转变对应于第一边缘和第二边缘中最新选择的一个。延迟电路可以用在脉冲发生电路中。

22. 发明授权

US07852693B2 Apparatus for and method of current leakage reduction in static random access memory arrays 失效
标题翻译：静态随机存取存储器阵列中电流泄漏减少的装置和方法
公开(公告)号：US07852693B2
公开(公告)日：2010-12-14
申请号：US11970035
申请日：2008-01-07
申请人： Todd A Christensen , Elizabeth L Gerhard , Omer Heymann , Amira Rozenfeld
发明人： Todd A Christensen , Elizabeth L Gerhard , Omer Heymann , Amira Rozenfeld
IPC分类号： G11C7/00
CPC分类号： G11C7/12 , G11C11/412 , G11C11/413
摘要： A novel and useful mechanism for reducing current leakage in a static random access memory array which significantly reduces the power requirements of the memory array. The method enables the steady state of all local and global bit lines in an SRAM array to be discharged during both active and inactive modes. The memory array includes memory cells having an N channel field effect transistor read stack. A mechanism is provided to evaluate data from memory cells where the steady state of local and global read bit lines is discharged.
摘要翻译：一种用于减少静态随机存取存储器阵列中的电流泄漏的新颖有用的机制，其显着地降低了存储器阵列的功率需求。该方法使SRAM阵列中的所有局部和全局位线的稳态在有源模式和非活动模式下都被放电。存储器阵列包括具有N沟道场效应晶体管读取堆栈的存储单元。提供一种机制来评估来自存储器单元的数据，其中局部和全局读位线的稳态被放电。

23. 发明授权

US07817481B2 Column selectable self-biasing virtual voltages for SRAM write assist 有权
标题翻译：列可选择自偏压虚拟电压用于SRAM写入辅助
公开(公告)号：US07817481B2
公开(公告)日：2010-10-19
申请号：US12167300
申请日：2008-07-03
申请人： Chad Allen Adams , George M. Braceras , Todd A. Christensen , Harold Pilo
发明人： Chad Allen Adams , George M. Braceras , Todd A. Christensen , Harold Pilo
IPC分类号： G11C7/22 , G11C11/00 , G11C5/14
CPC分类号： G11C11/417 , G11C11/41 , G11C11/419
摘要： A static random access memory decoder circuit includes a first cell supply line coupled to provide a first column of memory cells a first cell supply voltage and a second cell supply line coupled to provide a first column of memory cells a first cell supply voltage. The decoder circuit further includes a write assist circuit having a first threshold transistor coupled to the first cell supply line and a second threshold transistor coupled to the second cell supply line. In response to a write assist signal, the write assist circuit connects one of the first and second cell supply lines selected by control circuitry to an associated one of the first and second threshold transistors, such that a cell supply voltage of the selected one of the first and second cell supply lines is reduced toward the threshold voltage of the threshold transistor.
摘要翻译：静态随机存取存储器解码器电路包括第一单元电源线，其被耦合以提供第一列存储器单元第一单元电源电压和耦合以提供第一列存储器单元的第一单元电源电压的第二单元电源线。解码器电路还包括具有耦合到第一单元电源线的第一阈值晶体管和耦合到第二单元电源线的第二阈值晶体管的写辅助电路。响应于写入辅助信号，写入辅助电路将由控制电路选择的第一和第二单元电源线之一连接到第一和第二阈值晶体管中的相关联的一个，使得所选择的一个的单元电源电压第一和第二电池供应线路朝阈值晶体管的阈值电压减小。

24. 发明申请

US20090271669A1 High-Speed Testing of Integrated Devices 有权
标题翻译：集成器件的高速测试
公开(公告)号：US20090271669A1
公开(公告)日：2009-10-29
申请号：US12110955
申请日：2008-04-28
申请人： Chad A. Adams , Derick G. Behrends , Todd A. Christensen , Travis R. Hebig
发明人： Chad A. Adams , Derick G. Behrends , Todd A. Christensen , Travis R. Hebig
IPC分类号： G11C29/12 , G06F11/27
CPC分类号： G11C29/48 , G11C11/41 , G11C29/12 , G11C29/1201 , G11C29/50012 , G11C2029/0401
摘要： A method for allowing high-speed testability of a memory device having a core with memory cells for storing data, comprising: enabling a data signal having a first logical state or a second logical state from the core to reach an output port of the memory device within an evaluate cycle during a functional operating mode and pass an array built in self test during LBIST mode; enabling the data signal to change from the first logical state to the second logical state during LBIST mode at a time that coincides with the latest possible time the data signal from the core can reach the read output port within the evaluate cycle during the functional operating mode and pass the array built in self test; and executing a logic built-in self test configured to test a logic block located downstream of a transmission path of the memory device.
摘要翻译：一种用于允许具有用于存储数据的存储器单元的具有核的存储器件的高速可测试性的方法，包括：使得具有来自所述核的第一逻辑状态或第二逻辑状态的数据信号到达所述存储器件的输出端口在功能操作模式的评估周期内，并且在LBIST模式期间通过内置自检的阵列; 使得数据信号在LBIST模式期间能够在LBIST模式期间从与核心的数据信号在功能操作模式期间到达评估周期内的读取输出端口的最新可能时间一致的时刻改变为第一逻辑状态并通过自检内置的数组; 以及执行被配置为测试位于所述存储器件的传输路径下游的逻辑块的逻辑内置自检。

25. 发明申请

US20090175107A1 Apparatus for and Method of Current Leakage Reduction in Static Random Access Memory Arrays 失效
标题翻译：静态随机存取存储器阵列中电流泄漏减少的装置和方法
公开(公告)号：US20090175107A1
公开(公告)日：2009-07-09
申请号：US11970035
申请日：2008-01-07
申请人： Todd A. Christensen , Elizabeth L. Gerhard , Omer Heymann , Amira Rozenfeld
发明人： Todd A. Christensen , Elizabeth L. Gerhard , Omer Heymann , Amira Rozenfeld
IPC分类号： G11C7/00
CPC分类号： G11C7/12 , G11C11/412 , G11C11/413
摘要： A novel and useful mechanism for reducing current leakage in a static random access memory array which significantly reduces the power requirements of the memory array. The method enables the steady state of all local and global bit lines in an SRAM array to be discharged during both active and inactive modes. The memory array consists of memory cells having an N channel field effect transistor read stack. A mechanism is provided to evaluate data from memory cells where the steady state of local and global read bit lines is discharged.
摘要翻译：一种用于减少静态随机存取存储器阵列中的电流泄漏的新颖有用的机制，其显着地降低了存储器阵列的功率需求。该方法使SRAM阵列中的所有局部和全局位线的稳态在有源模式和非活动模式下都被放电。存储器阵列由具有N沟道场效应晶体管读取堆叠的存储器单元组成。提供一种机制来评估来自存储器单元的数据，其中局部和全局读位线的稳态被放电。

26. 发明申请

US20090116324A1 Apparatus for Guaranteed Write Through in Domino Read SRAM'S 失效
标题翻译：用于保证在Domino中读写SRAM的设备
公开(公告)号：US20090116324A1
公开(公告)日：2009-05-07
申请号：US11936139
申请日：2007-11-07
申请人： Todd A Christensen , Elizabeth L. Gerhard , Travis R. Hebig
发明人： Todd A Christensen , Elizabeth L. Gerhard , Travis R. Hebig
IPC分类号： G11C7/00
CPC分类号： G11C7/22 , G11C7/12 , G11C11/413
摘要： In a digital device for facilitating recovery of a precharged dot line, periodically precharged by a precharge signal, that has been prematurely discharged as a result of an early read condition, a data input signal can have a selected one of a first value and a second value. The first value is a value that would be reflected by the dot line being in a charged state. A logic device that is responsive to the data input signal causes charge to be applied to the dot line when the data signal has the first value.
摘要翻译：在数字装置中，为了便于恢复预充电点线，由于预充电信号周期性预充电，该预充电信号由于早期读取条件而被过早地放电，所以数据输入信号可以具有第一值和第二值值。第一个值是由点线处于充电状态将反映的值。当数据信号具有第一值时，响应于数据输入信号的逻辑器件使电荷被施加到点线。

27. 发明授权

US07502276B1 Method and apparatus for multi-word write in domino read SRAMs 失效
标题翻译：在多米诺骨牌SRAM中多字写入的方法和装置
公开(公告)号：US07502276B1
公开(公告)日：2009-03-10
申请号：US12122185
申请日：2008-05-16
申请人： Derick G. Behrends , Todd A. Christensen , Travis R. Hebig , Daniel M. Nelson
发明人： Derick G. Behrends , Todd A. Christensen , Travis R. Hebig , Daniel M. Nelson
IPC分类号： G11C8/12 , G11C11/413 , G11C8/10 , G11C29/18 , G11C29/26
CPC分类号： G11C8/10 , G11C11/413 , G11C29/26 , G11C2029/1202 , G11C2029/2602
摘要： A domino read SRAM capable of writing multiple wordlines simultaneously. A read/write multiplexer may allow conventional, single-wordline selection during a read operation, while allowing external logic, such as an ABIST controller, to enable multiple wordlines during a write operation.
摘要翻译：一个能够同时写入多个字线的多米诺骨牌SRAM。读/写复用器可以允许在读取操作期间的常规的单字线选择，同时允许诸如ABIST控制器的外部逻辑在写操作期间启用多个字线。

28. 发明授权

US08675427B2 Implementing RC and coupling delay correction for SRAM 有权
标题翻译：实现SRAM的RC和耦合延迟校正
公开(公告)号：US08675427B2
公开(公告)日：2014-03-18
申请号：US13414133
申请日：2012-03-07
申请人： Derick G. Behrends , Todd A. Christensen , Travis R. Hebig , Michael Launsbach , Daniel M. Nelson
发明人： Derick G. Behrends , Todd A. Christensen , Travis R. Hebig , Michael Launsbach , Daniel M. Nelson
IPC分类号： G11C7/00
CPC分类号： G11C7/12 , G11C11/419
摘要： A method and circuit for implementing delay correction in static random access memory (SRAM), and a design structure on which the subject circuit resides are provided. The SRAM circuit includes a precharge enable signal coupled between precharge near and precharge far signals and wordline near and wordline far signals of the SRAM. A precharge pull down device is coupled between the precharge far signal and ground and is controlled responsive to the precharge enable signal to decrease a time delay of the falling transition of the precharge far signal. A respective word line pull up device is coupled between a respective wordline far signal and a voltage supply rail and is controlled responsive to the precharge enable signal to increase wordline voltage level upon a rising transition of the wordline far signal.
摘要翻译：一种用于实现静态随机存取存储器（SRAM）中的延迟校正的方法和电路，以及设置有被摄体电路所在的设计结构。 SRAM电路包括预充电接近和预充电远信号以及SRAM的字线附近和字线远信号之间的预充电使能信号。预充电下拉装置耦合在预充电远信号和地之间，并且响应于预充电使能信号被控制，以减小预充电远信号的下降转换的时间延迟。相应的字线上拉器件耦合在相应的字线远信号和电压供应轨之间，并且响应于预充电使能信号被控制，以在字线远信号的上升转变时增加字线电压电平。

29. 发明授权

US08531203B2 Mask alignment, rotation and bias monitor utilizing threshold voltage dependence 失效
标题翻译：掩模对准，旋转和偏置监视器利用阈值电压依赖
公开(公告)号：US08531203B2
公开(公告)日：2013-09-10
申请号：US12813804
申请日：2010-06-11
申请人： Todd A. Christensen , Matthew J. Paschal , John E. Sheets, II
发明人： Todd A. Christensen , Matthew J. Paschal , John E. Sheets, II
IPC分类号： G01R31/26
CPC分类号： H01L22/34 , H01L21/266 , H01L29/78
摘要： The present invention provides a method and apparatus for measuring alignment, rotation and bias of mask layers in semiconductor manufacturing by examining threshold voltage variation.
摘要翻译：本发明提供一种通过检查阈值电压变化来测量半导体制造中掩模层的取向，旋转和偏置的方法和装置。

30. 发明授权

US08513815B2 Implementing integrated circuit mixed double density and high performance wire structure 失效
标题翻译：实现集成电路混合双密度和高性能导线结构
公开(公告)号：US08513815B2
公开(公告)日：2013-08-20
申请号：US13187758
申请日：2011-07-21
申请人： Anthony G. Aipperspach , Todd A. Christensen , John E. Sheets, II
发明人： Anthony G. Aipperspach , Todd A. Christensen , John E. Sheets, II
IPC分类号： H01L23/528
CPC分类号： H01L23/5283 , H01L21/76816 , H01L23/5226 , H01L2924/0002 , H01L2924/00
摘要： A method and structures are provided for implementing an integrated circuit with an enhanced wiring structure of mixed double density and high performance wires in a common plane. A wiring structure includes a first wire having a first plane and a first via to a second wire in a second plane having a second via and a third wire having the first plane with height equal to the first wire and the first via, and a third via having a height equal to the second wire and the second via.
摘要翻译：提供了一种方法和结构，用于在公共平面中实现具有混合双密度和高性能导线的增强布线结构的集成电路。布线结构包括具有第一平面的第一导线和具有第二通孔的第二平面中的第一导线和第二导线的第一导线，以及具有第一平面的第三导线，第一平面的高度等于第一导线和第一通孔，通过具有与第二线和第二通孔相等的高度。

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