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21. 发明授权

US06951825B2 Method of etching a SiN/Ir/TaN or SiN/Ir/Ti stack using an aluminum hard mask 失效
标题翻译：使用铝硬掩模蚀刻SiN / Ir / TaN或SiN / Ir / Ti叠层的方法
公开(公告)号：US06951825B2
公开(公告)日：2005-10-04
申请号：US10391294
申请日：2003-03-17
申请人： Tingkai Li , Bruce D. Ulrich , David R. Evans , Sheng Teng Hsu
发明人： Tingkai Li , Bruce D. Ulrich , David R. Evans , Sheng Teng Hsu
IPC分类号： H01L21/3065 , H01L21/02 , H01L21/311 , H01L21/3213 , H01L21/8246 , H01L21/8247 , H01L27/105 , H01L29/788 , H01L29/792 , H01L21/302
CPC分类号： H01L21/32136 , H01L21/31116 , H01L21/32139 , H01L28/65
摘要： A method of etching includes preparing a substrate; depositing a first etch stop layer; forming an iridium bottom electrode layer; depositing a SiN layer; depositing and patterning an aluminum hard mask; etching a non-patterned SiN layer with a SiN selective etchant, stopping at the level of the iridium bottom electrode layer; etching the first etch stop layer with a second selective etchant; depositing an oxide layer and CMP the oxide layer to the level of the remaining SiN layer; wet etching the SiN layer to form a trench; depositing a layer of ferroelectric material in the trench formed by removal of the SiN layer; depositing a layer of high-k oxide; and completing the device, including metallization.
摘要翻译：蚀刻方法包括准备基板; 沉积第一蚀刻停止层; 形成铱底电极层; 沉积SiN层; 沉积和图案化铝硬掩模; 用SiN选择性蚀刻剂蚀刻未图案化的SiN层，停止在铱底部电极层的水平面上; 用第二选择性蚀刻剂蚀刻第一蚀刻停止层; 将氧化物层沉积并将所述氧化物层CMP沉积到剩余SiN层的水平; 湿式蚀刻SiN层以形成沟槽; 在通过去除SiN层形成的沟槽中沉积一层铁电材料; 沉积一层高K氧化物; 并完成设备，包括金属化。

22. 发明申请

US20050054166A1 Conductive metal oxide gate ferroelectric memory transistor 失效
标题翻译：导电金属氧化物栅极铁电存储晶体管
公开(公告)号：US20050054166A1
公开(公告)日：2005-03-10
申请号：US10659547
申请日：2003-09-09
申请人： Sheng Hsu , Tingkai Li
发明人： Sheng Hsu , Tingkai Li
IPC分类号： H01L27/105 , G11C11/22 , H01L21/28 , H01L21/336 , H01L21/8246 , H01L29/78
CPC分类号： G11C11/22 , H01L21/28273 , H01L21/28291 , H01L29/66545 , H01L29/66553 , H01L29/66825 , H01L29/6684 , H01L29/78391
摘要： The present invention discloses a ferroelectric transistor having a conductive oxide in the place of the gate dielectric. The conductive oxide gate ferroelectric transistor can have a three-layer metal/ferroelectric/metal or a two-layer metal/ferroelectric on top of the conductive oxide gate. By replacing the gate dielectric with a conductive oxide, the bottom gate of the ferroelectric layer is conductive through the conductive oxide to the silicon substrate, thus minimizing the floating gate effect. The memory retention degradation related to the leakage current associated with the charges trapped within the floating gate is eliminated. The fabrication of the ferroelectric transistor by a gate etching process or a replacement gate process is also disclosed.
摘要翻译：本发明公开了一种具有导电氧化物代替栅电介质的铁电晶体管。导电氧化物栅极铁电晶体管可以在导电氧化物栅极的顶部上具有三层金属/铁电/金属或两层金属/铁电体。通过用导电氧化物代替栅极电介质，铁电层的底栅通过导电氧化物导电到硅衬底，从而最小化浮栅效应。消除了与在浮动栅极内捕获的电荷相关的泄漏电流相关的存储器保持性降低。还公开了通过栅极蚀刻工艺或替代栅极工艺制造铁电晶体管。

23. 发明授权

US06819583B2 Ferroelectric resistor non-volatile memory array 失效
标题翻译：铁电电阻非易失性存储器阵列
公开(公告)号：US06819583B2
公开(公告)日：2004-11-16
申请号：US10345726
申请日：2003-01-15
申请人： Sheng Teng Hsu , Tingkai Li , Fengyan Zhang
发明人： Sheng Teng Hsu , Tingkai Li , Fengyan Zhang
IPC分类号： G11C1122
CPC分类号： G11C11/22
摘要： A ferroelectric thin film resistor memory array is formed on a substrate and includes plural memory cells arranged in an array of rows and columns; wherein each memory cell includes: a FE resistor having a pair of terminals, and a transistor associated with each resistor, wherein each transistor has a gate, a drain and a source, and wherein the drain of each transistor is electrically connected to one terminal of its associated resistor; a word line connected to the gate of each transistor in a row; a programming line connected to each memory cell in a column; and a bit line connected to each memory cell in a column.
摘要翻译：铁基薄膜电阻存储阵列形成在基板上，并且包括以行和列为阵列排列的多个存储单元; 其中每个存储器单元包括：具有一对端子的FE电阻器和与每个电阻器相关联的晶体管，其中每个晶体管具有栅极，漏极和源极，并且其中每个晶体管的漏极电连接到其相关电阻器; 连接到每个晶体管的栅极的字线; 连接到列中的每个存储单元的编程线; 以及连接到列中每个存储单元的位线。

24. 发明授权

US06759250B2 Deposition method for lead germanate ferroelectric structure with multi-layered electrode 失效
标题翻译：具有多层电极的锗酸铅铁电结构沉积方法
公开(公告)号：US06759250B2
公开(公告)日：2004-07-06
申请号：US10196503
申请日：2002-07-15
申请人： Fengyan Zhang , Tingkai Li , Sheng Teng Hsu
发明人： Fengyan Zhang , Tingkai Li , Sheng Teng Hsu
IPC分类号： H01L2100
CPC分类号： H01L28/56 , H01L21/31604 , H01L21/31691 , H01L28/75
摘要： The ferroelectric structure including a Pt/Ir layered electrode used in conjunction with a lead germanate (Pb5Ge3O11) thin film is provided. The electrode exhibits good adhesion to the substrate, and barrier properties resistant to oxygen and lead. Ferroelectric properties are improved, without detriment to the leakage current, by using a thin IrO2 layer formed in situ, during the MOCVD lead germanate (Pb5Ge3O11) thin film process. By using a Pt/Ir electrode, a relatively low MOCVD processing temperature is required to achieve c-axis oriented lead germanate (Pb5Ge3O11) thin film. The temperature range of MOCVD c-axis oriented lead germanate (Pb5Ge3O11) thin film on top of Pt/Ir is 400-500° C. Further, a relatively large nucleation density is obtained, as compared to using single-layer iridium electrode. Therefore, the lead germanate (Pb5Ge3O11) thin film has a smooth surface, a homogeneous microstructure, and homogeneous ferroelectric properties. A method of forming the above-mentioned multi-layered electrode ferroelectric structure is also provided.
摘要翻译：提供了包括与锗酸铅（Pb5Ge3O11）薄膜结合使用的Pt / Ir层叠电极的铁电体结构。该电极对基材表现出良好的粘合性，并且对氧和铅具有阻挡性能。在MOCVD锗酸铅（Pb5Ge3O11）薄膜工艺中，通过使用在原位形成的薄的IrO 2层，铁电性能得到改善，而不损害漏电流。通过使用Pt / Ir电极，需要相对低的MOCVD处理温度来实现c轴取向的锗酸铅（Pb5Ge3O11）薄膜。 Pt / Ir顶部的MOCVD c轴取向锗酸铅（Pb5Ge3O11）薄膜的温度范围为400-500℃。与使用单层铱电极相比，获得了较大的成核密度。因此，锗酸铅（Pb5Ge3O11）薄膜表面光滑，微观组织均匀，铁电性能均匀。还提供了形成上述多层电极铁电体结构体的方法。

25. 发明授权

US06664116B2 Seed layer processes for MOCVD of ferroelectric thin films on high-k gate oxides 失效
标题翻译：在高k栅极氧化物上的铁电薄膜的MOCVD的种子层处理
公开(公告)号：US06664116B2
公开(公告)日：2003-12-16
申请号：US10020868
申请日：2001-12-12
申请人： Tingkai Li , Sheng Teng Hsu
发明人： Tingkai Li , Sheng Teng Hsu
IPC分类号： H01L2100
CPC分类号： H01L21/28273 , C23C16/0272 , C23C16/40 , C23C16/56 , H01L21/28194 , H01L21/28291 , H01L21/31691 , H01L28/56 , H01L29/513 , H01L29/517
摘要： A method of forming a ferroelectric thin film on a high-k layer includes preparing a silicon substrate; forming a high-k layer on the substrate; depositing a seed layer of ferroelectric material at a relatively high temperature on the high-k layer; depositing a top layer of ferroelectric material on the seed layer at a relatively low temperature; and annealing the substrate, the high-k layer and the ferroelectric layers to form a ferroelectric thin film.
摘要翻译：在高k层上形成铁电薄膜的方法包括：制备硅衬底; 在基板上形成高k层; 在高k层上沉积相对较高温度的铁电材料种子层; 在相对低的温度下在种子层上沉积铁电材料的顶层; 并且对衬底，高k层和铁电层进行退火以形成铁电薄膜。

26. 发明授权

US06566148B2 Method of making a ferroelectric memory transistor 有权
标题翻译：制造铁电存储晶体管的方法
公开(公告)号：US06566148B2
公开(公告)日：2003-05-20
申请号：US09929710
申请日：2001-08-13
申请人： Sheng Teng Hsu , Tingkai Li , Bruce D. Ulrich
发明人： Sheng Teng Hsu , Tingkai Li , Bruce D. Ulrich
IPC分类号： H01L2100
CPC分类号： H01L27/11502 , H01L21/28291 , H01L27/11585 , H01L27/1159 , H01L29/6684
摘要： A method of making a ferroelectric memory transistor includes preparing a silicon substrate including forming plural active areas thereon; depositing a layer of gate insulator on the substrate, and depositing a layer of polysilicon over the gate insulator layer; forming a source region, a drain region and a gate electrode; depositing a layer of bottom electrode material and finishing the bottom electrode without damaging the underlying gate insulator and silicon substrate; depositing a layer of ferroelectric material on the bottom electrode; depositing a layer of top electrode material on the ferroelectric material; and finishing the transistor, including passivation oxide deposition, contact hole etching and metalization.
摘要翻译：制造铁电存储晶体管的方法包括制备包括在其上形成多个有源区的硅衬底; 在所述衬底上沉积栅极绝缘体层，以及在所述栅极绝缘体层上沉积多晶硅层; 形成源极区域，漏极区域和栅极电极; 沉积一层底部电极材料并整理底部电极，而不损坏下面的栅极绝缘体和硅衬底; 在底部电极上沉积一层铁电材料; 在铁电材料上沉积顶层电极材料层; 并整理晶体管，包括钝化氧化物沉积，接触孔蚀刻和金属化。

27. 发明授权

US06531324B2 MFOS memory transistor & method of fabricating same 失效
公开(公告)号：US06531324B2
公开(公告)日：2003-03-11
申请号：US09820039
申请日：2001-03-28
申请人： Sheng Teng Hsu , Fengyan Zhang , Tingkai Li
发明人： Sheng Teng Hsu , Fengyan Zhang , Tingkai Li
IPC分类号： H01L2100
CPC分类号： H01L29/516 , H01L21/28291 , H01L29/78391
摘要： A ferroelectric transistor gate structure with a ferroelectric gate and passivation sidewalls is provided. The passivation sidewalls serve as an insulator to reduce, or eliminate, the diffusion of oxygen or hydrogen into the ferroelectric gate. A method of forming the ferroelectric gate structure is also provided. The method comprises the steps of forming a sacrificial gate structure, removing the sacrificial gate structure, depositing passivation insulator material, etching the passivation insulator material using anisotropic plasma etching to form passivation sidewalls, depositing a ferroelectric material, polishing the ferroelectric material using CMP, and forming a top electrode overlying the ferroelectric material.

28. 发明授权

US06495378B2 Ferroelastic lead germanate thin film and deposition method 有权
标题翻译：铁硬脂酸铅薄膜和沉积方法
公开(公告)号：US06495378B2
公开(公告)日：2002-12-17
申请号：US09814273
申请日：2001-03-21
申请人： Tingkai Li , Fengyan Zhang , Yoshi Ono , Sheng Teng Hsu
发明人： Tingkai Li , Fengyan Zhang , Yoshi Ono , Sheng Teng Hsu
IPC分类号： H01L2100
CPC分类号： H01L21/02197 , C23C16/40 , H01L21/02271 , H01L21/31604 , H01L21/31691
摘要： A Pb3GeO5 phase PGO thin film is provided. This film has ferroelastic properties that make it ideal for many microelectromechanical applications or as decoupling capacitors in high speed multichip modules. This PGO film is uniquely formed in a MOCVD process that permits a thin film, less than 1 mm, of material to be deposited. The process mixes Pd and germanium in a solvent. The solution is heated to form a precursor vapor which is decomposed. The method provides deposition temperatures and pressures. The as-deposited film is also annealed to enhanced the film's ferroelastic characteristics. A ferroelastic capacitor made from the present invention PGO film is also provided.
摘要翻译：提供Pb3GeO5相PGO薄膜。该薄膜具有铁弹性，使其成为许多微机电应用或高速多芯片模块中的去耦电容器的理想选择。该PGO膜在MOCVD工艺中唯一形成，其允许沉积小于1mm的薄膜。该方法将Pd和锗在溶剂中混合。将溶液加热以形成分解的前体蒸汽。该方法提供沉积温度和压力。沉积的膜也被退火以增强膜的铁弹性特征。还提供了由本发明PGO膜制成的铁弹性电容器。

29. 发明授权

US06190925B1 Epitaxially grown lead germanate film and deposition method 有权
标题翻译：外延生长的锗酸铅膜和沉积法
公开(公告)号：US06190925B1
公开(公告)日：2001-02-20
申请号：US09302272
申请日：1999-04-28
申请人： Tingkai Li , Fengyan Zhang , Yoshi Ono , Sheng Teng Hsu
发明人： Tingkai Li , Fengyan Zhang , Yoshi Ono , Sheng Teng Hsu
IPC分类号： H01L2100
CPC分类号： H01L21/31604 , C23C16/40 , H01L21/31691 , Y10S438/933
摘要： The present invention provides a substantially single crystal PGO film with optimal the ferroelectric properties. The PGO film and adjacent electrodes are epitaxially grown to minimize mismatch between the structures. MOCVD deposition methods and RTP annealing procedures permit a PGO film to be epitaxially grown in commercial fabrication processes. These epitaxial ferroelectric have application in FeRAM memory devices. The present invention deposition method epitaxially grows ferroelectric Pb5Ge3O11 thin films along with c-axis orientation.
摘要翻译：本发明提供了具有最佳铁电性能的基本单晶PGO膜。 PGO膜和相邻电极被外延生长以最小化结构之间的失配。 MOCVD沉积方法和RTP退火程序允许PGO膜在商业制造工艺中外延生长。这些外延铁电体已经应用于FeRAM存储器件中。本发明沉积方法外延生长铁电Pb5Ge3O11薄膜以及c轴取向。

30. 发明授权

US08951842B2 Semiconductor growth substrates and associated systems and methods for die singulation 有权
标题翻译：半导体生长衬底及相关系统和模具分离方法
公开(公告)号：US08951842B2
公开(公告)日：2015-02-10
申请号：US13349432
申请日：2012-01-12
申请人： Xiaolong Fang , Lifang Xu , Tingkai Li , Thomas Gehrke
发明人： Xiaolong Fang , Lifang Xu , Tingkai Li , Thomas Gehrke
IPC分类号： H01L33/50 , H01L33/48 , H01L21/66 , H01L23/544 , H01L33/00 , H01L21/78
CPC分类号： H01L33/32 , H01L21/78 , H01L22/10 , H01L22/32 , H01L22/34 , H01L23/544 , H01L33/0066 , H01L33/007 , H01L33/0095 , H01L33/48 , H01L2924/0002 , H01L2924/00
摘要： Semiconductor growth substrates and associated systems and methods for die singulation are disclosed. A representative method for manufacturing semiconductor devices includes forming spaced-apart structures at a dicing street located between neighboring device growth regions of a substrate material. The method can further include epitaxially growing a semiconductor material by adding a first portion of semiconductor material to the device growth regions and adding a second portion of semiconductor material to the structures. The method can still further include forming semiconductor devices at the device growth regions, and separating the semiconductor devices from each other at the dicing street by removing the spaced-apart structures and the underlying substrate material at the dicing street.
摘要翻译：公开了半导体生长衬底和用于芯片分离的相关系统和方法。用于制造半导体器件的代表性方法包括在位于衬底材料的相邻器件生长区域之间的切割街道上形成间隔开的结构。该方法还可以包括通过将半导体材料的第一部分添加到器件生长区域并将半导体材料的第二部分添加到该结构体来外延生长半导体材料。该方法还可以进一步包括在器件生长区域处形成半导体器件，并且在切割街道处通过在切割街道处去除间隔开的结构和下面的衬底材料来将半导体器件彼此分离。

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