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    • 27. 发明申请
    • DELAY-LOCKED LOOP CIRCUIT AND METHOD OF GENERATING MULTIPLIED CLOCK THEREFROM
    • 延迟环路电路及其生成多个时钟的方法
    • US20080116950A1
    • 2008-05-22
    • US11877187
    • 2007-10-23
    • Seung-Hwan BaekSeung-Won Lee
    • Seung-Hwan BaekSeung-Won Lee
    • H03L7/06
    • H03L7/0812H03L7/0891H03L7/113H03L7/16
    • A delay-locked loop circuit includes: a phase detector generating a detection signal from a phase difference between an external clock signal and a feedback clock signal; a charge pump controlling a level of a voltage signal in response to the detection signal; and a voltage-controlled delay line generating a plurality of delay clock signals by delaying the external clock signal in response to the voltage signal and generating a multiplied clock signal using the delay clock signals in different numbers in accordance with a frequency domain of the external clock signal. The multiplied clock signal is generated by multiplying the external clock signal an integer number of times and the feedback clock signal is delayed from the plurality of delay clock signals by a cycle period of the external clock signal.
    • 延迟锁定环路电路包括:相位检测器,从外部时钟信号和反馈时钟信号之间的相位差产生检测信号; 电荷泵,响应于检测信号控制电压信号的电平; 以及电压控制延迟线,通过响应于电压信号延迟外部时钟信号并且根据外部时钟的频域使用不同数量的延迟时钟信号产生倍增时钟信号来产生多个延迟时钟信号 信号。 乘法时钟信号通过将外部时钟信号乘以整数倍而产生,反馈时钟信号从多个延迟时钟信号延迟外部时钟信号的周期。
    • 29. 发明申请
    • Proportional to absolute temperature current generation circuit having higher temperature coefficient, display device including the same, and method thereof
    • 与具有较高温度系数的绝对温度电流产生电路的比例,包括其的显示装置及其方法
    • US20080284493A1
    • 2008-11-20
    • US12149808
    • 2008-05-08
    • Seung Hwan BaekChang Hwe ChoiHyung Tae Kim
    • Seung Hwan BaekChang Hwe ChoiHyung Tae Kim
    • H03K3/42
    • G05F3/30
    • A proportional to absolute temperature (PTAT) current generation circuit may include a current mirror unit and/or a level control unit. The current mirror unit may be connected between a first power supply voltage, a first node, and/or a second node. The level control unit may be connected between the first node, the second node, and/or a second power supply voltage. The level control unit may be configured to control a level of an output current of the current mirror unit based on a voltage level of the first node and a voltage level of the second node. The level control unit may include a first transistor connected between the first node and the second power supply voltage, at least one second transistor connected between the second node and a third node, the at least one second transistor configured to operate in a weak inversion region, and/or a third transistor connected between the third node and the second power supply voltage.
    • 与绝对温度(PTAT)电流产生电路成正比可以包括电流镜单元和/或电平控制单元。 电流镜单元可以连接在第一电源电压,第一节点和/或第二节点之间。 电平控制单元可以连接在第一节点,第二节点和/或第二电源电压之间。 电平控制单元可以被配置为基于第一节点的电压电平和第二节点的电压电平来控制电流镜单元的输出电流的电平。 电平控制单元可以包括连接在第一节点和第二电源电压之间的第一晶体管,连接在第二节点和第三节点之间的至少一个第二晶体管,所述至少一个第二晶体管被配置为在弱反转区域 ,和/或连接在第三节点和第二电源电压之间的第三晶体管。