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21. 发明授权

US08896072B2 Channel surface technique for fabrication of FinFET devices 有权
标题翻译：用于制造FinFET器件的通道表面技术
公开(公告)号：US08896072B2
公开(公告)日：2014-11-25
申请号：US13736546
申请日：2013-01-08
申请人： Chung Foong Tan , Eng Huat Toh , Jae Gon Lee , Sanford Chu
发明人： Chung Foong Tan , Eng Huat Toh , Jae Gon Lee , Sanford Chu
IPC分类号： H01L29/78 , H01L29/66
CPC分类号： H01L29/7853 , H01L29/66795
摘要： A FinFET (p-channel) device is formed having a fin structure with sloped or angled sidewalls (e.g., a pyramidal or trapezoidal shaped cross-section shape). When using conventional semiconductor substrates having a (100) surface orientation, the fin structure is formed in a way (groove etching) which results in sloped or angled sidewalls having a (111) surface orientation. This characteristic substantially increases hole mobility as compared to conventional fin structures having vertical sidewalls.
摘要翻译： FinFET（p沟道）器件形成为具有倾斜或成角度的侧壁（例如，金字塔形或梯形形状的横截面形状）的翅片结构。当使用具有（100）表面取向的常规半导体衬底时，翅片结构以一种（凹槽蚀刻）形成，其导致具有（111）表面取向的倾斜或倾斜的侧壁。与具有垂直侧壁的常规翅片结构相比，该特性显着增加了空穴迁移率。

22. 发明授权

US08383475B2 EEPROM cell 有权
标题翻译： EEPROM单元
公开(公告)号：US08383475B2
公开(公告)日：2013-02-26
申请号：US12888431
申请日：2010-09-23
申请人： Sung Mun Jung , Kian Hong Lim , Jianbo Yang , Swee Tuck Woo , Sanford Chu
发明人： Sung Mun Jung , Kian Hong Lim , Jianbo Yang , Swee Tuck Woo , Sanford Chu
IPC分类号： H01L21/8238
CPC分类号： H01L21/28273 , H01L27/11521 , H01L27/11524 , H01L29/66825 , H01L29/7881
摘要： A method of forming a device is disclosed. The method includes providing a substrate prepared with a cell area separated by other active areas by isolation regions. First and second gates of first and second transistors in the cell area are formed. The first gate includes first and second sub-gates separated by a first intergate dielectric layer. The second gate includes a second sub-gate surrounding a first sub-gate. The first and second sub-gates of the second gate are separated by a second intergate dielectric layer. First and second junctions of the first and second transistors are formed. The method also includes forming a first gate terminal coupled to the second sub-gate of the first transistor and a second gate terminal coupled to at least the first sub-gate of the second transistor.
摘要翻译：公开了一种形成装置的方法。该方法包括提供制备有由其它活性区域隔离的细胞区域的基底。在单元区域中形成第一和第二晶体管的第一和第二栅极。第一栅极包括由第一隔间栅极介电层隔开的第一和第二子栅极。第二栅极包括围绕第一子栅极的第二子栅极。第二栅极的第一和第二子栅极由第二栅极间介电层分开。形成第一和第二晶体管的第一和第二结。该方法还包括形成耦合到第一晶体管的第二子栅极的第一栅极端子和耦合到第二晶体管的至少第一子栅极的第二栅极端子。

23. 发明授权

US08349692B2 Channel surface technique for fabrication of FinFET devices 有权
标题翻译：用于制造FinFET器件的通道表面技术
公开(公告)号：US08349692B2
公开(公告)日：2013-01-08
申请号：US13043323
申请日：2011-03-08
申请人： Chung Foong Tan , Eng Huat Toh , Jae Gon Lee , Sanford Chu
发明人： Chung Foong Tan , Eng Huat Toh , Jae Gon Lee , Sanford Chu
IPC分类号： H01L21/336
CPC分类号： H01L29/7853 , H01L29/66795
摘要： A FinFET (p-channel) device is formed having a fin structure with sloped or angled sidewalls (e.g., a pyramidal or trapezoidal shaped cross-section shape). When using conventional semiconductor substrates having a (100) surface orientation, the fin structure is formed in a way (groove etching) which results in sloped or angled sidewalls having a (111) surface orientation. This characteristic substantially increases hole mobility as compared to conventional fin structures having vertical sidewalls.
摘要翻译： FinFET（p沟道）器件形成为具有倾斜或成角度的侧壁（例如，金字塔形或梯形形状的横截面形状）的翅片结构。当使用具有（100）表面取向的常规半导体衬底时，翅片结构以一种（凹槽蚀刻）形成，其导致具有（111）表面取向的倾斜或倾斜的侧壁。与具有垂直侧壁的常规翅片结构相比，该特性显着增加了空穴迁移率。

24. 发明申请

US20120228676A1 CHANNEL SURFACE TECHNIQUE FOR FABRICATION OF FinFET DEVICES 有权
标题翻译：用于制造FinFET器件的通道表面技术
公开(公告)号：US20120228676A1
公开(公告)日：2012-09-13
申请号：US13043323
申请日：2011-03-08
申请人： Chung Foong Tan , Eng Huat Toh , Jae Gon Lee , Sanford Chu
发明人： Chung Foong Tan , Eng Huat Toh , Jae Gon Lee , Sanford Chu
IPC分类号： H01L29/772 , H01L21/336
CPC分类号： H01L29/7853 , H01L29/66795
摘要： A FinFET (p-channel) device is formed having a fin structure with sloped or angled sidewalls (e.g., a pyramidal or trapezoidal shaped cross-section shape). When using conventional semiconductor substrates having a (100) surface orientation, the fin structure is formed in a way (groove etching) which results in sloped or angled sidewalls having a (111) surface orientation. This characteristic substantially increases hole mobility as compared to conventional fin structures having vertical sidewalls.
摘要翻译： FinFET（p沟道）器件形成为具有倾斜或成角度的侧壁（例如，金字塔形或梯形形状的横截面形状）的翅片结构。当使用具有（100）表面取向的常规半导体衬底时，翅片结构以一种（凹槽蚀刻）形成，其导致具有（111）表面取向的倾斜或成角度的侧壁。与具有垂直侧壁的常规翅片结构相比，该特性显着增加了空穴迁移率。

25. 发明授权

US07951680B2 Integrated circuit system employing an elevated drain 有权
标题翻译：集成电路系统采用升高的漏极
公开(公告)号：US07951680B2
公开(公告)日：2011-05-31
申请号：US12262120
申请日：2008-10-30
申请人： Guowei Zhang , Yisuo Li , Ming Li , Purakh Raj Verma , Shao-fu Sanford Chu
发明人： Guowei Zhang , Yisuo Li , Ming Li , Purakh Raj Verma , Shao-fu Sanford Chu
IPC分类号： H01L21/336
CPC分类号： H01L29/0847 , H01L29/66659 , H01L29/7834
摘要： A method for manufacturing an integrated circuit system that includes: providing a substrate including an active device; forming a drift region in the substrate, the drift region bounded in part by a top surface of the substrate and spaced apart from a source; and forming a drain above the drift region.
摘要翻译：一种用于制造集成电路系统的方法，包括：提供包括有源器件的衬底; 在所述衬底中形成漂移区域，所述漂移区域部分地由所述衬底的顶表面限定并与源极隔开; 并在漂移区上方形成漏极。

26. 发明授权

US07846805B2 Self-aligned vertical PNP transistor for high performance SiGe CBiCMOS process 有权
标题翻译：用于高性能SiGe CBiCMOS工艺的自对准垂直PNP晶体管
公开(公告)号：US07846805B2
公开(公告)日：2010-12-07
申请号：US12368283
申请日：2009-02-09
申请人： Shaoqiang Zhang , Purakh Raj Verma , Sanford Chu
发明人： Shaoqiang Zhang , Purakh Raj Verma , Sanford Chu
IPC分类号： H01L21/331
CPC分类号： H01L21/82285 , H01L21/8249 , H01L27/0623 , H01L27/0826 , H01L29/7378
摘要： A structure and a process for a self-aligned vertical PNP transistor for high performance SiGe CBiCMOS process. Embodiments include SiGe CBiCMOS with high-performance SiGe NPN transistors and PNP transistors. As the PNP transistors and NPN transistors contained different types of impurity profile, they need separate lithography and doping step for each transistor. The process is easy to integrate with existing CMOS process to save manufacturing time and cost. As plug-in module, fully integration with SiGe BiCMOS processes. High doping Polysilicon Emitter can increase hole injection efficiency from emitter to base, reduce emitter resistor, and form very shallow EB junction. Self-aligned N+ base implant can reduce base resistor and parasitical EB capacitor. Very low collector resistor benefits from BP layer. PNP transistor can be Isolated from other CMOS and NPN devices by BNwell, Nwell and BN+ junction.
摘要翻译：用于高性能SiGe CBiCMOS工艺的自对准垂直PNP晶体管的结构和工艺。实施例包括具有高性能SiGe NPN晶体管和PNP晶体管的SiGe CBiCMOS。由于PNP晶体管和NPN晶体管包含不同类型的杂质分布，因此每个晶体管需要单独的光刻和掺杂步骤。该过程易于与现有的CMOS工艺集成，以节省制造时间和成本。作为插件模块，与SiGe BiCMOS工艺完全集成。高掺杂多晶硅发射器可以增加从发射极到基极的空穴注入效率，减少发射极电阻，并形成非常浅的EB结。自对准N +基极植入可以减少基极电阻和寄生EB电容。极低的集电极电阻受益于BP层。 PNP晶体管可以通过BNwell，Nwell和BN +结与其他CMOS和NPN器件隔离。

27. 发明申请

US20090315152A1 DIFFUSION BARRIER AND METHOD OF FORMATION THEREOF 有权
标题翻译：扩散障碍及其形成方法
公开(公告)号：US20090315152A1
公开(公告)日：2009-12-24
申请号：US12144652
申请日：2008-06-24
申请人： Shyue Seng TAN , Lee Wee TEO , Yung Fu CHONG , Elgin QUEK , Sanford CHU
发明人： Shyue Seng TAN , Lee Wee TEO , Yung Fu CHONG , Elgin QUEK , Sanford CHU
IPC分类号： H01L29/32 , H01L21/76
CPC分类号： H01L29/66537 , H01L21/26506 , H01L21/266 , H01L21/3223 , H01L21/76224 , H01L21/823807 , H01L21/823814 , H01L21/823842 , H01L21/823871 , H01L21/823878 , H01L23/532 , H01L27/088 , H01L29/0649 , H01L29/1083 , H01L29/32 , H01L29/36 , H01L29/66477 , H01L29/7833 , H01L2924/0002 , H01L2924/00
摘要： A method of forming a device is presented. The method includes providing a structure having first and second regions. A diffusion barrier is formed between at least a portion of the first and second regions. The diffusion barrier comprises cavities that reduce diffusion of elements between the first and second regions.
摘要翻译：提出了一种形成装置的方法。该方法包括提供具有第一和第二区域的结构。在第一和第二区域的至少一部分之间形成扩散阻挡层。扩散屏障包括减少元件在第一和第二区域之间的扩散的空腔。

28. 发明申请

US20090294904A1 INTEGRATED CIRCUIT SYSTEM EMPLOYING BACK END OF LINE VIA TECHNIQUES 有权
标题翻译：集成电路系统采用线路技术的后端
公开(公告)号：US20090294904A1
公开(公告)日：2009-12-03
申请号：US12132342
申请日：2008-06-03
申请人： Shaoqing Zhang , Fan Zhang , Shao-fu Sanford Chu , Bei Chao Zhang
发明人： Shaoqing Zhang , Fan Zhang , Shao-fu Sanford Chu , Bei Chao Zhang
IPC分类号： H01L21/283 , H01L21/02 , H01L29/92
CPC分类号： H01L27/0207 , H01L21/76816 , H01L23/5223 , H01L23/5226 , H01L28/60 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit system that includes: providing a substrate including front-end-of-line circuitry; forming a first metallization layer over the substrate and electrically connected to the substrate; forming a viabar or a via group over the first metallization layer; and forming a second metallization layer over the first metallization layer and electrically connected to the first metallization layer through either the viabar or the via group.
摘要翻译：一种集成电路系统，包括：提供包括前端电路的基板; 在所述衬底上形成第一金属化层并电连接到所述衬底; 在所述第一金属化层上形成viabar或通孔基团; 以及在所述第一金属化层上形成第二金属化层，并且通过所述viabar或通孔基团电连接到所述第一金属化层。

29. 发明授权

US07323736B2 Method to form both high and low-k materials over the same dielectric region, and their application in mixed mode circuits 有权
标题翻译：在同一电介质区域上形成高k和低k材料的方法及其在混合模式电路中的应用
公开(公告)号：US07323736B2
公开(公告)日：2008-01-29
申请号：US11438188
申请日：2006-05-22
申请人： Pradeep Yelehanka , Sanford Chu , Chit Hwei Ng , Jia Zhen , Purakh Verma
发明人： Pradeep Yelehanka , Sanford Chu , Chit Hwei Ng , Jia Zhen , Purakh Verma
IPC分类号： H01L27/108
CPC分类号： H01L28/55 , H01L21/02109 , H01L21/3127 , H01L21/3144 , H01L21/31625 , H01L21/31629 , H01L27/0617 , H01L27/0629 , H01L27/1203 , H01L2924/0002 , Y10T428/12035 , H01L2924/00
摘要： A new method of provided for forming in one plane layers of semiconductor material having both high and low dielectric constants. Layers, having selected and preferably non-identical parameters of dielectric constants, are successively deposited interspersed with layers of etch stop material. The layers can be etched, creating openings there-through that can be filled with a layer of choice.
摘要翻译：一种提供用于在具有高和低介电常数的半导体材料的一个平面层中形成的新方法。具有选择且优选不相同的介电常数参数的层被依次沉积，散布有蚀刻停止材料层。这些层可以被蚀刻，在那里形成开口，通过这些层可以填充一层选择。

30. 发明授权

US07268412B2 Double polysilicon bipolar transistor 有权
标题翻译：双晶硅双极晶体管
公开(公告)号：US07268412B2
公开(公告)日：2007-09-11
申请号：US11057259
申请日：2005-02-12
申请人： Purakh Raj Verma , Shao-fu Sanford Chu
发明人： Purakh Raj Verma , Shao-fu Sanford Chu
IPC分类号： H01L27/082 , H01L27/102 , H01L29/70 , H01L31/11
CPC分类号： H01L29/66287 , H01L29/0804 , H01L29/0821 , H01L29/732 , H01L29/7375
摘要： A bipolar transistor with a substrate having a collector region and a base structure provided thereon. An emitter structure is formed over the base structure and an extrinsic base structure is formed over the base structure and over the collector region beside and spaced from the emitter structure. A dielectric layer is deposited over the substrate and connections are formed to the extrinsic base structure, the emitter structure and the collector region.
摘要翻译：一种双极晶体管，其具有设置在其上的集电极区域和基极结构的衬底。在基底结构上形成发射极结构，并且在基极结构之上形成外部基极结构，并且在发射极结构旁边和间隔开的集电极区上方形成发射极结构。电介质层沉积在衬底上，并且连接被形成为非本征基极结构，发射极结构和集电极区。

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