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21. 发明申请

US20060044885A1 System and method for preserving an error margin for a non-volatile memory 有权
标题翻译：用于保存非易失性存储器的错误余量的系统和方法
公开(公告)号：US20060044885A1
公开(公告)日：2006-03-02
申请号：US11124939
申请日：2005-05-09
申请人： Massimiliano Frulio , Fabio Tassan Caser , Lorenzo Bedarida , Mirella Marsella
发明人： Massimiliano Frulio , Fabio Tassan Caser , Lorenzo Bedarida , Mirella Marsella
IPC分类号： G11C5/14
CPC分类号： G11C29/50 , G11C7/062 , G11C7/067 , G11C7/14 , G11C16/04 , G11C16/28 , G11C29/026 , G11C29/028 , G11C2207/063 , G11C2211/5645
摘要： A system and method for preserving an error margin for a non-volatile memory that includes a memory cell, a reference cell coupled to a reference current mirror configured to mirror current through the reference cell. The system comprises a memory current mirror coupled to the memory cell and configured to mirror current through the memory cell. A sense amplifier has a first and a second input. The first input is coupled to the reference current mirror and the second input is coupled to the memory current mirror. The sense amplifier is configured to compare a voltage across the memory cell with a voltage across the reference cell.
摘要翻译：一种用于保持非易失性存储器的误差容限的系统和方法，所述非易失性存储器包括存储器单元，耦合到被配置为镜像通过所述参考单元的电流的参考电流镜的参考单元。该系统包括耦合到存储器单元并被配置为镜像通过存储器单元的电流的存储器电流镜。读出放大器具有第一和第二输入。第一输入耦合到参考电流镜，第二输入耦合到存储器电流镜。读出放大器被配置为将存储器单元两端的电压与参考单元两端的电压进行比较。

22. 发明授权

US06906576B2 High precision digital-to-analog converter with optimized power consumption 有权
标题翻译：具有优化功耗的高精度数模转换器
公开(公告)号：US06906576B2
公开(公告)日：2005-06-14
申请号：US10753273
申请日：2004-01-07
申请人： Stefano Sivero , Lorenzo Bedarida , Massimiliano Frulio
发明人： Stefano Sivero , Lorenzo Bedarida , Massimiliano Frulio
IPC分类号： G05F1/10 , G05F3/02 , H02M20060101 , H02M3/07 , H02M5/42 , H03M1/76
CPC分类号： H02M3/07 , H03M1/765
摘要： A regulated charge pump circuit having two-way switching means that switches between a first feedback pathway that provides a precise and stable voltage output and a second feedback pathway that provides a regulated voltage output with low current consumption from the power source. The first feedback pathway maintains a precise voltage output by regulating a pass device that draws current to the voltage output. The second feedback pathway regulates the voltage output by controlling the connection of a clock input to the charge pump. A variable resistor is used to set the regulated level of the voltage output. A digital-to analog converter is formed by using a combination logic circuit to convert a digital input signal to a control signal for the variable resistor.
摘要翻译：一种具有双向切换装置的调节电荷泵电路，其在提供精确和稳定的电压输出的第一反馈通路与从电源提供具有低电流消耗的调节电压输出的第二反馈通路之间切换。第一反馈通道通过调节将电流吸引到电压输出的通过装置来保持精确的电压输出。第二反馈通道通过控制时钟输入到电荷泵的连接来调节电压输出。可变电阻用于设置电压输出的稳定电平。通过使用组合逻辑电路将数字输入信号转换成可变电阻器的控制信号，形成数模转换器。

23. 发明申请

US20090109754A1 NON-VOLATILE MEMORY ARRAY ARCHITECTURE WITH JOINED WORD LINES 有权
标题翻译：具有连接字线的非易失性存储器阵列架构
公开(公告)号：US20090109754A1
公开(公告)日：2009-04-30
申请号：US11928086
申请日：2007-10-30
申请人： Steve Schumann , Massimiliano Frulio , Simone Bartoli , Lorenzo Bedarida , Edward Shue Ching Hui
发明人： Steve Schumann , Massimiliano Frulio , Simone Bartoli , Lorenzo Bedarida , Edward Shue Ching Hui
IPC分类号： G11C16/04 , H01S4/00
CPC分类号： G11C16/3418 , Y10T29/49002
摘要： In an embodiment, a non-volatile memory array wherein narrow word lines, as small as the minimum feature size width F, in separate strings, are extended outwardly from a non-volatile memory array and joined by wider connector segments. The joined word lines provide new opportunities. First, metal straps that can be formed to overlie the word lines can be joined by metal connector segments to the word lines. The connector segments can serve as an interface between the polysilicon word lines and the metal straps. Two adjacent word lines in the same string share a single metal strap using these segments thereby reducing the overall number of segments and contacts in the array. Increased width of the polysilicon joinder segments joining word lines in different strings, provides the opportunity for widening the connection beyond the minimum feature size so that contact may be readily made between the metal straps and the polysilicon word lines. Second, the joined word lines require fewer row decoder circuits. One row decoder is provided for each joined set of word lines.
摘要翻译：在一个实施例中，非易失性存储器阵列，其中与分离的串中的最小特征尺寸宽度F一样小的窄字线从非易失性存储器阵列向外延伸并由更宽的连接器段连接。加入的词语提供了新的机会。首先，可以形成为覆盖字线的金属带可以通过金属连接器部分连接到字线。连接器部分可以用作多晶硅字线和金属带之间的接口。相同字符串中的两个相邻字线使用这些段共享单个金属带，从而减少阵列中的段和触点的总数。在不同的串中连接字线的多晶硅接合段的增加的宽度提供了将连接扩大超出最小特征尺寸的机会，使得可以容易地在金属带和多晶硅字线之间进行接触。第二，连接的字线需要更少的行解码器电路。为每个连接的字线组提供一行解码器。

24. 发明授权

US07522002B2 Biasing current to speed up current mirror settling time 有权
标题翻译：偏置电流以加快电流反射镜稳定时间
公开(公告)号：US07522002B2
公开(公告)日：2009-04-21
申请号：US11619729
申请日：2007-01-04
申请人： Gabriele Pelli , Lorenzo Bedarida , Massimiliano Frulio , Andrea Bettini
发明人： Gabriele Pelli , Lorenzo Bedarida , Massimiliano Frulio , Andrea Bettini
IPC分类号： H03F3/04
CPC分类号： H03F3/343 , G09G3/20 , G09G3/3216 , G09G3/3225
摘要： A current mirror circuit includes a first current-mirror transistor coupled to a second current-mirror transistor. A load is coupled to the second current-mirror transistor. A first current source is coupled to the first current-mirror transistor to cause a bias current to flow through the first current-mirror transistor and a second current source is coupled to the second current-mirror transistor and in parallel with the load to shunt the bias current away from the load.
摘要翻译：电流镜电路包括耦合到第二电流镜晶体管的第一电流镜晶体管。负载耦合到第二电流镜晶体管。第一电流源耦合到第一电流镜晶体管以引起偏置电流流过第一电流镜晶体管，并且第二电流源耦合到第二电流镜晶体管并且与负载并联以分流偏置电流远离负载。

25. 发明申请

US20080232169A1 NAND-LIKE MEMORY ARRAY EMPLOYING HIGH-DENSITY NOR-LIKE MEMORY DEVICES 审中-公开
标题翻译： NAND型存储器阵列采用高密度NOR形存储器件
公开(公告)号：US20080232169A1
公开(公告)日：2008-09-25
申请号：US11688740
申请日：2007-03-20
申请人： Massimiliano Frulio , Lorenzo Bedarida , Simone Bartoli , Fabio Tassan Caser
发明人： Massimiliano Frulio , Lorenzo Bedarida , Simone Bartoli , Fabio Tassan Caser
IPC分类号： G11C11/34
CPC分类号： G11C16/08 , G11C5/025 , G11C5/063
摘要： A flash memory integrated circuit includes a plurality of flash memory arrays. A global word line driver is associated with each array, each global word line driver coupled to a plurality of select lines. A plurality of sense amplifiers are individually coupled to a plurality of bit lines. A plurality of sub arrays in each array each include a plurality of NAND flash memory cells coupled to local word lines and local bit lines. A local word line driver is associated with each sub-array and coupled to the plurality of select lines and configured to drive ones of the local word lines in its sub array associated with selected ones of the plurality of NAND flash memory cells in its sub-array. A local bit line driver is coupled between selected ones of the local bit lines in each sub array and selected ones of the plurality of bit lines.
摘要翻译：闪存集成电路包括多个闪存阵列。全局字线驱动器与每个阵列相关联，每个全局字线驱动器耦合到多个选择线。多个读出放大器分别耦合到多个位线。每个阵列中的多个子阵列每个包括耦合到本地字线和局部位线的多个NAND快闪存储器单元。本地字线驱动器与每个子阵列相关联并且耦合到多个选择线，并且被配置为驱动其子阵列中的与本发明的子阵列中的多个NAND快闪存储器单元中的选定的一个相关联的本地字线中的一个，数组。局部位线驱动器耦合在每个子阵列中的局部位线中的选定的位线和多个位线中的选定的位线之间。

26. 发明授权

US07379338B2 Method and system for regulating a program voltage value during multilevel memory device programming 有权
标题翻译：用于在多级存储器件编程期间调节编程电压值的方法和系统
公开(公告)号：US07379338B2
公开(公告)日：2008-05-27
申请号：US11635160
申请日：2006-12-07
申请人： Massimiliano Frulio , Simone Bartoli , Davide Manfre′ , Andrea Sacco
发明人： Massimiliano Frulio , Simone Bartoli , Davide Manfre′ , Andrea Sacco
IPC分类号： G11C11/34 , G11C16/04
CPC分类号： G11C16/12 , G11C5/145 , G11C11/5628 , G11C16/04 , G11C16/30 , G11C16/3459 , G11C29/02 , G11C29/021 , G11C29/028
摘要： Regulating a program voltage value during multilevel memory device programming includes utilizing a program path duplicate in an output pump regulator circuit. Further, the output pump regulator circuit is utilized to provide a regulated program voltage for memory cell programming, the regulated program voltage correcting for a program path voltage drop.
摘要翻译：在多级存储器件编程期间调节编程电压值包括在输出泵调节器电路中使用程序路径副本。此外，输出泵调节器电路用于为存储器单元编程提供调节的编程电压，用于编程路径电压降的调节的编程电压。

27. 发明授权

US07301814B2 System and method for avoiding offset in and reducing the footprint of a non-volatile memory 有权
标题翻译：用于避免偏移和减少非易失性存储器的占用空间的系统和方法
公开(公告)号：US07301814B2
公开(公告)日：2007-11-27
申请号：US11126473
申请日：2005-05-11
申请人： Massimiliano Frulio , Riccardo Riva Reggiori , Andrea Sacco , Luca Figini
发明人： Massimiliano Frulio , Riccardo Riva Reggiori , Andrea Sacco , Luca Figini
IPC分类号： G11C11/34 , G11C16/06
CPC分类号： G11C16/28 , G11C16/3436
摘要： A system and method for avoiding offset in and reducing the footprint of a non-volatile memory that has a plurality of memory bank circuits. Each memory bank circuit has memory cells coupled to sense amplifiers, row and column decoders coupled to the memory cells, and bias circuits coupled to the sense amplifiers. The system includes a reference cell matrix coupled to each of the plurality of memory bank circuits. The reference cell matrix is configured to provide reference cell current for each of the plurality of memory bank circuits.
摘要翻译：一种用于避免偏移并减小具有多个存储器组电路的非易失性存储器的占位面积的系统和方法。每个存储体电路具有耦合到读出放大器，耦合到存储器单元的行和列解码器以及耦合到读出放大器的偏置电路的存储单元。该系统包括耦合到多个存储体电路中的每一个的参考单元矩阵。参考单元矩阵被配置为为多个存储体电路中的每一个提供参考单元电流。

28. 发明授权

US06954102B2 Fast dynamic mirror sense amplifier with separate comparison equalization and evaluation paths 有权
标题翻译：快速动态镜像放大器，具有独立的比较均衡和评估路径
公开(公告)号：US06954102B2
公开(公告)日：2005-10-11
申请号：US10407640
申请日：2003-04-03
申请人： Lorenzo Bedarida , Andrea Sacco , Mirella Marsella , Massimiliano Frulio
发明人： Lorenzo Bedarida , Andrea Sacco , Mirella Marsella , Massimiliano Frulio
IPC分类号： G11C7/06 , G11C7/14 , G11C16/28 , G03F1/10
CPC分类号： G11C7/14 , G11C7/062 , G11C7/067 , G11C16/28 , G11C2207/063
摘要： A memory cell sensing circuit to sense data from a memory cell includes a reference memory cell coupled to pass a reference current. A sense amplifier has a first input and a second input coupled to a bias circuit of the data memory cell. A first mirror mirrors the reference current to a voltage coupled to the first input of the sense amplifier. A second mirror mirrors the reference current to a voltage coupled to the bias circuit of the data memory cell. A third mirror mirrors the reference current to a voltage coupled to the second input of the sense amplifier through a pass gate.
摘要翻译：用于感测来自存储器单元的数据的存储单元感测电路包括耦合以传递参考电流的参考存储单元。读出放大器具有耦合到数据存储单元的偏置电路的第一输入和第二输入。第一镜将参考电流反射到耦合到读出放大器的第一输入端的电压。第二镜将参考电流反射到耦合到数据存储单元的偏置电路的电压。第三反射镜将参考电流反射到通过传输门耦合到读出放大器的第二输入的电压。

29. 发明授权

US06831499B2 Negative charge pump with bulk biasing 有权
标题翻译：带负电荷的负电荷泵
公开(公告)号：US06831499B2
公开(公告)日：2004-12-14
申请号：US10407615
申请日：2003-04-03
申请人： Giorgio Oddone , Massimiliano Frulio , Luca Figini , Fabio Tassan Caser
发明人： Giorgio Oddone , Massimiliano Frulio , Luca Figini , Fabio Tassan Caser
IPC分类号： G05F110
CPC分类号： H02M3/073 , H02M2003/071 , H02M2003/075 , H02M2003/078
摘要： An n-channel MOS transistor negative-voltage charge pump is disclosed in which the bulks of the n-channel MOS transistors are biased in such a manner as to prevent turning on the parasitic bipolar transistor inherent in the CMOS environment of the charge pump structure.
摘要翻译：公开了一种n沟道MOS晶体管负电压电荷泵，其中n沟道MOS晶体管的体积以这样的方式被偏置，以防止接通电荷泵结构的CMOS环境中固有的寄生双极晶体管。

30. 发明申请

US20080170454A1 Sense amplifier with stages to reduce capacitance mismatch in current mirror load 有权
标题翻译：具有阶段的感应放大器，以减少电流镜像负载中的电容失配
公开(公告)号：US20080170454A1
公开(公告)日：2008-07-17
申请号：US11652770
申请日：2007-01-12
申请人： Gabriele Pelli , Lorenzo Bedarida , Massimiliano Frulio , Davide Manfre
发明人： Gabriele Pelli , Lorenzo Bedarida , Massimiliano Frulio , Davide Manfre
IPC分类号： G11C7/06
CPC分类号： G11C7/062 , G11C7/067 , G11C16/28 , G11C2207/063
摘要： A sense amplifier circuit for reading the state of memory cells. In one aspect of the invention, the sense amplifier circuit includes a first stage receiving a cell current derived from the memory cell and a reference current derived from a reference cell, and a second stage receiving the cell current and the reference current. A comparator, coupled to the first stage and the second stage, provides an output indicative of the state of the memory cell based on a difference of the voltages provided by the first stage and the second stage, where the state indicated by the comparator is substantially unaffected by capacitive current components provided by transient behavior of the first and second stages.
摘要翻译：一种用于读取存储器单元状态的读出放大器电路。在本发明的一个方面，读出放大器电路包括接收从存储单元导出的单元电流的第一级和从参考单元导出的参考电流，以及接收单元电流和参考电流的第二级。耦合到第一级和第二级的比较器基于由第一级和第二级提供的电压的差提供指示存储器单元的状态的输出，其中由比较器指示的状态基本上不受由第一和第二级的瞬态特性提供的电容电流分量的影响。

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