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21. 发明申请

WO2010068530A2 GRADED HIGH GERMANIUM COMPOUND FILMS FOR STRAINED SEMICONDUCTOR DEVICES 审中-公开
标题翻译：用于应变半导体器件的梯度高锗化合物膜
公开(公告)号：WO2010068530A2
公开(公告)日：2010-06-17
申请号：PCT/US2009/066334
申请日：2009-12-02
申请人： INTEL CORPORATION , SIMONELLI, Danielle , MURTHY, Anand
发明人： SIMONELLI, Danielle , MURTHY, Anand
IPC分类号： H01L21/20 , H01L21/336
CPC分类号： H01L21/0245 , H01L21/02381 , H01L21/0251 , H01L21/02532 , H01L21/02579 , H01L21/0262 , H01L21/02636 , H01L29/517 , H01L29/66636 , H01L29/66795 , H01L29/7834 , H01L29/7848 , H01L29/785
摘要： Embodiments of an apparatus and methods for providing a graded high germanium compound region are generally described herein. Other embodiments may be described and claimed.
摘要翻译：本文总体上描述了用于提供渐变高锗化合物区域的装置和方法的实施例。其他实施例可以被描述和要求保护。

22. 发明申请

WO2009079159A3 SYSTEMS AND METHODS TO INCREASE UNIAXIAL COMPRESSIVE STRESS IN TRI-GATE TRANSISTORS 审中-公开
公开(公告)号：WO2009079159A3
公开(公告)日：2009-06-25
申请号：PCT/US2008/084344
申请日：2008-11-21
申请人： INTEL CORPORATION , RAKSHIT, Titash , GILES, Martin D. , GHANI, Tahir , MURTHY, Anand , CEA, Stephen M.
发明人： RAKSHIT, Titash , GILES, Martin D. , GHANI, Tahir , MURTHY, Anand , CEA, Stephen M.
IPC分类号： H01L21/336 , H01L29/78
摘要： A transistor structure that increases uniaxial compressive stress on the channel region of a tri-gate transistor comprises at least two semiconductor bodies formed on a substrate, each semiconductor body having a pair of laterally opposite sidewalls and a top surface, a common source region formed on one end of the semiconductor bodies, wherein the common source region is coupled to all of the at least two semiconductor bodies, a common drain region formed on another end of the semiconductor bodies, wherein the common drain region is coupled to all of the at least two semiconductor bodies, and a common gate electrode formed over the at least two semiconductor bodies, wherein the common gate electrode provides a gate electrode for each of the at least two semiconductor bodies and wherein the common gate electrode has a pair of laterally opposite sidewalls that are substantially perpendicular to the sidewalls of the semiconductor bodies.

23. 发明申请

WO2005062366A1 METHOD FOR IMPROVING TRANSISTOR PERFORMANCE THROUGH REDUCING THE SALICIDE INTERFACE RESISTANCE 审中-公开
标题翻译：通过减少绝缘体接触电阻来提高晶体管性能的方法
公开(公告)号：WO2005062366A1
公开(公告)日：2005-07-07
申请号：PCT/US2004/038986
申请日：2004-11-19
申请人： INTEL CORPORATION , MURTHY, Anand , BOYANOV, Boyan , GLASS, Glenn , HOFFMANN, Thomas
发明人： MURTHY, Anand , BOYANOV, Boyan , GLASS, Glenn , HOFFMANN, Thomas
IPC分类号： H01L21/336
CPC分类号： H01L29/7848 , H01L21/28518 , H01L21/823807 , H01L21/823814 , H01L29/0653 , H01L29/0847 , H01L29/165 , H01L29/167 , H01L29/36 , H01L29/41725 , H01L29/6628 , H01L29/665 , H01L29/6653 , H01L29/6656 , H01L29/6659 , H01L29/66628 , H01L29/66636 , H01L29/78 , H01L29/7833 , H01L29/7842 , Y10S438/933
摘要： An embodiment of the invention reduces the external resistance of a transistor by utilizing a silicon germanium alloy for the source and drain regions and a nickel silicon germanium self-aligned silicide (i.e., salicide) layer to form the contact surface of the source and drain regions. The interface of the silicon germanium and the nickel silicon germanium silicide has a lower specific contact resistivity based on a decreased metalsemiconductor work function between the silicon germanium and the silicide and the increased carrier mobility in silicon germanium versus silicon. The silicon germanium may be doped to further tune its electrical properties. A reduction of the external resistance of a transistor equates to increased transistor performance both in switching speed and power consumption.
摘要翻译：本发明的一个实施例通过利用用于源极和漏极区域的硅锗合金和镍硅锗自对准硅化物（即，自对准硅化物）层来形成源极和漏极区域的接触表面来降低晶体管的外部电阻。基于硅锗和硅化物之间的金属半导体功函数降低，硅锗与硅硅锗的界面具有较低的比接触电阻率，并且硅锗与硅中的载流子迁移率增加。可以掺杂硅锗以进一步调整其电性能。降低晶体管的外部电阻等同于在开关速度和功耗方面提高晶体管的性能。

24. 发明申请

WO2019132904A1 SOURCE ELECTRODE AND DRAIN ELECTRODE PROTECTION FOR NANOWIRE TRANSISTORS 审中-公开
公开(公告)号：WO2019132904A1
公开(公告)日：2019-07-04
申请号：PCT/US2017/068624
申请日：2017-12-28
申请人： INTEL CORPORATION , JAMBUNATHAN, Karthik , GUHA, Biswajeet , MURTHY, Anand S. , GHANI, Tahir
发明人： JAMBUNATHAN, Karthik , GUHA, Biswajeet , MURTHY, Anand S. , GHANI, Tahir
IPC分类号： H01L29/78 , H01L29/66 , H01L29/06 , H01L29/41 , H01L21/768
摘要： Embodiments herein describe techniques, systems, and method for a semiconductor device. A nanowire transistor may include a channel region including a nanowire above a substrate, a source electrode coupled to a first end of the nanowire through a first etch stop layer, and a drain electrode coupled to a second end of the nanowire through a second etch stop layer. A gate electrode may be above the substrate to control conductivity in at least a portion of the channel region. A first spacer may be above the substrate between the gate electrode and the source electrode, and a second spacer may be above the substrate between the gate electrode and the drain electrode. A gate dielectric layer may be between the channel region and the gate electrode. Other embodiments may be described and/or claimed.

25. 发明申请

WO2019005114A1 FIELD EFFECT TRANSISTORS WITH WIDE BANDGAP MATERIALS 审中-公开
公开(公告)号：WO2019005114A1
公开(公告)日：2019-01-03
申请号：PCT/US2017/040328
申请日：2017-06-30
申请人： INTEL CORPORATION , MA, Sean T. , DEWEY, Gilbert , RACHMADY, Willy , METZ, Matthew V. , HUANG, Cheng-Ying , KENNEL, Harold W. , KAVALIEROS, Jack T. , MURTHY, Anand S. , GHANI, Tahir
发明人： MA, Sean T.
IPC分类号： H01L29/78 , H01L29/66
摘要： An electronic device comprises a channel layer on a buffer layer on a substrate. The channel layer has a first portion and a second portion adjacent to the first portion. The first portion comprises a first semiconductor. The second portion comprises a second semiconductor that has a bandgap greater than a bandgap of the first semiconductor.

26. 发明申请

WO2016190858A1 APPARATUS AND METHODS TO CREATE A BUFFER WHICH EXTENDS INTO A GATED REGION OF A TRANSISTOR 审中-公开
标题翻译：产生延伸到晶体管的区域的缓冲器的装置和方法
公开(公告)号：WO2016190858A1
公开(公告)日：2016-12-01
申请号：PCT/US2015/032612
申请日：2015-05-27
申请人： INTEL CORPORATION , MOHAPATRA, Chandra, S. , DEWEY, Gilbert , MURTHY, Anand, S. , GLASS, Glenn, A. , RACHMADY, Willy , KAVALIEROS, Jack, T. , GHANI, Tahir , METZ, Matthew, V.
发明人： MOHAPATRA, Chandra, S. , DEWEY, Gilbert , MURTHY, Anand, S. , GLASS, Glenn, A. , RACHMADY, Willy , KAVALIEROS, Jack, T. , GHANI, Tahir , METZ, Matthew, V.
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/78609 , H01L29/0673 , H01L29/1054 , H01L29/42392 , H01L29/66522 , H01L29/66742 , H01L29/66795 , H01L29/785 , H01L29/78681 , H01L29/78696
摘要： Transistor devices may be formed having a buffer between an active channel and a substrate, wherein the active channel and a portion of the buffer form a gated region. The active channel may comprise a low band-gap material on a sub-structure, e.g. the buffer, between the active channel and the substrate. The sub-structure may comprise a high band-gap material having a desired conduction band offset, such that leakage may be arrested without significant impact on electron mobility within the active channel. In an embodiment, the active channel and the sub-structure may be formed in a narrow trench, such that defects due to lattice mismatch between the active channel and the sub-structure are terminated in the sub-structure.
摘要翻译：可以形成晶体管器件，其具有在有源沟道和衬底之间的缓冲器，其中所述有源沟道和所述缓冲器的一部分形成选通区域。有源沟道可以包括在子结构上的低带隙材料，例如。缓冲器，在有源沟道和衬底之间。子结构可以包括具有期望导带偏移的高带隙材料，使得可以阻止泄漏而不会对有源沟道内的电子迁移率产生显着影响。在一个实施例中，有源沟道和子结构可以形成在窄沟槽中，使得由于在有源沟道和子结构之间的晶格失配导致的缺陷在子结构中终止。

27. 发明申请

WO2016105377A1 APPARATUS AND METHODS OF FORMING FIN STRUCTURES WITH SIDEWALL LINER 审中-公开
标题翻译：使用小型衬板形成结构的装置和方法
公开(公告)号：WO2016105377A1
公开(公告)日：2016-06-30
申请号：PCT/US2014/072089
申请日：2014-12-23
申请人： INTEL CORPORATION , RACHMADY, Willy , METZ, Matthew V. , MOHAPATRA, Chandra S. , DEWEY, Gilbert , KAVALIEROS, Jack T. , MURTHY, Anand S. , RAHHAL-ORABI, Nadia M. , GHANI, Tahir , GLASS, Glenn A.
发明人： RACHMADY, Willy , METZ, Matthew V. , MOHAPATRA, Chandra S. , DEWEY, Gilbert , KAVALIEROS, Jack T. , MURTHY, Anand S. , RAHHAL-ORABI, Nadia M. , GHANI, Tahir , GLASS, Glenn A.
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/66795 , H01L21/762 , H01L27/108 , H01L29/04 , H01L29/0649 , H01L29/1054 , H01L29/42392 , H01L29/66484 , H01L29/785 , H01L29/7851 , H01L29/78696 , H01L2029/7858
摘要： An includes an epitaxial sub-fin structure disposed on a substrate, wherein a first portion of the sub-fin structure is disposed within a portion of the substrate, and a second portion of the sub-fin structure is disposed adjacent a dielectric material. A fin device structure is disposed on the sub-fin structure, wherein the fin device structure comprises the epitaxial material. A liner is disposed between the second portion of the sub-fin structure and the dielectric material. Other embodiments are described herein.
摘要翻译： An包括设置在基板上的外延子鳍结构，其中子鳍结构的第一部分设置在衬底的一部分内，并且副鳍结构的第二部分邻近电介质材料设置。翅片装置结构设置在子鳍结构上，其中翅片装置结构包括外延材料。衬垫设置在子鳍结构的第二部分和电介质材料之间。本文描述了其它实施例。

28. 发明申请

WO2016043770A1 APPARATUS AND METHODS TO CREATE A BUFFER TO REDUCE LEAKAGE IN MICROELECTRONIC TRANSISTORS 审中-公开
标题翻译：创建缓冲器以减少微电子晶体管泄漏的装置和方法
公开(公告)号：WO2016043770A1
公开(公告)日：2016-03-24
申请号：PCT/US2014/056528
申请日：2014-09-19
申请人： INTEL CORPORATION , MOHAPATRA, Chandra S. , MURTHY, Anand S. , GLASS, Glen A. , GHANI, Tahir , KAVALIEROS, Jack T. , RACHMADY, Willy , METZ, Matthew V. , DEWEY, Gilbert
发明人： MOHAPATRA, Chandra S. , MURTHY, Anand S. , GLASS, Glen A. , GHANI, Tahir , KAVALIEROS, Jack T. , RACHMADY, Willy , METZ, Matthew V. , DEWEY, Gilbert
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7827 , H01L21/76224 , H01L29/0649 , H01L29/1054 , H01L29/201 , H01L29/4238 , H01L29/66545 , H01L29/66666 , H01L29/785 , H01L29/78696
摘要： Transistor devices having a buffer between an active channel and a substrate, which may include the active channel comprising a low band-gap material on a sub-structure, e.g. a buffer, between the active channel and the substrate. The sub-structure may comprise a high band-gap material having a desired conduction band offset, such that leakage may be arrested without significant impact on electronic mobility within the active channel. In an embodiment, the active channel and the sub-structure may be formed in a narrow trench, such that defects due to lattice mismatch between the active channel and the sub-structure are terminated in the sub-structure. In a further embodiment, the sub-structure may be removed to form either a void between the active channel and the substrate, or an insulative material may be disposed between the active channel and the substrate, such that the void or the insulative material form an insulative buffer.
摘要翻译：具有在有源沟道和衬底之间的缓冲器的晶体管器件，其可以包括在子结构上包括低带隙材料的有源沟道，例如，一个缓冲器，位于有源通道和衬底之间。子结构可以包括具有期望的导带偏移的高带隙材料，使得可以在没有对有源沟道内的电子迁移率的显着影响的情况下阻止泄漏。在一个实施例中，有源沟道和子结构可以形成在窄沟槽中，使得由于在有源沟道和子结构之间的晶格失配导致的缺陷在子结构中终止。在另一个实施例中，子结构可以被去除以在有源沟道和衬底之间形成空隙，或者绝缘材料可以设置在有源沟道和衬底之间，使得空隙或绝缘材料形成绝缘缓冲。

29. 发明申请

WO2015147783A1 TECHNIQUES FOR ACHIEVING MULTIPLE TRANSISTOR FIN DIMENSIONS ON A SINGLE DIE 审中-公开
标题翻译：在单个DIE上实现多个晶体管尺寸的技术
公开(公告)号：WO2015147783A1
公开(公告)日：2015-10-01
申请号：PCT/US2014/031599
申请日：2014-03-24
申请人： INTEL CORPORATION , GLASS, Glenn, A. , MURTHY, Anand, S.
发明人： GLASS, Glenn, A. , MURTHY, Anand, S.
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L27/0924 , H01L21/3065 , H01L21/3081 , H01L21/823807 , H01L21/823821 , H01L29/66545 , H01L29/66818 , H01L29/785
摘要： Techniques are disclosed for achieving multiple fin dimensions on a single die or semiconductor substrate. In some cases, multiple fin dimensions are achieved by lithographically defining (e.g., hardmasking and patterning) areas to be trimmed using a trim etch process, leaving the remainder of the die unaffected. In some such cases, the trim etch is performed on only the channel regions of the fins, when such channel regions are re-exposed during a replacement gate process. The trim etch may narrow the width of the fins being trimmed (or just the channel region of such fins) by 2-6 nm, for example. Alternatively, or in addition, the trim may reduce the height of the fins. The techniques can include any number of patterning and trimming processes to enable a variety of fin dimensions and/or fin channel dimensions on a given die, which may be useful for integrated circuit and system-on-chip (SOC) applications.
摘要翻译：公开了在单个管芯或半导体衬底上实现多个鳍尺寸的技术。在一些情况下，通过使用修剪蚀刻工艺光刻地限定（例如，硬掩模和图案化）待修剪的区域来实现多个鳍尺寸，从而不影响裸片的其余部分。在一些这样的情况下，当在更换栅极处理期间这种沟道区域被再曝光时，仅对散热片的沟道区域进行修整蚀刻。修整蚀刻可以使被修剪的翅片的宽度（或者仅仅是这种翅片的通道区域）变窄例如2-6nm。或者，或者另外，修整件可以减小翅片的高度。这些技术可以包括任何数量的图案化和修整过程，以使得在给定裸片上可以有用的集成电路和片上系统（SOC）应用中的各种鳍尺寸和/或鳍通道尺寸。

30. 发明申请

WO2014142952A1 NANOWIRE TRANSISTOR WITH UNDERLAYER ETCH STOPS 审中-公开
标题翻译：具有下层蚀刻层的纳米晶体管
公开(公告)号：WO2014142952A1
公开(公告)日：2014-09-18
申请号：PCT/US2013/031964
申请日：2013-03-15
申请人： INTEL CORPORATION , KIM, Seiyon , AUBERTINE, Daniel , KUHN, Kelin , MURTHY, Anand
发明人： KIM, Seiyon , AUBERTINE, Daniel , KUHN, Kelin , MURTHY, Anand
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/66795 , H01L29/0673 , H01L29/1037 , H01L29/42392 , H01L29/66439 , H01L29/66545 , H01L29/6656 , H01L29/6681 , H01L29/66818 , H01L29/775 , H01L29/785 , H01L29/78696
摘要： A nanowire device of the present description may be produced with the incorporation of at least one underlayer etch stop formed during the fabrication of at least one nanowire transistor in order to assist in protecting source structures and/or drain structures from damage that may result from fabrication processes. The underlayer etch stop may prevent damage to the source structures and/or drain the structures, when the material used in the fabrication of the source structures and/or the drain structures is susceptible to being etched by the processes used in the removal of the sacrificial materials, i.e. low selectively to the source structure and/or the drain structure materials, such that potential shorting between the transistor gate electrodes and contacts formed for the source structures and/or the drain structures may be prevented.
摘要翻译：本描述的纳米线器件可以通过结合在制造至少一个纳米线晶体管期间形成的至少一个底层蚀刻停止来产生，以便有助于保护源结构和/或漏极结构免受由制造引起的损伤流程。当用于制造源结构和/或漏极结构的材料易于被用于去除牺牲物的过程被蚀刻时，底层蚀刻停止件可以防止对源结构的损坏和/或排出结构材料，即选择性地低至源极结构和/或漏极结构材料，使得可以防止晶体管栅电极和为源极结构和/或漏极结构形成的触点之间的电位短路。

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