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21. 发明授权

US08179707B2 Semiconductor memory devices and methods of arranging memory cell arrays thereof 失效
标题翻译：半导体存储器件及其排列存储单元阵列的方法
公开(公告)号：US08179707B2
公开(公告)日：2012-05-15
申请号：US12453595
申请日：2009-05-15
申请人： Ki-Whan Song , Yeong-Taek Lee
发明人： Ki-Whan Song , Yeong-Taek Lee
IPC分类号： G11C5/02
CPC分类号： G11C7/18 , G11C8/08 , G11C8/14 , G11C11/4097 , G11C13/00 , G11C13/0004 , G11C13/0023 , G11C13/0026 , G11C13/0028 , G11C2211/4016 , G11C2213/79 , H01L27/0207 , H01L27/108 , H01L27/10802 , H01L27/10891
摘要： Semiconductor memory devices with a memory cell array including a first word line and a second word line arranged in a first direction, a source line arranged in the first direction between the first word line and the second word line, a bit line pair including a first bit line and a second bit line arranged in a second direction perpendicular to the first direction, a first memory cell including a gate connected to the first word line and first and second regions respectively connected to the second bit line and the source line, and arranged in a third direction between the first direction and the second direction, and a second memory cell including a gate connected to the second word line, a third region and the second region respectively connected to the first bit line and the source line, and arranged in the third direction.
摘要翻译：具有包括沿第一方向布置的第一字线和第二字线的存储单元阵列的半导体存储器件，在第一字线和第二字线之间沿第一方向布置的源极线，包括第一位线和与第一方向垂直的第二方向排列的第二位线，第一存储单元，包括连接到第一字线的栅极和分别连接到第二位线和源极线的第一和第二区域，并且布置在第一方向和第二方向之间的第三方向上，以及第二存储单元，包括连接到第二字线的栅极，分别连接到第一位线和源极线的第三区域和第二区域，并且布置在第三个方向。

22. 发明授权

US08023337B2 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US08023337B2
公开(公告)日：2011-09-20
申请号：US12591176
申请日：2009-11-12
申请人： Hoe-Ju Chung , Ki-Whan Song
发明人： Hoe-Ju Chung , Ki-Whan Song
IPC分类号： G11C16/04
CPC分类号： G11C7/06 , G11C7/1012 , G11C7/12 , G11C7/18 , G11C2207/005
摘要： A semiconductor memory device having shared sense amplifiers is provided. The semiconductor memory device has a bit-line selector disposed closer to a memory cell array than a column decoder. When the column decoder outputs a bit-line indication signal corresponding to the number of bit lines, the bit-line selector selects a plurality of bit lines in response to the bit-line indication signal. Thus, it is possible to reduce the number of signals output from the column decoder.
摘要翻译：提供了具有共享读出放大器的半导体存储器件。半导体存储器件具有比列解码器更靠近存储单元阵列设置的位线选择器。当列解码器输出与位线数相对应的位线指示信号时，位线选择器响应于位线指示信号选择多个位线。因此，可以减少从列解码器输出的信号的数量。

23. 发明授权

US08009473B2 Semiconductor memory device including memory cell array having memory cells using floating body transistors 失效
标题翻译：半导体存储器件包括具有使用浮体晶体管的存储单元的存储单元阵列
公开(公告)号：US08009473B2
公开(公告)日：2011-08-30
申请号：US12344765
申请日：2008-12-29
申请人： Duk-Ha Park , Ki-Whan Song
发明人： Duk-Ha Park , Ki-Whan Song
IPC分类号： G11C11/34
CPC分类号： G11C11/404 , G11C8/08 , G11C8/14 , G11C11/4097 , G11C2211/4016 , H01L27/0207 , H01L27/108 , H01L27/10802 , H01L27/10882 , H01L29/7841
摘要： A semiconductor memory device includes a memory cell array, which includes a cell array having multiple cell blocks. Each cell block includes source and word lines arranged in one direction, bit lines arranged in a perpendicular direction, and memory cells having corresponding floating bodies. Adjacent memory cells share source or drain regions to form common source or drain regions, respectively. The source regions are arranged in a word line direction and connected to corresponding source lines, and the drain regions are arranged in the bit line direction and connected to corresponding bit lines. Gates of the memory cells are arranged in the word line direction and are connected to form the word lines. The source lines are formed on a layer of the word lines, and the bit lines are formed at a different layer to be insulated from the word and source lines.
摘要翻译：半导体存储器件包括存储单元阵列，其包括具有多个单元块的单元阵列。每个单元块包括沿一个方向布置的源极和字线，沿垂直方向排列的位线，以及具有相应浮体的存储单元。相邻的存储单元分别共享源极或漏极区域以形成共同的源极或漏极区域。源极区域以字线方向排列并连接到相应的源极线，并且漏极区域以位线方向排列并连接到相应的位线。存储器单元的栅极被排列在字线方向上并被连接以形成字线。源极线形成在字线的一层上，位线形成在与字线和源极线绝缘的不同层上。

24. 发明申请

US20110163371A1 METHODS OF FABRICATING NONVOLATILE SEMICONDUCTOR MEMORY DEVICES 有权
标题翻译：制造非易失性半导体存储器件的方法
公开(公告)号：US20110163371A1
公开(公告)日：2011-07-07
申请号：US13047403
申请日：2011-03-14
申请人： Ki-whan Song , Byung-Gook Park
发明人： Ki-whan Song , Byung-Gook Park
IPC分类号： H01L29/772
CPC分类号： H01L27/115 , H01L27/11519 , H01L27/11568 , H01L29/792 , H01L29/7926
摘要： A nonvolatile semiconductor memory device includes a plurality of pillars protruding upward from a semiconductor substrate and having respective top surfaces and opposing sidewalls, a bit line on the top surfaces of the pillars and connecting a row of the pillars along a first direction, a pair of word lines on the opposing sidewalls of one of the plurality of pillars and crossing beneath the bit line, and a pair of memory layers interposed between respective ones of the pair of word lines and the one of the plurality of pillars. Methods of fabricating a nonvolatile semiconductor memory device include selectively etching a semiconductor substrate to form pluralities of stripes having opposing sidewalls and being arranged along a direction, forming memory layers and word lines along the sidewalls of the stripes selectively etching the stripes to form a plurality of pillars, and forming a bit line connecting the pillars and crossing above the word lines.
摘要翻译：非易失性半导体存储器件包括从半导体衬底向上突出并具有相应顶表面和相对侧壁的多个柱，在柱的顶表面上的位线，并沿着第一方向连接一排柱，一对在多个柱中的一个柱的相对的侧壁上并且在位线下方交叉的字线以及插入在该对字线中的相应一个字线和多个柱之一之间的一对存储层。制造非易失性半导体存储器件的方法包括选择性地蚀刻半导体衬底以形成具有相对侧壁并沿着方向布置的多个条纹，沿着条纹的侧壁形成存储层和字线，选择性地蚀刻条纹以形成多个并且形成连接柱子并跨越字线上方的位线。

25. 发明授权

US07969808B2 Memory cell structures, memory arrays, memory devices, memory controllers, and memory systems, and methods of manufacturing and operating the same 失效
标题翻译：存储单元结构，存储器阵列，存储器件，存储器控制器和存储器系统，以及制造和操作存储器单元结构的方法
公开(公告)号：US07969808B2
公开(公告)日：2011-06-28
申请号：US12171406
申请日：2008-07-11
申请人： Ki-Whan Song , Nam-Kyun Tak
发明人： Ki-Whan Song , Nam-Kyun Tak
IPC分类号： G11C11/00
CPC分类号： H01L27/108 , G11C11/406 , G11C11/40618 , G11C11/40622 , G11C2211/4016 , H01L27/10802 , H01L29/7841
摘要： Example embodiments are directed to memory cell structures, memory arrays, memory devices, memory controllers, and memory systems using bipolar junction transistor (BJT) operation.
摘要翻译：示例性实施例涉及使用双极结型晶体管（BJT）操作的存储器单元结构，存储器阵列，存储器件，存储器控制器和存储器系统。

26. 发明授权

US07924644B2 Semiconductor memory device including floating body transistor memory cell array and method of operating the same 失效
标题翻译：半导体存储器件包括浮体晶体管存储单元阵列及其操作方法
公开(公告)号：US07924644B2
公开(公告)日：2011-04-12
申请号：US12348036
申请日：2009-01-02
申请人： Duk-ha Park , Ki-Whan Song
发明人： Duk-ha Park , Ki-Whan Song
IPC分类号： G11C7/00
CPC分类号： G11C8/18 , G11C11/404 , G11C11/406 , G11C11/4076 , G11C2211/4016
摘要： A semiconductor memory device includes a memory cell array including a plurality of memory cells, where each memory cell includes a transistor with a floating body region in which majority carriers are accumulated in a steady state. In write and read operations, a first data state corresponding to the steady state is written to and read from at least one selected memory cell of the memory cell array by supplying a first bipolar current through the at least one selected memory cell, and a second data state is written to and read from the at least one selected memory cell by supplying a second bipolar current which is smaller than the first bipolar current through the at least one selected memory cell. In a refresh operation, memory cells of the memory cell array storing the second data state are refreshed.
摘要翻译：半导体存储器件包括包括多个存储单元的存储单元阵列，其中每个存储器单元包括具有浮动体区域的晶体管，其中多数载流子以稳定状态累积。在写入和读取操作中，通过提供通过所述至少一个选择的存储器单元的第一双极性电流，将与稳态对应的第一数据状态写入存储单元阵列的至少一个所选择的存储单元并从其读出，通过提供比通过所述至少一个所选择的存储单元小的第一双极性电流的第二双极电流，将数据状态写入至少一个所选存储单元并从其读出。在刷新操作中，存储第二数据状态的存储单元阵列的存储单元被刷新。

27. 发明申请

US20100118631A1 Semiconductor memory devices with mismatch cells 有权
标题翻译：具有不匹配单元的半导体存储器件
公开(公告)号：US20100118631A1
公开(公告)日：2010-05-13
申请号：US12591196
申请日：2009-11-12
申请人： Jin-Young Kim , Chul-Woo Park , Ki-Whan Song
发明人： Jin-Young Kim , Chul-Woo Park , Ki-Whan Song
IPC分类号： G11C7/00 , G11C7/06
CPC分类号： G11C11/4099 , G11C11/4091
摘要： A semiconductor memory device having the mismatch cell makes a capacitance difference between a bit line pair relatively large during a read operation using at least one dummy memory cell as a mismatch cell selected together with a corresponding memory cell. Therefore, data of a semiconductor memory device may be detected more easily.
摘要翻译：具有不匹配单元的半导体存储器件在使用至少一个虚拟存储器单元作为与对应的存储器单元一起选择的不匹配单元的读取操作期间，位线对之间的电容差相对较大。因此，可以更容易地检测半导体存储器件的数据。

28. 发明授权

US07709308B2 Semiconductor devices and methods of fabricating the same including forming a fin with first and second gates on the sidewalls 有权
标题翻译：半导体器件及其制造方法，包括在侧壁上形成具有第一和第二栅极的鳍片
公开(公告)号：US07709308B2
公开(公告)日：2010-05-04
申请号：US12194343
申请日：2008-08-19
申请人： Chang-Woo Oh , Ki-Whan Song
发明人： Chang-Woo Oh , Ki-Whan Song
IPC分类号： H01L21/00 , H01L21/84 , H01L21/338 , H01L21/336
CPC分类号： H01L27/1203 , H01L21/28282 , H01L27/115 , H01L27/11568 , H01L29/785
摘要： Disclosed is a semiconductor device and method of fabricating the same. The device is disposed on a substrate, including a fin constructed with first and second sidewalls, a first gate line formed in the pattern of spacer on the first sidewall of the fin, and a second gate line formed in the pattern of spacer on the second sidewall of the fin. First and second impurity regions are disposed in the fin. The first and second impurity regions are isolated from each other and define a channel region in the fin between the first and second gate lines.
摘要翻译：公开了半导体器件及其制造方法。该器件设置在基板上，包括由第一和第二侧壁构成的鳍片，在鳍片的第一侧壁上以间隔物图案形成的第一栅极线和形成在第二栅极上的间隔物图案中的第二栅极线鳍的侧壁第一和第二杂质区域设置在翅片中。第一和第二杂质区彼此隔离并且在第一和第二栅极线之间的鳍中限定沟道区。

29. 发明授权

US07701793B2 Semiconductor integrated circuit and method of operating the same 失效
标题翻译：半导体集成电路及其操作方法
公开(公告)号：US07701793B2
公开(公告)日：2010-04-20
申请号：US11882931
申请日：2007-08-07
申请人： Jin-Young Kim , Ki-Whan Song , Duk-Ha Park
发明人： Jin-Young Kim , Ki-Whan Song , Duk-Ha Park
IPC分类号： G11C7/00
CPC分类号： G11C11/4091 , G11C11/4096 , G11C2207/002 , G11C2207/005 , G11C2211/4016
摘要： One embodiment includes a plurality of word lines, a plurality of bit lines intersecting with the plurality of word lines, a plurality of memory cells formed at intersections of and connected to the plurality of word lines and the plurality of bit lines. Each of the plurality of memory cells may be a floating body cell. A bit line selecting circuit may be configured to selectively connect each of the plurality of bit lines to an output bit line. The embodiment may further include plurality of sense amplifiers, where the plurality of sense amplifiers is greater than one and less than the plurality of bit lines in number. A sense amplifier switching structure may be configured to selectively connect each of the plurality of sense amplifiers to the output bit line.
摘要翻译：一个实施例包括多个字线，与多个字线相交的多个位线，多个存储单元，形成在多个字线和多个位线的交叉点处并与之连接。多个存储单元中的每一个可以是浮动体单元。位线选择电路可以被配置为选择性地将多个位线中的每一个连接到输出位线。该实施例还可以包括多个读出放大器，其中多个读出放大器的数量大于一个且小于多个位线。读出放大器切换结构可以被配置为选择性地将多个读出放大器中的每一个连接到输出位线。

30. 发明授权

US07633096B2 Silicon-controlled rectifier for electrostatic discharge protection circuits and structure thereof 有权
标题翻译：用于静电放电保护电路的可控硅整流器及其结构
公开(公告)号：US07633096B2
公开(公告)日：2009-12-15
申请号：US11461681
申请日：2006-08-01
申请人： Ki-Whan Song , Yeong-Taek Lee
发明人： Ki-Whan Song , Yeong-Taek Lee
IPC分类号： H01L23/62
CPC分类号： H01L27/0262
摘要： A Silicon-Controlled Rectifier (SCR) for Electrostatic Discharge (ESD) protection includes an isolation device. The isolation device isolates a main ground voltage line, connected to a first cathode, from a peripheral ground voltage line, connected to a second cathode. As result, even when noise occurs in the peripheral ground voltage line during the operation of an integrated circuit, the main ground voltage line maintains a stable voltage level.
摘要翻译：用于静电放电（ESD）保护的硅控整流器（SCR）包括隔离装置。隔离装置将连接到第一阴极的主接地电压线与连接到第二阴极的外围接地电压线隔离。因此，即使在集成电路的动作中，外围接地电压线发生噪声时，主接地电压线保持稳定的电压电平。

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