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21. 发明授权

US6057036A Semiconductor substrate having a serious effect of gettering heavy metal and method of manufacturing the same 失效
标题翻译：具有重吸收重金属的重要作用的半导体衬底及其制造方法
公开(公告)号：US6057036A
公开(公告)日：2000-05-02
申请号：US160352
申请日：1993-11-29
申请人： Kensuke Okonogi
发明人： Kensuke Okonogi
IPC分类号： H01L21/02 , H01L21/322 , H01L21/84 , H01L27/12 , B32B17/06
CPC分类号： H01L21/3226 , H01L21/3221 , Y10T428/12528
摘要： A silicon dioxide layer overlies a monocrystal silicon substrate and has a first upper surface. A first monocrystal silicon layer overlies the first upper surface and has phosphorus atoms diffused. A second monocrystal silicon layer overlies the first monocrystal silicon layer. The first monocrystal silicon layer may have phosphorus or silicon atoms each of which has a positive electric charge instead of the phosphorus atoms diffused. A lattice mismatching layer may overlie the first upper surface instead of the first monocrystal silicon layer. The lattice mismatching layer has parts in each of which misfit dislocation is caused. The first and the second monocrystal silicon layers may overlie the monocrystal silicon substrate and layer, respectively. In this event, a silicon glass layer is interposed between the first and the second monocrystal silicon layers. The second monocrystal silicon layer has phosphorus atoms diffused.
摘要翻译：二氧化硅层覆盖在单晶硅衬底上并具有第一上表面。第一单晶硅层覆盖第一上表面并且具有扩散的磷原子。第二单晶硅层覆盖在第一单晶硅层上。第一单晶硅层可以具有磷或硅原子，其各自具有正电荷而不是扩散的磷原子。晶格失配层可以覆盖第一上表面而不是第一单晶硅层。晶格失配层具有引起错位错位的部分。第一和第二单晶硅层可以分别覆盖在单晶硅衬底和层上。在这种情况下，硅玻璃层插入在第一和第二单晶硅层之间。第二单晶硅层具有扩散的磷原子。

22. 发明授权

US5798294A Semiconductor substrate having a serious effect of gettering heavy metal and method of manufacturing the same 失效
公开(公告)号：US5798294A
公开(公告)日：1998-08-25
申请号：US446056
申请日：1995-05-19
申请人： Kensuke Okonogi
发明人： Kensuke Okonogi
IPC分类号： H01L21/02 , H01L21/322 , H01L21/84 , H01L27/12
CPC分类号： H01L21/3226 , H01L21/3221 , Y10T428/12528
摘要： A silicon dioxide layer overlies a monocrystal silicon substrate and has a first upper surface. A first monocrystal silicon layer overlies the first upper surface and has phosphorus atoms diffused. A second monocrystal silicon layer overlies the first monocrystal silicon layer. The first monocrystal silicon layer may have phosphorus or silicon atoms each of which has a positive electric charge instead of the phosphorus atoms diffused. A lattice mismatching layer may overlie the first upper surface instead of the first monocrystal silicon layer. The lattice mismatching layer has parts in each of which misfit dislocation is caused. The first and the second monocrystal silicon layers may overlie the monocrystal silicon substrate and layer, respectively. In this event, a silicon glass layer is interposed between the first and the second monocrystal silicon layers. The second monocrystal silicon layer has phosphorus atoms diffused.

23. 发明授权

US5726089A Semiconductor device and method for fabricating the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US5726089A
公开(公告)日：1998-03-10
申请号：US562790
申请日：1995-11-27
申请人： Kensuke Okonogi
发明人： Kensuke Okonogi
IPC分类号： H01L21/762 , H01L21/18 , H01L21/20 , H01L21/76 , H01L21/302
CPC分类号： H01L21/185 , H01L21/2007 , H01L21/76264 , H01L21/76275 , H01L21/76281 , H01L21/76283 , H01L21/76286
摘要： A method for fabricating a semiconductor device having a bonded wafer structure capable of reducing crystal defect in a power element forming region thereof is disclosed A recess is formed in a control circuit element forming region of a first n- silicon substrate, then filled with a silicon oxide film and subjected to grinding and polishing to provide a mirror-surface. An n- epitaxial layer is formed on the surface of a second n+ silicon substrate, then the surface of the epitaxial layer is coupled to the surfaces of the silicon oxide film and second circuit region of the first substrate and heat-treated to be bonded thereto.
摘要翻译：公开了一种用于制造具有能够减少其功率元件形成区域中的晶体缺陷的键合晶片结构的半导体器件的方法。在第一n-硅衬底的控制电路元件形成区域中形成凹部，然后填充硅并进行研磨和抛光以提供镜面。在第二n +硅衬底的表面上形成n外延层，然后将外延层的表面耦合到第一衬底的氧化硅膜和第二电路区的表面，并进行热处理以与其结合。

24. 发明授权

US5691231A Method of manufacturing silicon on insulating substrate 失效
标题翻译：在绝缘基板上制造硅的方法
公开(公告)号：US5691231A
公开(公告)日：1997-11-25
申请号：US779226
申请日：1997-01-07
申请人： Kenya Kobayashi , Tomohiro Hamajima , Kensuke Okonogi
发明人： Kenya Kobayashi , Tomohiro Hamajima , Kensuke Okonogi
IPC分类号： H01L21/20 , H01L21/762 , H01L21/76
CPC分类号： H01L21/2007 , H01L21/76264 , H01L21/76275 , H01L21/76286 , Y10S148/012
摘要： A first silicon single crystal substrate and a second silicon single crystal substrate are bonded together and the first silicon single crystal substrate is formed thin as an SOI layer. An insulation film is buried in portions of the bonding surface of one of the two silicon single crystal substrates, and in addition, a polycrystal silicon layer is formed on the bonding surface of the silicon single crystal substrate on the side into which the insulation film is buried.
摘要翻译：第一硅单晶衬底和第二硅单晶衬底被结合在一起，并且第一硅单晶衬底被形成为薄的SOI层。在两个硅单晶衬底之一的接合表面的部分中埋设有绝缘膜，此外，在单晶硅衬底的绝缘膜的一侧的接合面上形成多晶硅层埋葬

25. 发明授权

US5529947A Semiconductor device with clad substrate and fabrication process therefor 失效
标题翻译：具有复合衬底的半导体器件及其制造工艺
公开(公告)号：US5529947A
公开(公告)日：1996-06-25
申请号：US356509
申请日：1994-12-15
申请人： Kensuke Okonogi
发明人： Kensuke Okonogi
IPC分类号： H01L21/02 , H01L21/76 , H01L21/762 , H01L27/12 , H01L21/302 , H01L21/304 , H01L21/306
CPC分类号： H01L21/76 , H01L21/76264 , H01L21/76275 , H01L21/76286
摘要： On a first surface of a first single crystal silicon substrate, in which a silicon dioxide layer having gradually tapered peripheral edge (tapered wall), a second single crystal silicon substrate is clad. On the second surface of the first single crystal silicon substrate, an island form polycrystalline silicon region is isolated from remaining region by an isolation groove to form an element. By reducing step between the buried silicon dioxide layer and the first single crystal silicon substrate, local concentration of a stress can be successfully avoided. Also, abrasion of the silicon oxide layer and single crystal silicon substrate having mutually different etching speeds is not performed so that the step can be lowered to eliminate formation of void. Between the first surface of the first single crystal silicon substrate formed with the elements and the cladding surface, the silicon dioxide layer is present to avoid influence of contaminant penetrating during cladding process. Accordingly, degradation of reliability due to stress concentration and formation of void, and contamination in the SOI clad substrate can be successfully avoided.
摘要翻译：在第一单晶硅衬底的第一单面硅衬底的第二表面上，其中具有逐渐变细的周缘（锥形壁）的二氧化硅层，第二单晶硅衬底被包层。在第一单晶硅衬底的第二表面上，岛状多晶硅区域通过隔离沟槽与剩余区域隔离以形成元件。通过减少掩埋二氧化硅层和第一单晶硅衬底之间的步骤，可以成功地避免局部应力集中。此外，不进行具有相互不同蚀刻速度的氧化硅层和单晶硅衬底的磨损，从而可以降低该步骤以消除空隙的形成。在形成有元件的第一单晶硅衬底的第一表面和包层表面之间，存在二氧化硅层以避免包覆过程中污染物穿透的影响。因此，可以成功地避免由于应力集中和形成空穴引起的可靠性的劣化以及SOI包覆衬底中的污染。

26. 发明申请

US20120161219A1 SEMICONDUCTOR DEVICE 失效
标题翻译：半导体器件
公开(公告)号：US20120161219A1
公开(公告)日：2012-06-28
申请号：US13334964
申请日：2011-12-22
申请人： Kensuke OKONOGI , Kazuhiro NOJIMA , Kiyonori OYU
发明人： Kensuke OKONOGI , Kazuhiro NOJIMA , Kiyonori OYU
IPC分类号： H01L27/108
CPC分类号： H01L21/823892 , H01L27/0928 , H01L27/10873
摘要： a semiconductor device is provided, which includes an N well having a peak concentration of 2E+17 atom/cm3 or more in the range of 0.2 to 1 μm depth from the surface of a P-type semiconductor substrate, and a region provided below the N well, the region containing P-type impurities with higher concentration than concentration of electrons.
摘要翻译：提供一种半导体器件，其包括从P型半导体衬底的表面开始的深度为0.2-1μm的峰值浓度为2E + 17原子/ cm 3以上的N阱，以及设置在P型半导体衬底的下方的区域 N阱，含有比电子浓度高的浓度的P型杂质的区域。

27. 发明授权

US07846826B2 Method of manufacturing a semiconductor device with multilayer sidewall 有权
标题翻译：制造具有多层侧壁的半导体器件的方法
公开(公告)号：US07846826B2
公开(公告)日：2010-12-07
申请号：US12246908
申请日：2008-10-07
申请人： Kiyonori Oyu , Kensuke Okonogi
发明人： Kiyonori Oyu , Kensuke Okonogi
IPC分类号： H01L21/3205 , H01L21/4763
CPC分类号： H01L21/28114 , H01L21/28044 , H01L29/42376 , H01L29/6659 , H01L29/7833
摘要： A gate dielectric film, a poly-silicon film, a film of a refractory metal such as tungsten, and a gate cap dielectric film are sequentially laminated on a semiconductor substrate. The gate cap dielectric film and the refractory metal film are selectively removed by etching. Thereafter, a double protection film including a silicon nitride film and a silicon oxide film is formed on side surfaces of the gate cap dielectric film, the refractory metal film, and the poly-silicon film. The poly-silicon film is etched using the double protection film as a mask. Thereafter, the semiconductor substrate is light oxidized to form a silicon oxide film on side surfaces of the poly-silicon film. Accordingly, a junction leakage of a MOSFET having a gate electrode of a poly-metal structure, particularly, a memory cell transistor of a DRAM, can be further reduced.
摘要翻译：栅极电介质膜，多晶硅膜，耐火金属如钨的膜和栅极盖电介质膜依次层压在半导体衬底上。通过蚀刻选择性地去除栅极电介质膜和难熔金属膜。此后，在栅极盖电介质膜，难熔金属膜和多晶硅膜的侧表面上形成包括氮化硅膜和氧化硅膜的双重保护膜。使用双重保护膜作为掩模蚀刻多晶硅膜。此后，半导体衬底被光氧化以在多晶硅膜的侧表面上形成氧化硅膜。因此，可以进一步减少具有多金属结构的栅电极，特别是DRAM的存储单元晶体管的MOSFET的结漏电。

28. 发明授权

US07632696B2 Semiconductor chip with a porous single crystal layer and manufacturing method of the same 有权
标题翻译：具有多孔单晶层的半导体芯片及其制造方法相同
公开(公告)号：US07632696B2
公开(公告)日：2009-12-15
申请号：US11372351
申请日：2006-03-10
申请人： Kiyonori Oyu , Koji Hamada , Kensuke Okonogi , Hideharu Miyake , Yasushi Kozuki , Masaharu Watanabe
发明人： Kiyonori Oyu , Koji Hamada , Kensuke Okonogi , Hideharu Miyake , Yasushi Kozuki , Masaharu Watanabe
IPC分类号： H01L21/00
CPC分类号： H01L21/306 , H01L21/304 , H01L21/78
摘要： A semiconductor chip including a semiconductor substrate provided with a semiconductor device region and a porous single crystal layer, where the semiconductor device region is formed on the main surface portion of the semiconductor substrate, and the porous single crystal layer is formed in an inner region on the backside of the semiconductor substrate, and is comprised of erosion holes extending continuously from the backside of the semiconductor substrate in an inward direction of the semiconductor substrate, oxide films formed on inner surfaces of the erosion holes, and a single crystal portion.
摘要翻译：一种半导体芯片，包括设置有半导体器件区域的半导体衬底和多孔单晶层，其中半导体器件区域形成在半导体衬底的主表面部分上，并且多孔单晶层形成在半导体衬底的背面，并且包括从半导体衬底的背面在半导体衬底的内侧方向上连续延伸的腐蚀孔，形成在侵蚀孔的内表面上的氧化物膜和单晶部分。

29. 发明授权

US5773152A SOI substrate having a high heavy metal gettering effect for semiconductor device 失效
标题翻译：对于半导体器件具有高重金属吸气效应的SOI衬底
公开(公告)号：US5773152A
公开(公告)日：1998-06-30
申请号：US543068
申请日：1995-10-13
申请人： Kensuke Okonogi
发明人： Kensuke Okonogi
IPC分类号： H01L21/02 , H01L21/322 , H01L21/76 , H01L27/12 , H01L29/786 , B32B9/04
CPC分类号： H01L21/3226 , H01L29/78603
摘要： An SOI substrate comprises a buried silicon oxide layer formed directly under an active silicon layer, and a layer containing phosphorus therein formed under the buried silicon oxide layer. The layer containing phosphorus therein acts as the getter layer, so that an effective gettering of heavy metals can be obtained in a wide temperature range from a low temperature region to a high temperature region. In addition, since the silicon oxide layer exists between the active layer and the getter layer, the diffusion of the phosphorus into the active layer is effectively prevented, and therefore, the phosphorus scarely diffuses to the active layer, so that the device manufactured is subjected to almost no adverse influence of the diffusion of the phosphorus.
摘要翻译： SOI衬底包括直接在有源硅层下面形成的掩埋氧化硅层，以及在掩埋氧化硅层下形成含有磷的层。其中含有磷的层用作吸气剂层，从而在从低温区域到高温区域的宽温度范围内可以获得重金属的有效吸除。此外，由于氧化硅层存在于有源层和吸气层之间，因此有效地防止了磷向有源层的扩散，因此，磷被有害地扩散到有源层，使得制造的器件受到影响对磷的扩散几乎没有不利影响。

30. 发明授权

US08674455B2 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US08674455B2
公开(公告)日：2014-03-18
申请号：US13334964
申请日：2011-12-22
申请人： Kensuke Okonogi , Kazuhiro Nojima , Kiyonori Oyu
发明人： Kensuke Okonogi , Kazuhiro Nojima , Kiyonori Oyu
IPC分类号： H01L29/76 , H01L29/94
CPC分类号： H01L21/823892 , H01L27/0928 , H01L27/10873
摘要： A semiconductor device is provided, which includes an N well having a peak concentration of 2E+17 atom/cm3 or more in the range of 0.2 to 1 μm depth from the surface of a P-type semiconductor substrate, and a region provided below the N well, the region containing P-type impurities with higher concentration than concentration of electrons.
摘要翻译：提供一种半导体器件，其包括从P型半导体衬底的表面开始的深度为0.2至1μm的峰值浓度为2E + 17原子/ cm 3或更大的N阱，以及设置在P型半导体衬底的下方的区域 N阱，该区域含有比电子浓度高的P型杂质。

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