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21. 发明申请

US20090101979A1 Methods of Forming Field Effect Transistors Having Stress-Inducing Sidewall Insulating Spacers Thereon and Devices Formed Thereby 有权
标题翻译：形成具有应力诱导侧壁绝缘垫片的场效应晶体管的方法和由此形成的器件
公开(公告)号：US20090101979A1
公开(公告)日：2009-04-23
申请号：US11874118
申请日：2007-10-17
申请人： Jun-jung Kim , Sang-jine Park , Min-ho Lee , Thomas W. Dyer , Sunfei Fang , O-sung Kwon , Johnny Widodo
发明人： Jun-jung Kim , Sang-jine Park , Min-ho Lee , Thomas W. Dyer , Sunfei Fang , O-sung Kwon , Johnny Widodo
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L29/7833 , H01L29/665 , H01L29/6653 , H01L29/7843
摘要： Methods of forming integrated circuit devices include forming a field effect transistor having a gate electrode, a sacrificial spacer on a sidewall of the gate electrode and silicided source/drain regions. The sacrificial spacer is used as an implantation mask when forming highly doped portions of the source/drain regions. The sacrificial spacer is then removed from the sidewall of the gate electrode. A stress-inducing electrically insulating layer, which is configured to induce a net tensile stress (for NMOS transistors) or compressive stress (for PMOS transistors) in a channel region of the field effect transistor, is then formed on the sidewall of the gate electrode.
摘要翻译：形成集成电路器件的方法包括形成具有栅电极的场效应晶体管，栅电极的侧壁上的牺牲隔离物和硅化源/漏区。当形成源极/漏极区域的高掺杂部分时，牺牲间隔物用作注入掩模。然后从栅电极的侧壁去除牺牲隔离物。然后，在栅电极的侧壁上形成应力诱导电绝缘层，其被配置为在场效应晶体管的沟道区域中引起净拉伸应力（用于NMOS晶体管）或压应力（用于PMOS晶体管）。

22. 发明申请

US20090050972A1 Strained Semiconductor Device and Method of Making Same 审中-公开
标题翻译：应变半导体器件及其制造方法
公开(公告)号：US20090050972A1
公开(公告)日：2009-02-26
申请号：US11841516
申请日：2007-08-20
申请人： Richard Lindsay , Shyue Seng Tan , Joo-Chan Kim , Jun Jung Kim , Hyung-Yoon Choi , Chung Woh Lai , Johnny Widodo
发明人： Richard Lindsay , Shyue Seng Tan , Joo-Chan Kim , Jun Jung Kim , Hyung-Yoon Choi , Chung Woh Lai , Johnny Widodo
IPC分类号： H01L21/768 , H01L23/48 , H01L21/336 , H01L29/78
CPC分类号： H01L29/7843 , H01L21/28518 , H01L21/76834 , H01L21/76843 , H01L21/76855 , H01L21/823807 , H01L21/823871 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： A method of making a semiconductor device is disclosed. A semiconductor body, a gate electrode and source/drain regions are provided. A liner is provided that covers the gate electrode and the source/drain regions. Silicide regions are formed on the semiconductor device by etching a contact hole through the liner.
摘要翻译：公开了制造半导体器件的方法。提供半导体本体，栅极电极和源极/漏极区域。提供覆盖栅极电极和源极/漏极区域的衬垫。通过蚀刻通过衬套的接触孔，在半导体器件上形成硅化物区域。

23. 发明申请

US20080090412A1 Pre-silicide spacer removal 失效
标题翻译：预硅化物间隔物去除
公开(公告)号：US20080090412A1
公开(公告)日：2008-04-17
申请号：US11548842
申请日：2006-10-12
申请人： Thomas W. Dyer , Sunfei Fang , Jiang Yan , Jun Jung Kim , Yaocheng Liu , Huilong Zhu
发明人： Thomas W. Dyer , Sunfei Fang , Jiang Yan , Jun Jung Kim , Yaocheng Liu , Huilong Zhu
IPC分类号： H01L21/44
CPC分类号： H01L29/665 , H01L21/32 , H01L29/6653 , H01L29/66545 , H01L29/6659
摘要： A method forms a gate conductor over a substrate, and simultaneously forms spacers on sides of the gate conductor and a gate cap on the top of the gate conductor. Isolation regions are formed in the substrate and the method implants an impurity into exposed regions of the substrate not protected by the gate conductor and the spacers to form source and drain regions. The method deposits a mask over the gate conductor, the spacers, and the source and drain regions. The mask is recessed to a level below a top of the gate conductor but above the source and drain regions, such that the spacers are exposed and the source and drain regions are protected by the mask. With the mask in place, the method then safely removes the spacers and the gate cap, without damaging the source/drain regions or the isolation regions (which are protected by the mask). Next, the method removes the mask and then forms silicide regions on the gate conductor and the source and drain regions.
摘要翻译：一种方法在衬底上形成栅极导体，同时在栅极导体的侧面和栅极导体的顶部上形成栅极盖。在衬底中形成隔离区域，并且该方法将杂质注入未被栅极导体和间隔物保护的衬底的暴露区域中以形成源区和漏区。该方法在栅极导体，间隔物以及源极和漏极区域上沉积掩模。掩模凹陷到栅极导体的顶部下方但在源极和漏极区域之上的水平面，使得间隔物被暴露，并且源极和漏极区域被掩模保护。在掩模就位的情况下，该方法然后安全地去除间隔物和栅极盖，而不损坏源极/漏极区域或隔离区域（被掩模保护）。接下来，该方法移除掩模，然后在栅极导体和源极和漏极区域上形成硅化物区域。

24. 发明授权

US10229876B2 Wiring structures and semiconductor devices 有权
公开(公告)号：US10229876B2
公开(公告)日：2019-03-12
申请号：US15073640
申请日：2016-03-17
申请人： Jun-Jung Kim , Young-Bae Kim , Jong-Sam Kim , Jin-Hyeung Park , Jeong-Hoon Ahn , Hyeok-Sang Oh , Kyoung-Woo Lee , Hyo-Seon Lee , Suk-Hee Jang
发明人： Jun-Jung Kim , Young-Bae Kim , Jong-Sam Kim , Jin-Hyeung Park , Jeong-Hoon Ahn , Hyeok-Sang Oh , Kyoung-Woo Lee , Hyo-Seon Lee , Suk-Hee Jang
IPC分类号： H01L23/535 , H01L23/528 , H01L23/522 , H01L27/088 , H01L23/532 , H01L21/768 , H01L21/8234 , H01L23/485
摘要： A wiring structure includes a substrate, a lower insulation layer on the substrate, a lower wiring in the lower insulation layer, a first etch-stop layer covering the lower wiring and including a metallic dielectric material, a second etch-stop layer on the first etch-stop layer and the lower insulation layer, an insulating interlayer on the second etch-stop layer, and a conductive pattern extending through the insulating interlayer, the second etch-stop layer and the first etch-stop layer and electrically connected to the lower wiring.

25. 发明授权

US07923365B2 Methods of forming field effect transistors having stress-inducing sidewall insulating spacers thereon 有权
标题翻译：在其上形成具有应力诱导侧壁绝缘间隔物的场效应晶体管的方法
公开(公告)号：US07923365B2
公开(公告)日：2011-04-12
申请号：US11874118
申请日：2007-10-17
申请人： Jun-jung Kim , Sang-jine Park , Min-ho Lee , Thomas W. Dyer , Sunfei Fang , O-sung Kwon , Johnny Widodo
发明人： Jun-jung Kim , Sang-jine Park , Min-ho Lee , Thomas W. Dyer , Sunfei Fang , O-sung Kwon , Johnny Widodo
IPC分类号： H01L21/8234 , H01L21/336
CPC分类号： H01L29/7833 , H01L29/665 , H01L29/6653 , H01L29/7843
摘要： Methods of forming integrated circuit devices include forming a field effect transistor having a gate electrode, a sacrificial spacer on a sidewall of the gate electrode and silicided source/drain regions. The sacrificial spacer is used as an implantation mask when forming highly doped portions of the source/drain regions. The sacrificial spacer is then removed from the sidewall of the gate electrode. A stress-inducing electrically insulating layer, which is configured to induce a net tensile stress (for NMOS transistors) or compressive stress (for PMOS transistors) in a channel region of the field effect transistor, is then formed on the sidewall of the gate electrode.
摘要翻译：形成集成电路器件的方法包括形成具有栅电极的场效应晶体管，栅电极的侧壁上的牺牲隔离物和硅化源/漏区。当形成源极/漏极区域的高掺杂部分时，牺牲间隔物用作注入掩模。然后从栅电极的侧壁去除牺牲隔离物。然后，在栅电极的侧壁上形成应力诱导电绝缘层，其被配置为在场效应晶体管的沟道区域中引起净拉伸应力（用于NMOS晶体管）或压应力（用于PMOS晶体管）。

26. 发明申请

US20080237737A1 OVERLAPPED STRESSED LINERS FOR IMPROVED CONTACTS 失效
标题翻译：用于改进联系人的超重压力衬管
公开(公告)号：US20080237737A1
公开(公告)日：2008-10-02
申请号：US11693254
申请日：2007-03-29
申请人： Xiangdong Chen , Jun Jung Kim , Young Gun Ko , Jae-Eun Park , Haining S. Yang
发明人： Xiangdong Chen , Jun Jung Kim , Young Gun Ko , Jae-Eun Park , Haining S. Yang
IPC分类号： H01L29/76 , H01L21/8238
CPC分类号： H01L21/0217 , H01L21/02274 , H01L21/3185 , H01L21/823807 , H01L29/7843
摘要： A semiconductor structure is provided which includes a first semiconductor device in a first active semiconductor region and a second semiconductor device in a second active semiconductor region. A first dielectric liner overlies the first semiconductor device and a second dielectric liner overlies the second semiconductor device, with the second dielectric liner overlapping the first dielectric liner at an overlap region. The second dielectric liner has a first portion having a first thickness contacting an apex of the second gate conductor and a second portion extending from peripheral edges of the second gate conductor which has a second thickness substantially greater than the first thickness. A first conductive via contacts at least one of the first or second gate conductors and the conductive via extends through the first and second dielectric liners at the overlap region. A second conductive via may contact at least one of a source region or a drain region of the second semiconductor device.
摘要翻译：提供一种半导体结构，其包括第一有源半导体区域中的第一半导体器件和第二有源半导体区域中的第二半导体器件。第一电介质衬垫覆盖在第一半导体器件上，并且第二电介质衬垫覆盖在第二半导体器件上，第二电介质衬垫在重叠区域与第一电介质衬垫重叠。第二电介质衬垫具有第一部分，第一部分具有与第二栅极导体的顶点接触的第一厚度和从第二栅极导体的周边边延伸的第二部分，第二部分具有基本上大于第一厚度的第二厚度。第一导电通孔接触第一或第二栅极导体和导电通孔中的至少一个延伸穿过第一和第二电介质衬垫在重叠区域。第二导电通孔可以接触第二半导体器件的源极区域或漏极区域中的至少一个。

27. 发明申请

US20070082439A1 Semiconductor device having a dual stress liner, method of manufacturing the semiconductor device and light exposure apparatus for forming the dual stress liner 有权
标题翻译：具有双应力衬垫的半导体器件，半导体器件的制造方法和用于形成双重应力衬垫的曝光装置
公开(公告)号：US20070082439A1
公开(公告)日：2007-04-12
申请号：US11246471
申请日：2005-10-07
申请人： Jae-Eon Park , Ja-Hum Ku , Jun-Jung Kim , Dae-Kwon Kang , Young Teh
发明人： Jae-Eon Park , Ja-Hum Ku , Jun-Jung Kim , Dae-Kwon Kang , Young Teh
IPC分类号： H01L21/8238 , H01L29/788
CPC分类号： H01L21/823807 , H01L21/0217 , H01L21/02274 , H01L21/268 , H01L21/3185 , H01L21/823814 , H01L21/823835 , H01L21/823864 , H01L29/7843
摘要： In a semiconductor device having a dual stress liner for improving electron mobility, the dual stress liner includes a first liner portion formed on a PMOSFET and a second liner portion formed on an NMOSFET. The first liner portion has a first compressive stress, and the second liner portion has a second compressive stress smaller than the first compressive stress. The dual stress liner may be formed by forming a stress liner on a semiconductor substrate on which the PMOSFET and the NMOSFET are formed and selectively exposing a portion of the stress liner on the NMOSFET.
摘要翻译：在具有用于改善电子迁移率的双应力衬垫的半导体器件中，双应力衬垫包括形成在PMOSFET上的第一衬垫部分和形成在NMOSFET上的第二衬垫部分。第一衬里部分具有第一压缩应力，并且第二衬套部分具有小于第一压缩应力的第二压缩应力。双应力衬垫可以通过在其上形成PMOSFET和NMOSFET的半导体衬底上形成应力衬垫而形成，并且选择性地暴露在NMOSFET上的应力衬垫的一部分。

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