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    • 23. 发明申请
    • Pre-silicide spacer removal
    • 预硅化物间隔物去除
    • US20080090412A1
    • 2008-04-17
    • US11548842
    • 2006-10-12
    • Thomas W. DyerSunfei FangJiang YanJun Jung KimYaocheng LiuHuilong Zhu
    • Thomas W. DyerSunfei FangJiang YanJun Jung KimYaocheng LiuHuilong Zhu
    • H01L21/44
    • H01L29/665H01L21/32H01L29/6653H01L29/66545H01L29/6659
    • A method forms a gate conductor over a substrate, and simultaneously forms spacers on sides of the gate conductor and a gate cap on the top of the gate conductor. Isolation regions are formed in the substrate and the method implants an impurity into exposed regions of the substrate not protected by the gate conductor and the spacers to form source and drain regions. The method deposits a mask over the gate conductor, the spacers, and the source and drain regions. The mask is recessed to a level below a top of the gate conductor but above the source and drain regions, such that the spacers are exposed and the source and drain regions are protected by the mask. With the mask in place, the method then safely removes the spacers and the gate cap, without damaging the source/drain regions or the isolation regions (which are protected by the mask). Next, the method removes the mask and then forms silicide regions on the gate conductor and the source and drain regions.
    • 一种方法在衬底上形成栅极导体,同时在栅极导体的侧面和栅极导体的顶部上形成栅极盖。 在衬底中形成隔离区域,并且该方法将杂质注入未被栅极导体和间隔物保护的衬底的暴露区域中以形成源区和漏区。 该方法在栅极导体,间隔物以及源极和漏极区域上沉积掩模。 掩模凹陷到栅极导体的顶部下方但在源极和漏极区域之上的水平面,使得间隔物被暴露,并且源极和漏极区域被掩模保护。 在掩模就位的情况下,该方法然后安全地去除间隔物和栅极盖,而不损坏源极/漏极区域或隔离区域(被掩模保护)。 接下来,该方法移除掩模,然后在栅极导体和源极和漏极区域上形成硅化物区域。
    • 26. 发明申请
    • OVERLAPPED STRESSED LINERS FOR IMPROVED CONTACTS
    • 用于改进联系人的超重压力衬管
    • US20080237737A1
    • 2008-10-02
    • US11693254
    • 2007-03-29
    • Xiangdong ChenJun Jung KimYoung Gun KoJae-Eun ParkHaining S. Yang
    • Xiangdong ChenJun Jung KimYoung Gun KoJae-Eun ParkHaining S. Yang
    • H01L29/76H01L21/8238
    • H01L21/0217H01L21/02274H01L21/3185H01L21/823807H01L29/7843
    • A semiconductor structure is provided which includes a first semiconductor device in a first active semiconductor region and a second semiconductor device in a second active semiconductor region. A first dielectric liner overlies the first semiconductor device and a second dielectric liner overlies the second semiconductor device, with the second dielectric liner overlapping the first dielectric liner at an overlap region. The second dielectric liner has a first portion having a first thickness contacting an apex of the second gate conductor and a second portion extending from peripheral edges of the second gate conductor which has a second thickness substantially greater than the first thickness. A first conductive via contacts at least one of the first or second gate conductors and the conductive via extends through the first and second dielectric liners at the overlap region. A second conductive via may contact at least one of a source region or a drain region of the second semiconductor device.
    • 提供一种半导体结构,其包括第一有源半导体区域中的第一半导体器件和第二有源半导体区域中的第二半导体器件。 第一电介质衬垫覆盖在第一半导体器件上,并且第二电介质衬垫覆盖在第二半导体器件上,第二电介质衬垫在重叠区域与第一电介质衬垫重叠。 第二电介质衬垫具有第一部分,第一部分具有与第二栅极导体的顶点接触的第一厚度和从第二栅极导体的周边边延伸的第二部分,第二部分具有基本上大于第一厚度的第二厚度。 第一导电通孔接触第一或第二栅极导体和导电通孔中的至少一个延伸穿过第一和第二电介质衬垫在重叠区域。 第二导电通孔可以接触第二半导体器件的源极区域或漏极区域中的至少一个。