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21. 发明授权

US5831303A Field effect transistor utilizing the gate structure two-dimensionally 失效
标题翻译：利用二极管结构的场效应晶体管
公开(公告)号：US5831303A
公开(公告)日：1998-11-03
申请号：US679343
申请日：1996-07-10
申请人： Juha Rapeli
发明人： Juha Rapeli
IPC分类号： H01L29/43 , H01L29/78 , H01L29/788
CPC分类号： H01L29/7831 , H01L29/435
摘要： The object of the invention is a field-effect transistor comprising a drain (D) and a source (S) and a gate (G) with a determined width (W) and length (L), equipped with means (G1-G2) for generating a voltage distribution on the gate in direction of its width. The gate comprises a first end in direction of its width and a second end essentially opposite to the first end, and that a first gate contact (G1) is arranged at the first end for providing a first voltage (V.sub.G1) to the first end, and a second gate contact (G2) is arranged at the second end for providing a second voltage (V.sub.G2) to the second end, for generating a voltage distribution on the gate in direction of its width with the help of a difference voltage (V.sub.G1 -V.sub.G2) between the first (G1) and the second (G2) gate contact. On the basis of the first (V.sub.G1) and second (V.sub.G2) voltage, a determined common-mode voltage is obtained on the gate, by which the voltage level of the gate is adjusted, and the difference voltage can be used for the adjustment of the voltage distribution in the width direction of the gate. In addition, a third gate contact (G3) can be arranged on the gate for generating a determined potential (V.sub.G3) as a common voltage evenly over the entire gate area. As an output (I.sub.DS), a signal proportional to the product of the difference voltage (V.sub.G1 -V.sub.G2) and common-mode voltage is obtained from the field-effect transistor thereby forming a multiplier.
摘要翻译：本发明的目的是一种场效应晶体管，其包括具有确定的宽度（W）和长度（L）的漏极（D）和源极（S）和栅极（G），其具有装置（G1-G2）用于在栅极的宽度方向上产生电压分布。栅极包括其宽度方向的第一端和基本上与第一端相对的第二端，并且在第一端设置第一栅极接触（G1），以向第一端提供第一电压（VG1）并且在所述第二端处布置第二栅极触点（G2），用于向所述第二端提供第二电压（VG2），用于借助于差分电压（VG1）来在栅极的宽度方向上产生电压分布 VG2）在第一（G1）和第二（G2）门接触之间。在第一（VG1）和第二（VG2）电压的基础上，在栅极上获得确定的共模电压，通过该电压调节栅极的电压电平，并且差分电压可用于调整栅极宽度方向的电压分布。此外，可以在栅极上布置第三栅极触点（G3），以在整个栅极区域上均匀地产生作为公共电压的确定电位（VG3）。作为输出（IDS），从场效应晶体管获得与差分电压（VG1-VG2）和共模电压的乘积成比例的信号，从而形成乘法器。

22. 发明授权

US5732108A Method and apparatus for producing a difference signal between two signal frequencies, and for detection of modulation 失效
标题翻译：用于在两个信号频率之间产生差分信号并用于检测调制的方法和装置
公开(公告)号：US5732108A
公开(公告)日：1998-03-24
申请号：US521640
申请日：1995-08-31
申请人： Juha Rapeli , Kari Kananen
发明人： Juha Rapeli , Kari Kananen
IPC分类号： H03D3/00 , H03D7/00 , H03D7/16 , H03D3/18
CPC分类号： H03D7/00 , H03D2200/0052 , H03D2200/007 , H03D3/006 , H03D7/161
摘要： A frequency difference signal of a modulated signal (f.sub.1) and an unmodulated signal (f.sub.2) is produced maintaining the information of the frequency or phase modulation. According to the method, the time-related order of entry of the front edges of the pulses of the modulated and the unmodulated signal is controlled and the edge of the frequency difference signal in question at any moment is formed timewise at the same point as the edge of such modulated signal at which the time-related order of arrival of the modulating signal and the unmodulated signal has changed. Hereby, the frequency or phase shift of the modulated signal can be detected as an equivalent change in the frequency difference signal, and the modulation of the frequency difference signal is detected on the basis of the location of the pulse edge of the frequency difference signal.
摘要翻译：产生调制信号（f1）和未调制信号（f2）的频差信号，维持频率或相位调制的信息。根据该方法，控制调制信号和未调制信号的脉冲的前沿的时间相关顺序，并且在任何时刻所讨论的频差信号的边缘在时间上形成在与调制信号和未调制信号的到达时间相关顺序已经改变的这种调制信号的边沿。因此，调制信号的频率或相移可以被检测为频差信号的等效变化，并且基于频差信号的脉冲边缘的位置来检测频差信号的调制。

23. 发明授权

US5325075A Method and circuit arrangement to generate a phase modulated or frequency modulated signal 失效
标题翻译：用于产生相位调制或调频信号的方法和电路装置
公开(公告)号：US5325075A
公开(公告)日：1994-06-28
申请号：US997285
申请日：1992-12-23
申请人： Juha Rapeli
发明人： Juha Rapeli
IPC分类号： H03C3/00 , H03C3/09 , H04L27/20 , H04L27/36 , H03L7/18 , H03L7/22
CPC分类号： H03C3/0975 , H03C3/0925 , H03C3/0933 , H03C3/0941 , H03C3/0966
摘要： The invention relates to a method, in which a phase modulated or frequency modulated signal can be directly generated with a PLL frequency synthesizer. With an interpolating synthesizer it is possible to create a very dense output frequency (f.sub.x) raster, so that the pulses received in the phase comparator (63) both from the reference signal (f.sub.o) branch and from the voltage controlled oscillator VCO (65) are lengthened in lengthening means (62, 69; 67, 68; k.sub.1, L+.DELTA.L; k.sub.2, L) by a desired amount. The numbers k.sub.1 and k.sub.2 are proportional to the amount of lengthening. When these integers now further are changed proportionally to the modulating signal, the change of the integers causes a change of the time difference of the pulses received by the phase comparator (63). This change of the time difference further causes a change in the output signal (f.sub.x) of the voltage controlled oscillator. The method is particularly well suited to provide digital quadrature phase modulation QPSK or quadrature amplitude modulation QAM, in which the shift from one carrier phase to another has a predetermined size and waveform as a function of time.
摘要翻译：本发明涉及一种可以用PLL频率合成器直接产生相位调制或调频信号的方法。通过内插合成器，可以创建非常密集的输出频率（fx）光栅，使得从参考信号（fo）支路和压控振荡器VCO（65）中接收的脉冲在相位比较器（63）中接收，延长装置（62,69; 67,68; k1，L + DELTA L; k2，L）期望量。数字k1和k2与延长量成比例。当这些整数现在进一步与调制信号成比例地变化时，整数的改变引起由相位比较器（63）接收的脉冲的时间差的变化。时间差的这种变化进一步导致压控振荡器的输出信号（fx）的变化。该方法特别适用于提供数字正交相位调制QPSK或正交幅度调制QAM，其中从一个载波相位到另一个载波相位的移位具有作为时间的函数的预定大小和波形。

24. 发明授权

US5079520A Interpolating phase-locked loop frequency synthesizer 失效
标题翻译：插入相位锁定频率合成器
公开(公告)号：US5079520A
公开(公告)日：1992-01-07
申请号：US638130
申请日：1991-01-07
申请人： Juha Rapeli
发明人： Juha Rapeli
IPC分类号： H03L7/183 , H03L7/197
CPC分类号： H03L7/1974
摘要： The invention concerns are interpolating frequency synthesizer based on digital phase locking, with which frequencies can be produced which lie between frequencies defined by integer divisors. Traditional frequency synthesizers employ frequency dividers in which the dividing ratio is an integer. The circuit of the invention comprises member (8, 9), in one of which the reference frequency (f.sub.o) or the VCO frequency (f.sub.x), or the frequency obtained from them by division, is multiplied with a coefficient L and in the other member the corresponding frequency is multiplied by L+ .DELTA.L; and members (2, 7), in which the first pulses going to the phase detector (3) are lengthened by a time corresponding to a given integer number k1 of pulses formed in the number (8), and the other pulses are lengthened by a time corresponding to a given integer number k2 of pulses formed in the member (9).

25. 发明授权

US4408170A Component with trimmable electric impedance 失效
标题翻译：组件具有可调电阻抗
公开(公告)号：US4408170A
公开(公告)日：1983-10-04
申请号：US315533
申请日：1981-10-23
申请人： Juha Rapeli , Seppo Leppavuori
发明人： Juha Rapeli , Seppo Leppavuori
IPC分类号： H01P1/20 , H01C10/16 , H01C17/23 , H01L27/01 , H03H1/02 , H03H7/06 , H03H3/00
CPC分类号： H01C10/16 , H01C17/23 , H01L27/016 , H03H1/02 , Y10T29/49099
摘要： An electric component is disclosed with trimmable complex resistive-capacitive impedance comprising a first resistor layer forming a ground plane, an insulation layer connected thereover and a second resistor layer connected over the insulation layer. The second resistor layer is divided into a plurality of resistor layer portions. The resistor layer has one edge which is attached to a power drive connector and an opposite edge which is step shaped so that the resistor layer portions are varied both in length and in width. The resistor layer portions are selectively connected and disconnected from each other to produce a desired impedance value.
摘要翻译： PCT No.PCT / FI81 / 00017 Sec。 371日期：1981年10月23日 102（e）1981年10月23日日期PCT提交1981年3月11日PCT公布。出版物WO81 / 02652 公开了一种电子部件，其具有包括形成接地平面的第一电阻层，连接在其上的绝缘层和连接在绝缘层上的第二电阻层的可修整的复阻抗电阻阻抗。第二电阻层被分成多个电阻层部分。电阻层具有附接到功率驱动连接器的一个边缘和阶梯形的相对边缘，使得电阻器层部分的长度和宽度都变化。电阻层部分被选择性地连接和断开，以产生所需的阻抗值。

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