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21. 发明授权

US5084594A Multiwire cable 失效
标题翻译：多线电缆
公开(公告)号：US5084594A
公开(公告)日：1992-01-28
申请号：US563487
申请日：1990-08-07
申请人： James W. Cady , John P. Barr, Jr.
发明人： James W. Cady , John P. Barr, Jr.
IPC分类号： H01B7/08 , H01B7/17 , H01B11/00
CPC分类号： H01B7/0861 , H01B7/083 , H01B7/0892
摘要： A low cost high signal frequency multiwire cable and method of manufacture includes a stack of wire pairs fan folded from a flat ribbon cable to form columnated wire pair layers. The flat ribbon cable is folded together with a flexible conductive shield which extends around and between each layer to provide high quality signal isolation of each layer. The cable may be clad with multiple layers providing additional shielding and physical protection.
摘要翻译：低成本的高信号频率多线电缆及其制造方法包括从扁平带状电缆折叠的线对风扇的叠层，以形成柱状线对层。扁平带状电缆与柔性导电屏蔽件折叠在一起，每个层之间和之间延伸，以提供每层的高质量信号隔离。电缆可以包覆多层，提供额外的屏蔽和物理保护。

22. 发明申请

US20090273069A1 LOW PROFILE CHIP SCALE STACKING SYSTEM AND METHOD 审中-公开
标题翻译：低剖面芯片尺寸堆叠系统和方法
公开(公告)号：US20090273069A1
公开(公告)日：2009-11-05
申请号：US12437340
申请日：2009-05-07
申请人： James W. Cady , Julian Partridge , James Douglas Wehrly, JR. , James Wilder
发明人： James W. Cady , Julian Partridge , James Douglas Wehrly, JR. , James Wilder
IPC分类号： H01L23/50
CPC分类号： H05K1/141 , H01L23/3114 , H01L23/49816 , H01L23/49827 , H01L23/4985 , H01L23/5387 , H01L25/0657 , H01L25/105 , H01L2224/16225 , H01L2224/16237 , H01L2224/32225 , H01L2224/73253 , H01L2224/81801 , H01L2225/06517 , H01L2225/06541 , H01L2225/06579 , H01L2225/06586 , H01L2225/107 , H01L2924/01322 , H01L2924/19041 , H01L2924/3011 , H05K1/147 , H05K1/189 , H05K3/363 , H05K2201/056 , H05K2201/10689 , H05K2201/10734 , Y10T29/49126 , Y10T29/49144
摘要： The present invention stacks chip scale-packaged integrated circuits (CSPs) into low profile modules that conserve PWB or other board surface area. Low profile structures provide connection between CSPs of the stacked module and between and to the flex circuitry. Low profile contacts are created by any of a variety of methods and materials including, for example, screen paste techniques and use of high temperature solders, although other application techniques and traditional solders may be employed for creating low profile contacts in the present invention. A consolidated low profile contact structure and technique is provided for use in alternative embodiments of the present invention. The CSPs employed in stacked modules devised in accordance with the present invention are connected with flex circuitry. That flex circuitry may exhibit one or two or more conductive layers. In some preferred embodiments, a form standard provides a physical form that allows many of the varying package sizes found in the broad family of CSP packages to be used to advantage while employing a standard connective flex circuitry design. In other embodiments, a heat spreader is disposed between the CSP and the flex circuitry thus providing an improved heat transference function without the standardization of the form standard, while still other embodiments lack either a form standard or a heat spreader and may employ, for example, the flex circuitry as a heat transference material.
摘要翻译：本发明将芯片级封装集成电路（CSP）堆叠成保留PWB或其他板表面积的低轮廓模块。薄型结构提供堆叠模块的CSP之间和柔性电路之间的连接。薄型触点由各种方法和材料中的任何一种产生，包括例如丝网糊技术和高温焊料的使用，尽管其它应用技术和传统焊料可用于在本发明中制造低轮廓触点。提供了一种合并的低轮廓接触结构和技术，用于本发明的替代实施例。根据本发明设计的堆叠模块中采用的CSP与柔性电路连接。该柔性电路可以表现出一个或两个或更多个导电层。在一些优选实施例中，形式标准提供了一种物理形式，其允许在采用标准连接柔性电路设计的同时，在广泛的CSP封装系列中发现许多变化的封装尺寸。在其他实施例中，散热器设置在CSP和柔性电路之间，从而提供改进的热传递功能，而不需要形式标准的标准化，而其它实施例还没有形式标准或散热器，并且可以采用例如，柔性电路作为热转移材料。

23. 发明授权

US07606050B2 Compact module system and method 有权
标题翻译：紧凑型模块系统和方法
公开(公告)号：US07606050B2
公开(公告)日：2009-10-20
申请号：US11187269
申请日：2005-07-22
申请人： James W. Cady , James Douglas Wehrly, Jr. , Paul Goodwin
发明人： James W. Cady , James Douglas Wehrly, Jr. , Paul Goodwin
IPC分类号： H05K7/00
CPC分类号： H05K1/189 , H05K2201/056 , H05K2201/10159 , H05K2201/10189
摘要： A flexible circuit is populated on one or both sides and disposed about a substrate to create a circuit module. Along one of its edges, the flex circuit is connected to a connective facility such as a multiple pin connector while the flex circuit is disposed about a thermally-conductive form that provides structure to create a module with plural layers of circuitry in a single module. In preferred embodiments, the form is metallic and, in alternative preferred embodiments, the module circuitry is disposed within a housing. Preferred embodiments may be devised that present a compact flash module within a housing that may be connected to or into a system or product through a connective facility that is preferably a male or female socket connector while the housing is configured to mechanically adapt to an application environment.
摘要翻译：柔性电路填充在一侧或两侧并且设置在基板周围以形成电路模块。沿着其边缘之一，柔性电路连接到诸如多针连接器的连接设备，而柔性电路围绕导热形式设置，其提供结构以在单个模块中创建具有多层电路的模块。在优选实施例中，该形式是金属的，并且在替代优选实施例中，模块电路设置在壳体内。可以设计出优选实施例，其在壳体内呈现紧凑型闪光模块，其可以通过连接设备连接到系统或产品，该连接设备优选地是公插座或母插座连接器，而壳体被配置为机械地适应应用环境。

24. 发明授权

US07602613B2 Thin module system and method 有权
标题翻译：薄模块系统和方法
公开(公告)号：US07602613B2
公开(公告)日：2009-10-13
申请号：US11624608
申请日：2007-01-18
申请人： Paul Goodwin , James W. Cady , Douglas Wehrly
发明人： Paul Goodwin , James W. Cady , Douglas Wehrly
IPC分类号： H05K1/00
CPC分类号： H01L25/0652 , G11C5/04 , G11C5/143 , H01L25/105 , H01L2924/0002 , H05K1/0203 , H05K1/118 , H05K1/181 , H05K1/189 , H05K3/0061 , H05K2201/056 , H05K2201/1056 , H05K2201/10734 , H05K2201/2018 , H05K2203/1572 , H01L2924/00
摘要： A flexible circuit has contacts for mounting in a socket or card edge connector. The flexible circuit includes integrated circuit devices mounted on both sides of the edge connector contacts. Preferably, the flexible circuit is wrapped about an edge of a rigid substrate and presents contacts on both sides of the substrate for mounting in a socket. Multiple flexible circuits may be overlaid with the same strategy. The flexible circuit may exhibit one or two or more conductive layers, and may have changes in the layered structure or have split layers.
摘要翻译：柔性电路具有用于安装在插座或卡缘连接器中的触点。柔性电路包括安装在边缘连接器触头两侧的集成电路器件。优选地，柔性电路围绕刚性基板的边缘缠绕，并且在基板的两侧上提供用于安装在插座中的触点。可以用相同的策略覆盖多个柔性电路。柔性电路可以表现出一个或两个或更多个导电层，并且可能具有分层结构的变化或具有分裂层。

25. 发明申请

US20090124045A1 Low Profile Stacking System and Method 有权
标题翻译：薄型堆叠系统和方法
公开(公告)号：US20090124045A1
公开(公告)日：2009-05-14
申请号：US12356432
申请日：2009-01-20
申请人： Julian Partridge , James W. Cady , James Wilder , David L. Roper , James Douglas Wehrly, JR.
发明人： Julian Partridge , James W. Cady , James Wilder , David L. Roper , James Douglas Wehrly, JR.
IPC分类号： H01L21/50
CPC分类号： H01L25/0657 , H01L23/3114 , H01L23/49816 , H01L23/49827 , H01L23/4985 , H01L23/5387 , H01L24/13 , H01L24/16 , H01L24/81 , H01L25/105 , H01L2224/13 , H01L2224/13099 , H01L2224/13111 , H01L2224/13116 , H01L2224/16237 , H01L2224/73253 , H01L2224/81011 , H01L2224/81191 , H01L2224/81192 , H01L2224/81193 , H01L2224/8121 , H01L2224/81815 , H01L2225/06517 , H01L2225/06541 , H01L2225/06579 , H01L2225/06586 , H01L2225/107 , H01L2924/01005 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01049 , H01L2924/0105 , H01L2924/01051 , H01L2924/01075 , H01L2924/01078 , H01L2924/01082 , H01L2924/014 , H01L2924/1305 , H01L2924/14 , H01L2924/15311 , H01L2924/19041 , H01L2924/3011 , H05K1/141 , H05K1/147 , H05K1/189 , H05K3/3463 , H05K3/363 , H05K2201/056 , H05K2201/10689 , H05K2201/10734 , H01L2924/00
摘要： The present invention provides a system and method that mounts integrated circuit devices onto substrates and a system and method for employing the method in stacked modules. The contact pads of a packaged integrated circuit device are substantially exposed. A solder paste that includes higher temperature solder paste alloy is applied to a substrate or to the integrated circuit device to be mounted. The integrated circuit device is positioned to contact the contacts of the substrate. Heat is applied to create high temperature joints between the contacts of the substrate and the integrated circuit device resulting in a device-substrate assembly with high temperature joints. The formed joints are less subject to re-melting in subsequent processing steps. The method may be employed in devising stacked module constructions such as those disclosed herein as preferred embodiments in accordance with the invention. Typically, the created joints are low in profile.
摘要翻译：本发明提供了一种将集成电路器件安装到衬底上的系统和方法，以及用于将堆叠模块中采用该方法的系统和方法。封装的集成电路器件的接触焊盘基本上露出。将包括较高温度的焊膏合金的焊膏施加到要安装的基板或集成电路器件上。集成电路器件定位成与衬底的触点接触。施加热量以在基板的触点和集成电路装置之间形成高温接头，从而形成具有高温接头的装置 - 基板组件。形成的接头在随后的加工步骤中较少受到再熔化。该方法可以用于设计堆叠的模块结构，例如根据本发明的优选实施例中公开的那些。通常，创建的关节的轮廓较低。

26. 发明授权

US07180167B2 Low profile stacking system and method 失效
标题翻译：薄型堆叠系统和方法
公开(公告)号：US07180167B2
公开(公告)日：2007-02-20
申请号：US11011469
申请日：2004-12-14
申请人： Julian Partridge , James W. Cady , James Wilder , David L. Roper , James Douglas Wehrly, Jr.
发明人： Julian Partridge , James W. Cady , James Wilder , David L. Roper , James Douglas Wehrly, Jr.
IPC分类号： H01L23/02
CPC分类号： H01L25/0657 , H01L23/3114 , H01L23/49816 , H01L23/49827 , H01L23/4985 , H01L23/5387 , H01L24/13 , H01L24/16 , H01L24/81 , H01L25/105 , H01L2224/13 , H01L2224/13099 , H01L2224/13111 , H01L2224/13116 , H01L2224/16237 , H01L2224/73253 , H01L2224/81011 , H01L2224/81191 , H01L2224/81192 , H01L2224/81193 , H01L2224/8121 , H01L2224/81815 , H01L2225/06517 , H01L2225/06541 , H01L2225/06579 , H01L2225/06586 , H01L2225/107 , H01L2924/01005 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01049 , H01L2924/0105 , H01L2924/01051 , H01L2924/01075 , H01L2924/01078 , H01L2924/01082 , H01L2924/014 , H01L2924/1305 , H01L2924/14 , H01L2924/15311 , H01L2924/19041 , H01L2924/3011 , H05K1/141 , H05K1/147 , H05K1/189 , H05K3/3463 , H05K3/363 , H05K2201/056 , H05K2201/10689 , H05K2201/10734 , H01L2924/00
摘要： The present invention provides a system and method that mounts integrated circuit devices onto substrates and a system and method for employing the method in stacked modules. The contact pads of a packaged integrated circuit device are substantially exposed. A solder paste that includes higher temperature solder paste alloy is applied to a substrate or to the integrated circuit device to be mounted. The integrated circuit device is positioned to contact the contacts of the substrate. Heat is applied to create high temperature joints between the contacts of the substrate and the integrated circuit device resulting in a device-substrate assembly with high temperature joints. The formed joints are less subject to re-melting in subsequent processing steps. The method may be employed in devising stacked module constructions such as those disclosed herein as preferred embodiments in accordance with the invention. Typically, the created joints are low in profile.
摘要翻译：本发明提供了一种将集成电路器件安装到衬底上的系统和方法，以及用于将堆叠模块中采用该方法的系统和方法。封装的集成电路器件的接触焊盘基本上露出。将包括较高温度的焊膏合金的焊膏施加到要安装的基板或集成电路器件上。集成电路器件定位成与衬底的触点接触。施加热量以在基板的触点和集成电路装置之间形成高温接头，从而形成具有高温接头的装置 - 基板组件。形成的接头在随后的加工步骤中较少受到再熔化。该方法可以用于设计堆叠的模块结构，例如根据本发明的优选实施例中公开的那些。通常，创建的关节的轮廓较低。

27. 发明授权

US07026708B2 Low profile chip scale stacking system and method 失效
标题翻译：薄型芯片级堆叠系统及方法
公开(公告)号：US07026708B2
公开(公告)日：2006-04-11
申请号：US10631886
申请日：2003-07-11
申请人： James W. Cady , Julian Partridge , James Douglas Wehrly, Jr. , James Wilder , David L. Roper , Jeff Buchle
发明人： James W. Cady , Julian Partridge , James Douglas Wehrly, Jr. , James Wilder , David L. Roper , Jeff Buchle
IPC分类号： H01L23/488 , H05K1/14
CPC分类号： H05K1/141 , H01L23/3114 , H01L23/49816 , H01L23/49827 , H01L23/4985 , H01L23/5387 , H01L25/0657 , H01L25/105 , H01L2224/16225 , H01L2224/16237 , H01L2224/32225 , H01L2224/73253 , H01L2224/81801 , H01L2225/06517 , H01L2225/06541 , H01L2225/06579 , H01L2225/06586 , H01L2225/107 , H01L2924/01322 , H01L2924/19041 , H01L2924/3011 , H05K1/147 , H05K1/189 , H05K3/363 , H05K2201/056 , H05K2201/10689 , H05K2201/10734 , Y10T29/49126 , Y10T29/49144
摘要： The present invention stacks chip scale-packaged integrated circuits (CSPs) into low profile modules that conserve PWB or other board surface area. Low profile contacts are created by any of a variety of methods and materials. A consolidated low profile contact structure and technique is provided for use in alternative embodiments of the present invention. Multiple numbers of CSPs may be stacked in accordance with the present invention. The CSPs employed in stacked modules devised in accordance with the present invention are connected with flex circuitry that exhibit one or two or more conductive layers.
摘要翻译：本发明将芯片级封装集成电路（CSP）堆叠成保留PWB或其他板表面积的低轮廓模块。薄型触点由各种方法和材料中的任何一种制成。提供了一种合并的低轮廓接触结构和技术，用于本发明的替代实施例。根据本发明可以堆叠多个CSP。根据本发明设计的堆叠模块中采用的CSP与展现一个或两个或更多个导电层的柔性电路连接。

28. 发明授权

US06940729B2 Integrated circuit stacking system and method 有权
标题翻译：集成电路堆叠系统及方法
公开(公告)号：US06940729B2
公开(公告)日：2005-09-06
申请号：US10136890
申请日：2002-05-02
申请人： James W. Cady , James Wilder , David L. Roper , Russell Rapport , James Douglas Wehrly, Jr. , Jeffrey Alan Buchle
发明人： James W. Cady , James Wilder , David L. Roper , Russell Rapport , James Douglas Wehrly, Jr. , Jeffrey Alan Buchle
IPC分类号： H01L23/31 , H01L23/498 , H01L23/538 , H01L25/065 , H01L25/10 , H05K1/14 , H05K1/18 , H05K3/36 , H05K7/10 , H05K7/12
CPC分类号： H01L23/49816 , H01L23/3114 , H01L23/49827 , H01L23/4985 , H01L23/5387 , H01L25/0657 , H01L25/105 , H01L2224/16225 , H01L2224/16237 , H01L2224/32145 , H01L2224/32225 , H01L2224/32245 , H01L2224/73204 , H01L2224/73253 , H01L2225/06517 , H01L2225/06541 , H01L2225/06579 , H01L2225/06586 , H01L2225/107 , H01L2225/1094 , H01L2924/19041 , H01L2924/3011 , H05K1/141 , H05K1/147 , H05K1/189 , H05K3/363 , H05K2201/056 , H05K2201/10689 , H05K2201/10734 , H01L2924/00012
摘要： The present invention stacks packaged integrated circuits into modules that conserve PWB or other board surface area. The invention provides techniques and structures for aggregating chip scale-packaged integrated circuits (CSPs) or leaded packages with other CSPs or with monolithic or stacked leaded packages into modules that conserve PWB or other board surface area. The present invention can be used to advantage with CSP or leaded packages of a variety of sizes and configurations ranging from larger packaged base elements having many dozens of contacts to smaller packages such as, for example, die-sized packages such as DSBGA. In a preferred embodiment devised in accordance with the present invention, a base element IC and a support element IC are aggregated through a flex circuit having at least two conductive layers that are patterned to selectively connect the two IC elements. A portion of the flex circuit connected to the support element is folded over the base element to dispose the support element above the base element while reducing the overall footprint occupied by the two ICs. The flex circuit connects the ICs and provides a thermal and electrical connection path between the module and an application environment such as a printed wiring board (PWB). The present invention may be employed to advantage in numerous configurations and combinations in modules provided for high-density memories, high capacity computing, or applications where small size is valued.
摘要翻译：本发明将封装的集成电路堆叠成节省PWB或其他板表面积的模块。本发明提供了用于将芯片级封装集成电路（CSP）或具有其他CSP的引线封装或者将单片或堆叠引线封装集成到节省PWB或其他板表面积的模块中的技术和结构。本发明可以用于具有各种尺寸和配置的CSP或带引线的封装，其范围从具有许多触点的较大封装的基底元件到较小的封装，例如诸如管芯尺寸的封装（例如DSBGA）。在根据本发明设计的优选实施例中，基体元件IC和支撑元件IC通过具有图案化以选择性地连接两个IC元件的至少两个导电层的柔性电路聚集。连接到支撑元件的柔性电路的一部分折叠在基座元件上，以将支撑元件设置在基座元件上方，同时减少两个IC所占据的总占地面积。柔性电路连接IC，并在模块和诸如印刷电路板（PWB）的应用环境之间提供热和电连接路径。本发明可用于为高密度存储器，高容量计算或小尺寸的应用提供的模块中的多种配置和组合中的优点。

29. 发明授权

US06914324B2 Memory expansion and chip scale stacking system and method 有权
公开(公告)号：US06914324B2
公开(公告)日：2005-07-05
申请号：US10453398
申请日：2003-06-03
申请人： Russell Rapport , James W. Cady , James Wilder , David L. Roper , James Douglas Wehrly, Jr. , Jeff Buchle
发明人： Russell Rapport , James W. Cady , James Wilder , David L. Roper , James Douglas Wehrly, Jr. , Jeff Buchle
IPC分类号： H01L21/44 , H01L23/31 , H01L23/498 , H01L23/50 , H01L23/538 , H01L25/065 , H01L25/10 , H05K1/14 , H05K1/18 , H05K3/36 , H01L23/02
CPC分类号： H01L23/3114 , H01L23/49816 , H01L23/49827 , H01L23/49838 , H01L23/4985 , H01L23/50 , H01L23/5387 , H01L25/0657 , H01L25/105 , H01L2224/16237 , H01L2224/73253 , H01L2225/06517 , H01L2225/06541 , H01L2225/06579 , H01L2225/06586 , H01L2225/107 , H01L2924/00014 , H01L2924/01055 , H01L2924/15173 , H01L2924/15311 , H01L2924/19041 , H01L2924/3011 , H05K1/141 , H05K1/147 , H05K1/189 , H05K3/363 , H05K2201/056 , H05K2201/10689 , H05K2201/10734 , H01L2224/0401
摘要： The present invention stacks chip scale-packaged integrated circuits (CSPs) into modules that conserve PWB or other board surface area. In another aspect, the invention provides a lower capacitance memory expansion addressing system and method and preferably with the CSP stacked modules provided herein. In a preferred embodiment in accordance with the invention, a form standard is disposed between the flex circuitry and the IC package over which a portion of the flex circuitry is laid. The form standard provides a physical form that allows many of the varying package sizes found in the broad family of CSP packages to be used to advantage while employing a standard connective flex circuitry design. In a preferred embodiment, the form standard will be devised of heat transference material such as copper to improve thermal performance. In a preferred embodiment, a high speed switching system selects a data line associated with each level of a stacked module to reduce the loading effect upon data signals in memory access. This favorably changes the impedance characteristics exhibited by a DIMM board populated with stacked modules. In a preferred embodiment, FET multiplexers for example, under logic control select particular data lines associated with particular levels of stacked modules populated upon a DIMM for connection to a controlling chip set in a memory expansion system.

30. 发明授权

US06404662B1 Rambus stakpak 失效
公开(公告)号：US06404662B1
公开(公告)日：2002-06-11
申请号：US09646724
申请日：2001-03-07
申请人： James W. Cady , Russell Rapport
发明人： James W. Cady , Russell Rapport
IPC分类号： G11C506
CPC分类号： G11C5/06 , G11C5/02 , G11C5/04 , H01L25/105 , H01L2225/1029 , H01L2225/1064 , H01L2225/107 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： The RAMBUS compatible configuration of the present invention is achieved by stacking one of the two modules in the stacked configuration in an upside-down position with respect to the other. This way, the corresponding electrical leads of each memory module will extend on opposite sides of the stacked package and will be securably connected to vertical rails. The vertical rails are electrically and securably connected to the bonding pads which electrically connect to the RAMBUS signal channel. In this embodiment, the electrical leads of one memory module electrically connect to the signal channel at points located on one side of the stacked package and the electrical leads of the other memory module connect to the signal channel at points located on the opposite side of the stacked package. The resulting distance between the points of contact between corresponding leads of each memory module in the stacked package is sufficient to satisfy the requirements of the RAMBUS signal channel. Therefore, two memory modules can be vertically stacked to achieve higher memory density and thereby conserve board space.
摘要翻译：本发明的RAMBUS兼容配置通过以相对于另一个的上下颠倒的方式堆叠在层叠结构中的两个模块之一来实现。这样，每个存储器模块的相应的电引线将在堆叠封装的相对侧上延伸，并且将牢固地连接到垂直导轨。垂直导轨电连接到电连接到RAMBUS信号通道的接合焊盘。在该实施例中，一个存储器模块的电引线在位于堆叠封装的一侧的点处电连接到信号通道，另一存储器模块的电引线在位于该堆叠封装的相对侧上的点处连接到信号通道堆叠包装。层叠包装中的每个存储器模块的相应引线之间的所得接触点之间的距离足以满足RAMBUS信号通道的要求。因此，可以将两个存储器模块垂直堆叠以实现更高的存储器密度，从而节省电路板空间。

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