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21. 发明授权

US06841549B1 Condensed imidazole compounds and a therapeutic agent for diabetes mellitus 失效
标题翻译：缩合咪唑化合物和糖尿病治疗剂
公开(公告)号：US06841549B1
公开(公告)日：2005-01-11
申请号：US10018688
申请日：2000-06-30
申请人： Osamu Asano , Hitoshi Harada , Seiji Yoshikawa , Nobuhisa Watanabe , Takashi Inoue , Tatsuo Horizoe , Nobuyuki Yasuda , Kaya Ohashi , Hiroe Minami , Junsaku Nagaoka , Manabu Murakami , Seiichi Kobayashi , Isao Tanaka , Tsutomu Kawata , Naoyuki Shimomura , Hiroshi Akamatsu , Naoki Ozeki , Toshikazu Shimizu , Kenji Hayashi , Toyokazu Haga , Shigeto Negi , Toshihiko Naito
发明人： Osamu Asano , Hitoshi Harada , Seiji Yoshikawa , Nobuhisa Watanabe , Takashi Inoue , Tatsuo Horizoe , Nobuyuki Yasuda , Kaya Ohashi , Hiroe Minami , Junsaku Nagaoka , Manabu Murakami , Seiichi Kobayashi , Isao Tanaka , Tsutomu Kawata , Naoyuki Shimomura , Hiroshi Akamatsu , Naoki Ozeki , Toshikazu Shimizu , Kenji Hayashi , Toyokazu Haga , Shigeto Negi , Toshihiko Naito
IPC分类号： A61P3/10 , A61P43/00 , C07D471/04 , C07D473/00 , C07D473/34 , C07D473/40 , A16K31/33 , C07D239/70 , C07D471/00 , C07D487/00 , A16K31/52
CPC分类号： C07D471/04 , C07D473/00 , C07D473/34 , C07D473/40
摘要： The present invention provides a preventive or therapeutic agent for diabetes mellitus and diabetic complications, which is a new type based on an adenosine A2 receptor antagonist action.That is, it provides a novel condensed imidazole compound which has an adenosine A2 receptor antagonist action, is effective for preventing or treating diabetes mellitus and diabetic complications, and is represented by the formula (I); (wherein R1 represents e.g. an amino group which may be substituted with an alkyl group; R2 represents e.g. hydrogen atom, an alkyl group, a cycloalkyl group or an alkyl group, alkenyl group or alkynyl group which may be substituted with hydrox etc.; R3 represents e.g. an optionally substituted alkyl group, alkenyl group, alkynyl group, aryl group, heteroaryl group, pyridinone group, pyrimidinone group or piperadinone group; Ar represents e.g. an optionally substituted aryl or heteroaryl group; and Q and W are the same as or different from each other and each represents N or CH), a pharmacologically acceptable salt or hydrates thereof.
摘要翻译：本发明提供了一种基于腺苷A2受体拮抗剂作用的新型糖尿病和糖尿病并发症的预防或治疗剂。即提供了具有腺苷A2受体拮抗剂作用的新颖的缩合咪唑化合物，是有效预防或治疗糖尿病和糖尿病并发症，并由式（I）表示;（其中R 1表示例如可被烷基取代的氨基; R 2表示例如氢原子，可以被羟基取代的烷基，环烷基或烷基，烯基或炔基; R 3表示例如任选取代的烷基，烯基，炔基，芳基，杂芳基，吡啶酮基，嘧啶酮基或哌嗪酮基; Ar表示例如任选取代的芳基或杂芳基; Q和W彼此相同或不同，每个代表 N或CH），其药理学上可接受的盐或其水合物。

22. 发明授权

US6163177A Semiconductor integrated circuit device having output buffer 失效
标题翻译：具有输出缓冲器的半导体集成电路器件
公开(公告)号：US6163177A
公开(公告)日：2000-12-19
申请号：US219781
申请日：1998-12-23
申请人： Motoko Hara , Hiroshi Akamatsu , Yutaka Ikeda
发明人： Motoko Hara , Hiroshi Akamatsu , Yutaka Ikeda
IPC分类号： G11C11/417 , G11C11/407 , G11C11/409 , H03K19/017 , H03K19/0175 , H03B1/00 , H03K3/00
CPC分类号： H03K19/01721
摘要： An output buffer includes an NAND circuit, a first N channel MOS transistor connected between a power supply node and an output node, a second N channel MOS transistor connected between the output node and a ground node, the first to third drive circuits, and a delay circuit. The power supply voltage is first supplied to the gate of the second N channel MOS transistor by the second drive circuit. After a delay time delayed by the delay circuit has passed, boosted voltage is supplied to the gate of the second N channel MOS transistor by the third drive circuit. Accordingly, the output buffer is not influenced by the ringing and the pull-down characteristic improves.
摘要翻译：输出缓冲器包括NAND电路，连接在电源节点和输出节点之间的第一N沟道MOS晶体管，连接在输出节点和接地节点之间的第二N沟道MOS晶体管，第一至第三驱动电路和延时电路。电源电压首先通过第二驱动电路提供给第二N沟道MOS晶体管的栅极。在延迟电路延迟的延迟时间过去之后，由第三驱动电路向第二N沟道MOS晶体管的栅极提供升压电压。因此，输出缓冲器不受振铃影响，并且下拉特性提高。

23. 发明授权

US5659260A Sense amplifier having a circuit for compensating for potential voltage drops caused by parasitic interconnections 失效
标题翻译：感测放大器具有用于补偿由寄生互连引起的潜在电压降的电路
公开(公告)号：US5659260A
公开(公告)日：1997-08-19
申请号：US602521
申请日：1996-02-20
申请人： Takeshi Kajimoto , Hiroshi Akamatsu
发明人： Takeshi Kajimoto , Hiroshi Akamatsu
IPC分类号： G11C11/409 , G05F1/577 , G11C5/14 , G11C11/401 , G11C11/407 , G11C11/4091 , G01R19/00
CPC分类号： G11C5/145 , G05F1/577 , G11C11/4091
摘要： A negative power supply circuit is connected via an NMOS transistor to a node receiving ground potential in a sense amplifier. A one shot pulse generation circuit provides a one shot pulse signal to the gate of the NMOS transistor. The NMOS transistor is turned on when a one shot pulse signal is applied to connect the negative power supply circuit to the node. This causes the potential of the node to be lowered to a negative potential. As a result, increase in the potential at the ground side of the sense amplifier caused by an interconnection resistance in the ground interconnection is suppressed. Therefore, variation in the potential received by the sense amplifier due to interconnection resistance can be suppressed.
摘要翻译：负电源电路通过NMOS晶体管连接到读出放大器中接收地电位的节点。单脉冲发生电路向NMOS晶体管的栅极提供单触发脉冲信号。当施加单触发脉冲信号以将负电源电路连接到节点时，NMOS晶体管导通。这导致节点的电位降低到负电位。结果，由于接地互连中的互连电阻引起的感测放大器的接地侧的电位的增加被抑制。因此，可以抑制由于互连电阻而由读出放大器接收的电位的变化。

24. 发明申请

US20120250435A1 SEMICONDUCTOR DEVICE AND METHOD OF COTNROLING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20120250435A1
公开(公告)日：2012-10-04
申请号：US13431412
申请日：2012-03-27
申请人： Kinu MATSUNAGA , Hiroshi AKAMATSU
发明人： Kinu MATSUNAGA , Hiroshi AKAMATSU
IPC分类号： G11C7/12 , G11C7/00
CPC分类号： G11C7/12 , G11C7/222 , G11C11/401 , G11C11/4094 , G11C29/16
摘要： A device includes a command decoder that is configured to output, in a normal operation mode, a precharge signal in response to a first type transition edge of a synchronous signal, and an active signal in response to a next first type transition edge that is next to the first type transition edge. The command decoder is configured to output, in a test mode, the precharge signal in response to a second type transition edge of the synchronous signal, and the active signal in response to a next first type transition edge that is next to the second type transition edge.
摘要翻译：一种设备包括命令解码器，其被配置为在正常操作模式下响应于同步信号的第一类型转换边缘输出预充电信号，并响应于下一个第一类型转换边缘而输出下一个到第一类型的过渡边缘。命令解码器被配置为在测试模式下响应于同步信号的第二类型转换边沿而输出预充电信号，并且响应于接下来的第二类型转换的下一个第一类型转换边缘来输出有效信号边缘。

25. 发明授权

US07791402B2 Electric fuse determination circuit and determination method 有权
标题翻译：电熔丝确定电路及测定方法
公开(公告)号：US07791402B2
公开(公告)日：2010-09-07
申请号：US12289588
申请日：2008-10-30
申请人： Hiroshi Akamatsu
发明人： Hiroshi Akamatsu
IPC分类号： H01H37/76
CPC分类号： G11C17/18
摘要： An electrical fuse determination circuit that can speedily and reliably incorporate an electrical fuse data and improve a reliability of electrical fuse device, includes a first electrical fuse device of which one end connects with a higher voltage, a second electrical fuse device of which one end connects with a lower voltage, a set portion that puts one of the first electrical fuse device and the second electrical fuse device in a conductive state, and a determination portion that determines a voltage level of a predetermined contact point connecting the other end of the first electrical fuse device and the other end of the second electrical fuse device.
摘要翻译：一种可快速可靠地并入电熔丝数据并提高电熔丝装置的可靠性的电熔丝确定电路，包括一端与较高电压连接的第一电熔丝装置，一端连接的第二电熔丝装置具有较低的电压，将第一电熔丝装置和第二电熔丝装置中的一个置于导通状态的设定部分，以及确定部分，其确定连接第一电熔丝装置和第二电熔丝装置的另一端的预定接触点的电压电平保险丝装置和第二电熔丝装置的另一端。

26. 发明授权

US06728149B2 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US06728149B2
公开(公告)日：2004-04-27
申请号：US10269062
申请日：2002-10-11
申请人： Hiroshi Akamatsu
发明人： Hiroshi Akamatsu
IPC分类号： G11C700
CPC分类号： G11C29/785 , G11C29/24
摘要： A spare address conversion circuit makes an address assignment to spare sub word lines different from the address assignment to normal sub word lines between a mode of data writing and a mode of data reading. Data are written such that opposite data patterns are stored in spare word lines before and after address conversion. When a multi-selection occurs, there is data collision on the corresponding bit lines, so that the multi-selection can be detected without fail.
摘要翻译：备用地址转换电路进行地址分配，以在数据写入模式和数据读取模式之间对与通常子字线的地址分配不同的子字线进行备用。数据被写入，使得相反的数据模式存储在地址转换之前和之后的备用字线中。当进行多重选择时，在相应的位线上存在数据冲突，从而可以无故障地检测多选。

27. 发明授权

US06304503B1 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US06304503B1
公开(公告)日：2001-10-16
申请号：US09238916
申请日：1999-01-28
申请人： Hiroshi Akamatsu , Masanori Hayashikoshi
发明人： Hiroshi Akamatsu , Masanori Hayashikoshi
IPC分类号： G11C700
CPC分类号： G11C29/14
摘要： The semiconductor memory device in accordance with the present invention allows evaluation of input/output terminal dependency of noise characteristic at the time of data output, it has a normal operation mode and a test mode, and includes a plurality of output at buffers and selecting means for selectively activating at least one output buffer among the plurality of output buffers in the test mode.
摘要翻译：根据本发明的半导体存储器件允许在数据输出时评估噪声特性的输入/输出端子依赖性，它具有正常操作模式和测试模式，并且包括在缓冲器处的多个输出和选择装置用于在测试模式中选择性地激活多个输出缓冲器中的至少一个输出缓冲器。

28. 发明授权

US06222781B1 Semiconductor integrated circuit device capable of externally applying power supply potential to internal circuit while restricting noise 失效
标题翻译：半导体集成电路器件能够在限制噪声的同时向内部电路外部施加电源电位
公开(公告)号：US06222781B1
公开(公告)日：2001-04-24
申请号：US09549934
申请日：2000-04-14
申请人： Yasuhiro Matsumoto , Hiroshi Akamatsu
发明人： Yasuhiro Matsumoto , Hiroshi Akamatsu
IPC分类号： G11C1604
CPC分类号： G11C29/12 , G11C5/14 , G11C5/147
摘要： An external terminal and an internal power supply node to an internal circuit are connected via first and second transistors. In a test operation mode, the first and second transisters are turned on and potential is accordingly supplied to the internal circuit from the terminal. In a normal operation mode, a third transistor placed between the terminal and the gate of the first transistor is turned on so that the gate of the first transistor is coupled to the external terminal and the second transistor is turned off. Undershoot to the terminal is not transmitted to the inside since the first transistor is turned off.
摘要翻译：通过第一和第二晶体管连接到内部电路的外部端子和内部电源节点。在测试操作模式中，第一和第二转换器被接通，并且电位被相应地从终端提供给内部电路。在正常操作模式中，放置在第一晶体管的端子和栅极之间的第三晶体管导通，使得第一晶体管的栅极耦合到外部端子，并且第二晶体管截止。由于第一晶体管关闭，到端子的下端不会传输到内部。

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